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adding new performance counters (banks utilization and DRAM bus utilization)

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This commit is contained in:
Blaise Tine
2020-12-22 12:33:45 -08:00
parent 4b7d871d62
commit d956e268b9
14 changed files with 426 additions and 439 deletions
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103
hw/rtl/VX_config.vh
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@@ -167,63 +167,64 @@
// Machine Performance-monitoring counters
// PERF: pipeline
`define CSR_MPM_ICACHE_ST 12'hB03
`define CSR_MPM_ICACHE_ST_H 12'hB83
`define CSR_MPM_IBUF_ST 12'hB04
`define CSR_MPM_IBUF_ST_H 12'hB84
`define CSR_MPM_SCRB_ST 12'hB05
`define CSR_MPM_SCRB_ST_H 12'hB85
`define CSR_MPM_ALU_ST 12'hB06
`define CSR_MPM_ALU_ST_H 12'hB86
`define CSR_MPM_LSU_ST 12'hB07
`define CSR_MPM_LSU_ST_H 12'hB87
`define CSR_MPM_CSR_ST 12'hB08
`define CSR_MPM_CSR_ST_H 12'hB88
`define CSR_MPM_MUL_ST 12'hB09
`define CSR_MPM_MUL_ST_H 12'hB89
`define CSR_MPM_FPU_ST 12'hB0A
`define CSR_MPM_FPU_ST_H 12'hB8A
`define CSR_MPM_GPU_ST 12'hB0B
`define CSR_MPM_GPU_ST_H 12'hB8B
`define CSR_MPM_IBUF_ST 12'hB03
`define CSR_MPM_IBUF_ST_H 12'hB83
`define CSR_MPM_SCRB_ST 12'hB04
`define CSR_MPM_SCRB_ST_H 12'hB84
`define CSR_MPM_ALU_ST 12'hB05
`define CSR_MPM_ALU_ST_H 12'hB85
`define CSR_MPM_LSU_ST 12'hB06
`define CSR_MPM_LSU_ST_H 12'hB86
`define CSR_MPM_CSR_ST 12'hB07
`define CSR_MPM_CSR_ST_H 12'hB87
`define CSR_MPM_MUL_ST 12'hB08
`define CSR_MPM_MUL_ST_H 12'hB88
`define CSR_MPM_FPU_ST 12'hB09
`define CSR_MPM_FPU_ST_H 12'hB89
`define CSR_MPM_GPU_ST 12'hB0A
`define CSR_MPM_GPU_ST_H 12'hB8A
// PERF: icache
`define CSR_MPM_ICACHE_MISS_R 12'hB0C // read misses
`define CSR_MPM_ICACHE_READS 12'hB0B // total reads
`define CSR_MPM_ICACHE_READS_H 12'hB8B
`define CSR_MPM_ICACHE_MISS_R 12'hB0C // total misses
`define CSR_MPM_ICACHE_MISS_R_H 12'hB8C
`define CSR_MPM_ICACHE_DREQ_ST 12'hB0D // dram request stalls
`define CSR_MPM_ICACHE_DREQ_ST_H 12'hB8D
`define CSR_MPM_ICACHE_PIPE_ST 12'hB0D // pipeline stalls
`define CSR_MPM_ICACHE_PIPE_ST_H 12'hB8D
`define CSR_MPM_ICACHE_CRSP_ST 12'hB0E // core response stalls
`define CSR_MPM_ICACHE_CRSP_ST_H 12'hB8E
`define CSR_MPM_ICACHE_MSHR_ST 12'hB0F // MSHR stalls
`define CSR_MPM_ICACHE_MSHR_ST_H 12'hB8F
`define CSR_MPM_ICACHE_PIPE_ST 12'hB10 // pipeline stalls
`define CSR_MPM_ICACHE_PIPE_ST_H 12'hB90
`define CSR_MPM_ICACHE_READS 12'hB11 // total reads
`define CSR_MPM_ICACHE_READS_H 12'hB91
// PERF: dcache
`define CSR_MPM_DCACHE_MISS_R 12'hB12 // read misses
`define CSR_MPM_DCACHE_MISS_R_H 12'hB92
`define CSR_MPM_DCACHE_MISS_W 12'hB13 // write misses
`define CSR_MPM_DCACHE_MISS_W_H 12'hB93
`define CSR_MPM_DCACHE_DREQ_ST 12'hB14 // dram request stalls
`define CSR_MPM_DCACHE_DREQ_ST_H 12'hB94
`define CSR_MPM_DCACHE_CRSP_ST 12'hB15 // core response stalls
`define CSR_MPM_DCACHE_CRSP_ST_H 12'hB95
`define CSR_MPM_DCACHE_MSHR_ST 12'hB16 // MSHR stalls
`define CSR_MPM_DCACHE_MSHR_ST_H 12'hB96
`define CSR_MPM_DCACHE_PIPE_ST 12'hB17 // pipeline stalls
`define CSR_MPM_DCACHE_PIPE_ST_H 12'hB97
`define CSR_MPM_DCACHE_READS 12'hB18 // total reads
`define CSR_MPM_DCACHE_READS_H 12'hB98
`define CSR_MPM_DCACHE_WRITES 12'hB19 // total writes
`define CSR_MPM_DCACHE_WRITES_H 12'hB99
`define CSR_MPM_DCACHE_EVICTS 12'hB1A // total evictions
`define CSR_MPM_DCACHE_EVICTS_H 12'hB9A
`define CSR_MPM_DCACHE_READS 12'hB0F // total reads
`define CSR_MPM_DCACHE_READS_H 12'hB8F
`define CSR_MPM_DCACHE_WRITES 12'hB10 // total writes
`define CSR_MPM_DCACHE_WRITES_H 12'hB90
`define CSR_MPM_DCACHE_MISS_R 12'hB11 // read misses
`define CSR_MPM_DCACHE_MISS_R_H 12'hB91
`define CSR_MPM_DCACHE_MISS_W 12'hB12 // write misses
`define CSR_MPM_DCACHE_MISS_W_H 12'hB92
`define CSR_MPM_DCACHE_BANK_ST 12'hB13 // bank conflicts stalls
`define CSR_MPM_DCACHE_BANK_ST_H 12'hB93
`define CSR_MPM_DCACHE_MSHR_ST 12'hB14 // MSHR stalls
`define CSR_MPM_DCACHE_MSHR_ST_H 12'hB94
`define CSR_MPM_DCACHE_PIPE_ST 12'hB15 // pipeline stalls
`define CSR_MPM_DCACHE_PIPE_ST_H 12'hB95
`define CSR_MPM_DCACHE_CRSP_ST 12'hB16 // core response stalls
`define CSR_MPM_DCACHE_CRSP_ST_H 12'hB96
// PERF: smem
`define CSR_MPM_SMEM_READS 12'hB17 // total reads
`define CSR_MPM_SMEM_READS_H 12'hB97
`define CSR_MPM_SMEM_WRITES 12'hB18 // total writes
`define CSR_MPM_SMEM_WRITES_H 12'hB98
`define CSR_MPM_SMEM_BANK_ST 12'hB19 // bank conflicts stalls
`define CSR_MPM_SMEM_BANK_ST_H 12'hB99
// PERF: memory
`define CSR_MPM_DRAM_LAT 12'hB1B // dram latency (total)
`define CSR_MPM_DRAM_LAT_H 12'hB9B
`define CSR_MPM_DRAM_REQ 12'hB1C // dram requests
`define CSR_MPM_DRAM_REQ_H 12'hB9C
`define CSR_MPM_DRAM_RSP 12'hB1D // dram responses
`define CSR_MPM_DRAM_RSP_H 12'hB9D
`define CSR_MPM_DRAM_READS 12'hB1A // dram reads
`define CSR_MPM_DRAM_READS_H 12'hB9A
`define CSR_MPM_DRAM_WRITES 12'hB1B // dram writes
`define CSR_MPM_DRAM_WRITES_H 12'hB9B
`define CSR_MPM_DRAM_ST 12'hB1C // dram request stalls
`define CSR_MPM_DRAM_ST_H 12'hB9C
`define CSR_MPM_DRAM_LAT 12'hB1D // dram latency (total)
`define CSR_MPM_DRAM_LAT_H 12'hB9D
// Machine Information Registers
`define CSR_MVENDORID 12'hF11