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block ram refactoring (multi-porting supporting and simulation support)

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This commit is contained in:
Blaise Tine
2021-08-26 08:19:44 -07:00
parent 06a6857508
commit d91d56d126
14 changed files with 480 additions and 353 deletions
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37
hw/rtl/VX_gpr_ram_f.v
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@@ -1,37 +0,0 @@
`include "VX_define.vh"
`TRACING_OFF
module VX_gpr_ram_f #(
parameter DATAW = 1,
parameter DEPTH = 1,
parameter ADDRW = $clog2(DEPTH)
) (
input wire clk,
input wire wren,
input wire [ADDRW-1:0] waddr,
input wire [DATAW-1:0] wdata,
input wire [ADDRW-1:0] raddr1,
input wire [ADDRW-1:0] raddr2,
input wire [ADDRW-1:0] raddr3,
output wire [DATAW-1:0] rdata1,
output wire [DATAW-1:0] rdata2,
output wire [DATAW-1:0] rdata3
);
reg [DATAW-1:0] mem [DEPTH-1:0];
initial mem = '{default: 0};
always @(posedge clk) begin
if (wren) begin
mem [waddr] <= wdata;
end
end
assign rdata1 = mem [raddr1];
assign rdata2 = mem [raddr2];
assign rdata3 = mem [raddr3];
endmodule
`TRACING_ON

34
hw/rtl/VX_gpr_ram_i.v
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@@ -1,34 +0,0 @@
`include "VX_define.vh"
`TRACING_OFF
module VX_gpr_ram_i #(
parameter DATAW = 1,
parameter DEPTH = 1,
parameter ADDRW = $clog2(DEPTH)
) (
input wire clk,
input wire wren,
input wire [ADDRW-1:0] waddr,
input wire [DATAW-1:0] wdata,
input wire [ADDRW-1:0] raddr1,
input wire [ADDRW-1:0] raddr2,
output wire [DATAW-1:0] rdata1,
output wire [DATAW-1:0] rdata2
);
reg [DATAW-1:0] mem [DEPTH-1:0];
initial mem = '{default: 0};
always @(posedge clk) begin
if (wren) begin
mem [waddr] <= wdata;
end
end
assign rdata1 = mem [raddr1];
assign rdata2 = mem [raddr2];
endmodule
`TRACING_ON

62
hw/rtl/VX_gpr_stage.v
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@@ -21,9 +21,9 @@ module VX_gpr_stage #(
wire write_enable = writeback_if.valid && (writeback_if.rd != 0); wire write_enable = writeback_if.valid && (writeback_if.rd != 0);
`ifdef EXT_F_ENABLE `ifdef EXT_F_ENABLE
localparam RAM_DEPTH = `NUM_WARPS * `NUM_REGS; localparam RAM_SIZE = `NUM_WARPS * `NUM_REGS;
wire [`NUM_THREADS-1:0][31:0] rdata1, rdata2, rdata3; wire [`NUM_THREADS-1:0][31:0] rdata1, rdata2, rdata3;
wire [$clog2(RAM_DEPTH)-1:0] waddr, raddr1, raddr2, raddr3; wire [$clog2(RAM_SIZE)-1:0] waddr, raddr1, raddr2, raddr3;
assign waddr = {writeback_if.wid, writeback_if.rd}; assign waddr = {writeback_if.wid, writeback_if.rd};
assign raddr1 = {gpr_req_if.wid, gpr_req_if.rs1}; assign raddr1 = {gpr_req_if.wid, gpr_req_if.rs1};
@@ -31,20 +31,20 @@ module VX_gpr_stage #(
assign raddr3 = {gpr_req_if.wid, gpr_req_if.rs3}; assign raddr3 = {gpr_req_if.wid, gpr_req_if.rs3};
for (genvar i = 0; i < `NUM_THREADS; i++) begin for (genvar i = 0; i < `NUM_THREADS; i++) begin
VX_gpr_ram_f #( VX_dp_ram #(
.DATAW (32), .RD_PORTS (3),
.DEPTH (RAM_DEPTH) .DATAW (32),
) gpr_ram_f ( .SIZE (RAM_SIZE),
.clk (clk), .INIT_ENABLE (1),
.wren (write_enable && writeback_if.tmask[i]), .INIT_VALUE (0)
.waddr (waddr), ) dp_ram (
.wdata (writeback_if.data[i]), .clk (clk),
.raddr1 (raddr1), .wren (write_enable && writeback_if.tmask[i]),
.raddr2 (raddr2), .waddr (waddr),
.raddr3 (raddr3), .wdata (writeback_if.data[i]),
.rdata1 (rdata1[i]), .rden (3'b111),
.rdata2 (rdata2[i]), .raddr ({raddr3, raddr2, raddr1}),
.rdata3 (rdata3[i]) .rdata ({rdata3[i], rdata2[i], rdata1[i]})
); );
end end
@@ -52,9 +52,9 @@ module VX_gpr_stage #(
assign gpr_rsp_if.rs2_data = rdata2; assign gpr_rsp_if.rs2_data = rdata2;
assign gpr_rsp_if.rs3_data = rdata3; assign gpr_rsp_if.rs3_data = rdata3;
`else `else
localparam RAM_DEPTH = `NUM_WARPS * `NUM_REGS; localparam RAM_SIZE = `NUM_WARPS * `NUM_REGS;
wire [`NUM_THREADS-1:0][31:0] rdata1, rdata2; wire [`NUM_THREADS-1:0][31:0] rdata1, rdata2;
wire [$clog2(RAM_DEPTH)-1:0] waddr, raddr1, raddr2; wire [$clog2(RAM_SIZE)-1:0] waddr, raddr1, raddr2;
assign waddr = {writeback_if.wid, writeback_if.rd}; assign waddr = {writeback_if.wid, writeback_if.rd};
assign raddr1 = {gpr_req_if.wid, gpr_req_if.rs1}; assign raddr1 = {gpr_req_if.wid, gpr_req_if.rs1};
@@ -62,18 +62,20 @@ module VX_gpr_stage #(
`UNUSED_VAR (gpr_req_if.rs3) `UNUSED_VAR (gpr_req_if.rs3)
for (genvar i = 0; i < `NUM_THREADS; i++) begin for (genvar i = 0; i < `NUM_THREADS; i++) begin
VX_gpr_ram_i #( VX_dp_ram #(
.DATAW (32), .RD_PORTS (2),
.DEPTH (RAM_DEPTH) .DATAW (32),
) gpr_ram_i ( .SIZE (RAM_SIZE),
.clk (clk), .INIT_ENABLE (1),
.wren (write_enable && writeback_if.tmask[i]), .INIT_VALUE (0)
.waddr (waddr), ) dp_ram (
.wdata (writeback_if.data[i]), .clk (clk),
.raddr1 (raddr1), .wren (write_enable && writeback_if.tmask[i]),
.raddr2 (raddr2), .waddr (waddr),
.rdata1 (rdata1[i]), .wdata (writeback_if.data[i]),
.rdata2 (rdata2[i]) .rden (2'b11),
.raddr ({raddr2, raddr1}),
.rdata ({rdata2[i], rdata1[i]})
); );
end end

19
hw/rtl/VX_icache_stage.v
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@@ -33,16 +33,17 @@ module VX_icache_stage #(
wire [`NUM_THREADS-1:0] rsp_tmask; wire [`NUM_THREADS-1:0] rsp_tmask;
VX_dp_ram #( VX_dp_ram #(
.DATAW(32 + `NUM_THREADS), .DATAW (32 + `NUM_THREADS),
.SIZE(`NUM_WARPS), .SIZE (`NUM_WARPS),
.FASTRAM(1) .LUTRAM (1)
) req_metadata ( ) req_metadata (
.clk(clk), .clk (clk),
.waddr(req_tag), .wren (icache_req_fire),
.raddr(rsp_tag), .waddr (req_tag),
.wren(icache_req_fire), .wdata ({ifetch_req_if.PC, ifetch_req_if.tmask}),
.din({ifetch_req_if.PC, ifetch_req_if.tmask}), .rden (1'b1),
.dout({rsp_PC, rsp_tmask}) .raddr (rsp_tag),
.rdata ({rsp_PC, rsp_tmask})
); );
`RUNTIME_ASSERT((!ifetch_req_if.valid || ifetch_req_if.PC >= `STARTUP_ADDR), `RUNTIME_ASSERT((!ifetch_req_if.valid || ifetch_req_if.PC >= `STARTUP_ADDR),

20
hw/rtl/VX_ipdom_stack.v
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@@ -38,17 +38,17 @@ module VX_ipdom_stack #(
end end
VX_dp_ram #( VX_dp_ram #(
.DATAW(WIDTH * 2), .DATAW (WIDTH * 2),
.SIZE(DEPTH), .SIZE (DEPTH),
.RWCHECK(1), .LUTRAM (1)
.FASTRAM(1)
) store ( ) store (
.clk(clk), .clk (clk),
.waddr(wr_ptr), .wren (push),
.raddr(rd_ptr), .waddr (wr_ptr),
.wren(push), .wdata ({q2, q1}),
.din({q2, q1}), .rden (1'b1),
.dout({d2, d1}) .raddr (rd_ptr),
.rdata ({d2, d1})
); );
always @(posedge clk) begin always @(posedge clk) begin

14
hw/rtl/cache/VX_data_access.v vendored
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@@ -65,14 +65,14 @@ module VX_data_access #(
VX_sp_ram #( VX_sp_ram #(
.DATAW (CACHE_LINE_SIZE * 8), .DATAW (CACHE_LINE_SIZE * 8),
.SIZE (`LINES_PER_BANK), .SIZE (`LINES_PER_BANK),
.BYTEENW (BYTEENW), .BYTEENW (BYTEENW)
.RWCHECK (1)
) data_store ( ) data_store (
.clk(clk), .clk (clk),
.addr(line_addr), .addr (line_addr),
.wren({BYTEENW{writeen}} & byte_enable), .wren ({BYTEENW{writeen}} & byte_enable),
.din(wdata), .wdata (wdata),
.dout(rdata) .rden (1'b1),
.rdata (rdata)
); );
`UNUSED_VAR (stall) `UNUSED_VAR (stall)

20
hw/rtl/cache/VX_miss_resrv.v vendored
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@@ -169,17 +169,17 @@ module VX_miss_resrv #(
`LINE_TO_BYTE_ADDR(addr_table[fill_id], BANK_ID), fill_id)) `LINE_TO_BYTE_ADDR(addr_table[fill_id], BANK_ID), fill_id))
VX_dp_ram #( VX_dp_ram #(
.DATAW (`MSHR_DATA_WIDTH), .DATAW (`MSHR_DATA_WIDTH),
.SIZE (MSHR_SIZE), .SIZE (MSHR_SIZE),
.RWCHECK (1), .LUTRAM (1)
.FASTRAM (1)
) entries ( ) entries (
.clk (clk), .clk (clk),
.waddr (allocate_id_r), .waddr (allocate_id_r),
.raddr (dequeue_id_r), .raddr (dequeue_id_r),
.wren (allocate_valid), .wren (allocate_valid),
.din (allocate_data), .wdata (allocate_data),
.dout (dequeue_data) .rden (1'b1),
.rdata (dequeue_data)
); );
assign allocate_ready = allocate_rdy_r; assign allocate_ready = allocate_rdy_r;

32
hw/rtl/cache/VX_shared_mem.v vendored
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@@ -173,14 +173,14 @@ module VX_shared_mem #(
VX_sp_ram #( VX_sp_ram #(
.DATAW (`WORD_WIDTH), .DATAW (`WORD_WIDTH),
.SIZE (`LINES_PER_BANK), .SIZE (`LINES_PER_BANK),
.BYTEENW (WORD_SIZE), .BYTEENW (WORD_SIZE)
.RWCHECK (1)
) data_store ( ) data_store (
.clk (clk), .clk (clk),
.addr (per_bank_core_req_addr[i]), .addr (per_bank_core_req_addr[i]),
.wren ({WORD_SIZE{wren}} & per_bank_core_req_byteen[i]), .wren ({WORD_SIZE{wren}} & per_bank_core_req_byteen[i]),
.din (per_bank_core_req_data[i]), .wdata (per_bank_core_req_data[i]),
.dout (per_bank_core_rsp_data[i]) .rden (1'b1),
.rdata (per_bank_core_rsp_data[i])
); );
end end
@@ -216,18 +216,19 @@ module VX_shared_mem #(
reg [NUM_REQS-1:0][`WORD_WIDTH-1:0] core_rsp_data_in; reg [NUM_REQS-1:0][`WORD_WIDTH-1:0] core_rsp_data_in;
reg [CORE_TAG_WIDTH-1:0] core_rsp_tag_in; reg [CORE_TAG_WIDTH-1:0] core_rsp_tag_in;
always @(*) begin always @(*) begin
core_rsp_valids_in = 0; core_rsp_tag_in = 'x;
core_rsp_data_in = 'x;
core_rsp_tag_in = 'x;
bank_rsp_sel_cur = 0;
for (integer i = NUM_BANKS-1; i >= 0; --i) begin for (integer i = NUM_BANKS-1; i >= 0; --i) begin
if (per_bank_req_reads[i] && ~bank_rsp_sel_prv[i]) begin if (per_bank_req_reads[i] && ~bank_rsp_sel_prv[i]) begin
core_rsp_tag_in = per_bank_core_req_tag[i]; core_rsp_tag_in = per_bank_core_req_tag[i];
end end
end end
end
always @(*) begin
core_rsp_valids_in = 0;
core_rsp_data_in = 'x;
bank_rsp_sel_cur = 0;
for (integer i = 0; i < NUM_BANKS; i++) begin for (integer i = 0; i < NUM_BANKS; i++) begin
if (per_bank_core_req_valid[i] if (per_bank_core_req_valid[i]
&& (core_rsp_tag_in[CORE_TAG_ID_BITS-1:0] == per_bank_core_req_tag[i][CORE_TAG_ID_BITS-1:0])) begin && (core_rsp_tag_in[CORE_TAG_ID_BITS-1:0] == per_bank_core_req_tag[i][CORE_TAG_ID_BITS-1:0])) begin
@@ -278,13 +279,16 @@ module VX_shared_mem #(
reg [CORE_TAG_WIDTH-1:0] core_req_tag_sel; reg [CORE_TAG_WIDTH-1:0] core_req_tag_sel;
`IGNORE_UNUSED_END `IGNORE_UNUSED_END
always @(*) begin always @(*) begin
core_req_tag_sel ='x; core_req_tag_sel ='x;
for (integer i = NUM_BANKS-1; i >= 0; --i) begin for (integer i = NUM_BANKS-1; i >= 0; --i) begin
if (per_bank_core_req_valid[i]) begin if (per_bank_core_req_valid[i]) begin
core_req_tag_sel = per_bank_core_req_tag[i]; core_req_tag_sel = per_bank_core_req_tag[i];
end end
end end
end
always @(*) begin
is_multi_tag_req = 0; is_multi_tag_req = 0;
for (integer i = 0; i < NUM_BANKS; ++i) begin for (integer i = 0; i < NUM_BANKS; ++i) begin
if (per_bank_core_req_valid[i] if (per_bank_core_req_valid[i]

15
hw/rtl/cache/VX_tag_access.v vendored
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@@ -48,14 +48,15 @@ module VX_tag_access #(
VX_sp_ram #( VX_sp_ram #(
.DATAW(`TAG_SELECT_BITS + 1), .DATAW(`TAG_SELECT_BITS + 1),
.SIZE(`LINES_PER_BANK), .SIZE(`LINES_PER_BANK),
.INITZERO(1), .INIT_ENABLE(1),
.RWCHECK(1) .INIT_VALUE(0)
) tag_store ( ) tag_store (
.clk(clk), .clk( clk),
.addr(line_addr), .addr (line_addr),
.wren(fill), .wren (fill),
.din({!is_flush, line_tag}), .wdata ({!is_flush, line_tag}),
.dout({read_valid, read_tag}) .rden (1'b1),
.rdata ({read_valid, read_tag})
); );
assign tag_match = read_valid && (line_tag == read_tag); assign tag_match = read_valid && (line_tag == read_tag);

274
hw/rtl/libs/VX_dp_ram.v
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@@ -2,178 +2,286 @@
`TRACING_OFF `TRACING_OFF
module VX_dp_ram #( module VX_dp_ram #(
parameter DATAW = 1, parameter RD_PORTS = 1,
parameter SIZE = 1, parameter DATAW = 1,
parameter BYTEENW = 1, parameter SIZE = 1,
parameter OUTPUT_REG = 0, parameter BYTEENW = 1,
parameter RWCHECK = 1, parameter OUTPUT_REG = 0,
parameter ADDRW = $clog2(SIZE), parameter NO_RWCHECK = 0,
parameter FASTRAM = 0, parameter ADDRW = $clog2(SIZE),
parameter INITZERO = 0 parameter LUTRAM = 0,
parameter INIT_ENABLE = 0,
parameter INIT_FILE = "",
parameter [DATAW-1:0] INIT_VALUE = 0
) ( ) (
input wire clk, input wire clk,
input wire [ADDRW-1:0] waddr, input wire [BYTEENW-1:0] wren,
input wire [ADDRW-1:0] raddr, input wire [ADDRW-1:0] waddr,
input wire [BYTEENW-1:0] wren, input wire [DATAW-1:0] wdata,
input wire [DATAW-1:0] din, input wire [RD_PORTS-1:0] rden,
output wire [DATAW-1:0] dout input wire [RD_PORTS-1:0][ADDRW-1:0] raddr,
output wire [RD_PORTS-1:0][DATAW-1:0] rdata
); );
`STATIC_ASSERT((1 == BYTEENW) || ((BYTEENW > 1) && 0 == (BYTEENW % 4)), ("invalid parameter")) `STATIC_ASSERT((1 == BYTEENW) || ((BYTEENW > 1) && 0 == (BYTEENW % 4)), ("invalid parameter"))
`STATIC_ASSERT(!LUTRAM || (RD_PORTS == 1), ("multi-porting not supported on LUTRAM"))
if (FASTRAM) begin
`define RAM_INITIALIZATION \
if (INIT_ENABLE) begin \
if (INIT_FILE != "") begin \
initial $readmemh(INIT_FILE, ram); \
end else begin \
initial ram = '{default: INIT_VALUE}; \
end \
end
`ifdef SYNTHESIS
if (LUTRAM) begin
if (OUTPUT_REG) begin if (OUTPUT_REG) begin
reg [DATAW-1:0] dout_r; reg [DATAW-1:0] rdata_r;
if (BYTEENW > 1) begin if (BYTEENW > 1) begin
`USE_FAST_BRAM reg [BYTEENW-1:0][7:0] mem [SIZE-1:0]; `USE_FAST_BRAM reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
if (INITZERO) begin `RAM_INITIALIZATION
initial mem = '{default: 0};
end
always @(posedge clk) begin always @(posedge clk) begin
for (integer i = 0; i < BYTEENW; i++) begin for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i]) if (wren[i])
mem[waddr][i] <= din[i * 8 +: 8]; ram[waddr][i] <= wdata[i * 8 +: 8];
end end
dout_r <= mem[raddr]; if (rden)
rdata_r <= ram[raddr];
end end
end else begin end else begin
`USE_FAST_BRAM reg [DATAW-1:0] mem [SIZE-1:0]; `USE_FAST_BRAM reg [DATAW-1:0] ram [SIZE-1:0];
if (INITZERO) begin `RAM_INITIALIZATION
initial mem = '{default: 0};
end
always @(posedge clk) begin always @(posedge clk) begin
if (wren) if (wren)
mem[waddr] <= din; ram[waddr] <= wdata;
dout_r <= mem[raddr]; if (rden)
rdata_r <= ram[raddr];
end end
end end
assign dout = dout_r; assign rdata = rdata_r;
end else begin end else begin
`UNUSED_VAR (rden)
if (BYTEENW > 1) begin if (BYTEENW > 1) begin
`USE_FAST_BRAM reg [BYTEENW-1:0][7:0] mem [SIZE-1:0]; `USE_FAST_BRAM reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
if (INITZERO) begin `RAM_INITIALIZATION
initial mem = '{default: 0};
end
always @(posedge clk) begin always @(posedge clk) begin
for (integer i = 0; i < BYTEENW; i++) begin for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i]) if (wren[i])
mem[waddr][i] <= din[i * 8 +: 8]; ram[waddr][i] <= wdata[i * 8 +: 8];
end end
end end
assign dout = mem[raddr]; assign rdata = ram[raddr];
end else begin end else begin
`USE_FAST_BRAM reg [DATAW-1:0] mem [SIZE-1:0]; `USE_FAST_BRAM reg [DATAW-1:0] ram [SIZE-1:0];
if (INITZERO) begin `RAM_INITIALIZATION
initial mem = '{default: 0};
end
always @(posedge clk) begin always @(posedge clk) begin
if (wren) if (wren)
mem[waddr] <= din; ram[waddr] <= wdata;
end end
assign dout = mem[raddr]; assign rdata = ram[raddr];
end end
end end
end else begin end else begin
if (OUTPUT_REG) begin if (OUTPUT_REG) begin
reg [DATAW-1:0] dout_r; reg [RD_PORTS-1:0][DATAW-1:0] rdata_r;
if (BYTEENW > 1) begin if (BYTEENW > 1) begin
reg [BYTEENW-1:0][7:0] mem [SIZE-1:0]; reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
if (INITZERO) begin `RAM_INITIALIZATION
initial mem = '{default: 0};
end
always @(posedge clk) begin always @(posedge clk) begin
for (integer i = 0; i < BYTEENW; i++) begin for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i]) if (wren[i])
mem[waddr][i] <= din[i * 8 +: 8]; ram[waddr][i] <= wdata[i * 8 +: 8];
end
for (integer i = 0; i < RD_PORTS; ++i) begin
if (rden[i])
rdata_r[i] <= ram[raddr[i]];
end end
dout_r <= mem[raddr];
end end
end else begin end else begin
reg [DATAW-1:0] mem [SIZE-1:0]; reg [DATAW-1:0] ram [SIZE-1:0];
if (INITZERO) begin `RAM_INITIALIZATION
initial mem = '{default: 0};
end
always @(posedge clk) begin always @(posedge clk) begin
if (wren) if (wren)
mem[waddr] <= din; ram[waddr] <= wdata;
dout_r <= mem[raddr]; for (integer i = 0; i < RD_PORTS; ++i) begin
if (rden[i])
rdata_r[i] <= ram[raddr[i]];
end
end end
end end
assign dout = dout_r; assign rdata = rdata_r;
end else begin end else begin
if (RWCHECK) begin `UNUSED_VAR (rden)
if (NO_RWCHECK) begin
if (BYTEENW > 1) begin if (BYTEENW > 1) begin
reg [BYTEENW-1:0][7:0] mem [SIZE-1:0]; `NO_RW_RAM_CHECK reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
if (INITZERO) begin `RAM_INITIALIZATION
initial mem = '{default: 0};
end
always @(posedge clk) begin always @(posedge clk) begin
for (integer i = 0; i < BYTEENW; i++) begin for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i]) if (wren[i])
mem[waddr][i] <= din[i * 8 +: 8]; ram[waddr][i] <= wdata[i * 8 +: 8];
end end
end end
assign dout = mem[raddr]; for (genvar i = 0; i < RD_PORTS; ++i) begin
end else begin assign rdata[i] = ram[raddr[i]];
reg [DATAW-1:0] mem [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
end end
end else begin
`NO_RW_RAM_CHECK reg [DATAW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin always @(posedge clk) begin
if (wren) if (wren)
mem[waddr] <= din; ram[waddr] <= wdata;
end
for (genvar i = 0; i < RD_PORTS; ++i) begin
assign rdata[i] = ram[raddr[i]];
end end
assign dout = mem[raddr];
end end
end else begin end else begin
if (BYTEENW > 1) begin if (BYTEENW > 1) begin
`NO_RW_RAM_CHECK reg [BYTEENW-1:0][7:0] mem [SIZE-1:0]; reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
if (INITZERO) begin `RAM_INITIALIZATION
initial mem = '{default: 0};
end
always @(posedge clk) begin always @(posedge clk) begin
for (integer i = 0; i < BYTEENW; i++) begin for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i]) if (wren[i])
mem[waddr][i] <= din[i * 8 +: 8]; ram[waddr][i] <= wdata[i * 8 +: 8];
end end
end end
assign dout = mem[raddr]; for (genvar i = 0; i < RD_PORTS; ++i) begin
assign rdata[i] = ram[raddr[i]];
end
end else begin end else begin
`NO_RW_RAM_CHECK reg [DATAW-1:0] mem [SIZE-1:0]; reg [DATAW-1:0] ram [SIZE-1:0];
if (INITZERO) begin `RAM_INITIALIZATION
initial mem = '{default: 0};
end
always @(posedge clk) begin always @(posedge clk) begin
if (wren) if (wren)
mem[waddr] <= din; ram[waddr] <= wdata;
end
for (genvar i = 0; i < RD_PORTS; ++i) begin
assign rdata[i] = ram[raddr[i]];
end end
assign dout = mem[raddr];
end end
end end
end end
end end
`else
if (OUTPUT_REG) begin
reg [RD_PORTS-1:0][DATAW-1:0] rdata_r;
if (BYTEENW > 1) begin
reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i])
ram[waddr][i] <= wdata[i * 8 +: 8];
end
for (integer i = 0; i < RD_PORTS; ++i) begin
if (rden[i])
rdata_r[i] <= ram[raddr[i]];
end
end
end else begin
reg [DATAW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
ram[waddr] <= wdata;
for (integer i = 0; i < RD_PORTS; ++i) begin
if (rden[i])
rdata_r[i] <= ram[raddr[i]];
end
end
end
assign rdata = rdata_r;
end else begin
`UNUSED_VAR (rden)
if (BYTEENW > 1) begin
reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
reg [DATAW-1:0] prev_data;
reg [ADDRW-1:0] prev_waddr;
reg prev_write;
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i])
ram[waddr][i] <= wdata[i * 8 +: 8];
end
prev_write <= (| wren);
prev_data <= ram[waddr];
prev_waddr <= waddr;
end
if (LUTRAM || !NO_RWCHECK) begin
`UNUSED_VAR (prev_write)
`UNUSED_VAR (prev_data)
`UNUSED_VAR (prev_waddr)
for (genvar i = 0; i < RD_PORTS; ++i) begin
assign rdata[i] = ram[raddr[i]];
end
end else begin
for (genvar i = 0; i < RD_PORTS; ++i) begin
assign rdata[i] = (prev_write && (prev_waddr == raddr[i])) ? prev_data : ram[raddr[i]];
end
end
end else begin
reg [DATAW-1:0] ram [SIZE-1:0];
reg [DATAW-1:0] prev_data;
reg [ADDRW-1:0] prev_waddr;
reg prev_write;
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
ram[waddr] <= wdata;
prev_write <= wren;
prev_data <= ram[waddr];
prev_waddr <= waddr;
end
if (LUTRAM || !NO_RWCHECK) begin
`UNUSED_VAR (prev_write)
`UNUSED_VAR (prev_data)
`UNUSED_VAR (prev_waddr)
for (genvar i = 0; i < RD_PORTS; ++i) begin
assign rdata[i] = ram[raddr[i]];
end
end else begin
for (genvar i = 0; i < RD_PORTS; ++i) begin
assign rdata[i] = (prev_write && (prev_waddr == raddr[i])) ? prev_data : ram[raddr[i]];
end
end
end
end
`endif
endmodule endmodule
`TRACING_ON `TRACING_ON

4
hw/rtl/libs/VX_elastic_buffer.v
View File

@@ -5,7 +5,7 @@ module VX_elastic_buffer #(
parameter DATAW = 1, parameter DATAW = 1,
parameter SIZE = 2, parameter SIZE = 2,
parameter OUTPUT_REG = 0, parameter OUTPUT_REG = 0,
parameter FASTRAM = 0 parameter LUTRAM = 0
) ( ) (
input wire clk, input wire clk,
input wire reset, input wire reset,
@@ -56,7 +56,7 @@ module VX_elastic_buffer #(
.DATAW (DATAW), .DATAW (DATAW),
.SIZE (SIZE), .SIZE (SIZE),
.OUTPUT_REG (OUTPUT_REG), .OUTPUT_REG (OUTPUT_REG),
.FASTRAM (FASTRAM) .LUTRAM (LUTRAM)
) queue ( ) queue (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),

32
hw/rtl/libs/VX_fifo_queue.v
View File

@@ -9,7 +9,7 @@ module VX_fifo_queue #(
parameter ADDRW = $clog2(SIZE), parameter ADDRW = $clog2(SIZE),
parameter SIZEW = $clog2(SIZE+1), parameter SIZEW = $clog2(SIZE+1),
parameter OUTPUT_REG = 0, parameter OUTPUT_REG = 0,
parameter FASTRAM = 1 parameter LUTRAM = 1
) ( ) (
input wire clk, input wire clk,
input wire reset, input wire reset,
@@ -157,15 +157,15 @@ module VX_fifo_queue #(
.DATAW (DATAW), .DATAW (DATAW),
.SIZE (SIZE), .SIZE (SIZE),
.OUTPUT_REG (0), .OUTPUT_REG (0),
.RWCHECK (1), .LUTRAM (LUTRAM)
.FASTRAM (FASTRAM)
) dp_ram ( ) dp_ram (
.clk(clk), .clk(clk),
.waddr(wr_ptr_r), .wren (push),
.raddr(rd_ptr_r), .waddr (wr_ptr_r),
.wren(push), .wdata (data_in),
.din(data_in), .rden (1'b1),
.dout(data_out) .raddr (rd_ptr_r),
.rdata (data_out)
); );
end else begin end else begin
@@ -200,15 +200,15 @@ module VX_fifo_queue #(
.DATAW (DATAW), .DATAW (DATAW),
.SIZE (SIZE), .SIZE (SIZE),
.OUTPUT_REG (0), .OUTPUT_REG (0),
.RWCHECK (1), .LUTRAM (LUTRAM)
.FASTRAM (FASTRAM)
) dp_ram ( ) dp_ram (
.clk(clk), .clk (clk),
.waddr(wr_ptr_r), .wren (push),
.raddr(rd_ptr_n_r), .waddr (wr_ptr_r),
.wren(push), .wdata (data_in),
.din(data_in), .rden (1'b1),
.dout(dout) .raddr (rd_ptr_n_r),
.rdata (dout)
); );
always @(posedge clk) begin always @(posedge clk) begin

28
hw/rtl/libs/VX_index_buffer.v
View File

@@ -2,10 +2,10 @@
`TRACING_OFF `TRACING_OFF
module VX_index_buffer #( module VX_index_buffer #(
parameter DATAW = 1, parameter DATAW = 1,
parameter SIZE = 1, parameter SIZE = 1,
parameter FASTRAM = 1, parameter LUTRAM = 1,
parameter ADDRW = `LOG2UP(SIZE) parameter ADDRW = `LOG2UP(SIZE)
) ( ) (
input wire clk, input wire clk,
input wire reset, input wire reset,
@@ -68,17 +68,17 @@ module VX_index_buffer #(
end end
VX_dp_ram #( VX_dp_ram #(
.DATAW(DATAW), .DATAW (DATAW),
.SIZE(SIZE), .SIZE (SIZE),
.RWCHECK(1), .LUTRAM (LUTRAM)
.FASTRAM(FASTRAM)
) data_table ( ) data_table (
.clk(clk), .clk (clk),
.waddr(write_addr), .wren (acquire_slot),
.raddr(read_addr), .waddr (write_addr),
.wren(acquire_slot), .wdata (write_data),
.din(write_data), .rden (1'b1),
.dout(read_data) .raddr (read_addr),
.rdata (read_data)
); );
assign write_addr = write_addr_r; assign write_addr = write_addr_r;

242
hw/rtl/libs/VX_sp_ram.v
View File

@@ -2,177 +2,259 @@
`TRACING_OFF `TRACING_OFF
module VX_sp_ram #( module VX_sp_ram #(
parameter DATAW = 1, parameter DATAW = 1,
parameter SIZE = 1, parameter SIZE = 1,
parameter BYTEENW = 1, parameter BYTEENW = 1,
parameter OUTPUT_REG = 0, parameter OUTPUT_REG = 0,
parameter RWCHECK = 1, parameter NO_RWCHECK = 0,
parameter ADDRW = $clog2(SIZE), parameter ADDRW = $clog2(SIZE),
parameter FASTRAM = 0, parameter LUTRAM = 0,
parameter INITZERO = 0 parameter INIT_ENABLE = 0,
) ( parameter INIT_FILE = "",
input wire clk, parameter [DATAW-1:0] INIT_VALUE = 0
input wire [ADDRW-1:0] addr, ) (
input wire clk,
input wire [ADDRW-1:0] addr,
input wire [BYTEENW-1:0] wren, input wire [BYTEENW-1:0] wren,
input wire [DATAW-1:0] din, input wire [DATAW-1:0] wdata,
output wire [DATAW-1:0] dout input wire rden,
output wire [DATAW-1:0] rdata
); );
`STATIC_ASSERT((1 == BYTEENW) || ((BYTEENW > 1) && 0 == (BYTEENW % 4)), ("invalid parameter")) `STATIC_ASSERT((1 == BYTEENW) || ((BYTEENW > 1) && 0 == (BYTEENW % 4)), ("invalid parameter"))
if (FASTRAM) begin `define RAM_INITIALIZATION \
if (INIT_ENABLE) begin \
if (INIT_FILE != "") begin \
initial $readmemh(INIT_FILE, ram); \
end else begin \
initial ram = '{default: INIT_VALUE}; \
end \
end
`ifdef SYNTHESIS
if (LUTRAM) begin
if (OUTPUT_REG) begin if (OUTPUT_REG) begin
reg [DATAW-1:0] dout_r; reg [DATAW-1:0] rdata_r;
if (BYTEENW > 1) begin if (BYTEENW > 1) begin
`USE_FAST_BRAM reg [BYTEENW-1:0][7:0] mem [SIZE-1:0]; `USE_FAST_BRAM reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
if (INITZERO) begin `RAM_INITIALIZATION
initial mem = '{default: 0};
end
always @(posedge clk) begin always @(posedge clk) begin
for (integer i = 0; i < BYTEENW; i++) begin for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i]) if (wren[i])
mem[addr][i] <= din[i * 8 +: 8]; ram[addr][i] <= wdata[i * 8 +: 8];
end end
dout_r <= mem[addr]; if (rden)
rdata_r <= ram[addr];
end end
end else begin end else begin
`USE_FAST_BRAM reg [DATAW-1:0] mem [SIZE-1:0]; `USE_FAST_BRAM reg [DATAW-1:0] ram [SIZE-1:0];
if (INITZERO) begin `RAM_INITIALIZATION
initial mem = '{default: 0};
end
always @(posedge clk) begin always @(posedge clk) begin
if (wren) if (wren)
mem[addr] <= din; ram[addr] <= wdata;
dout_r <= mem[addr]; if (rden)
rdata_r <= ram[addr];
end end
end end
assign dout = dout_r; assign rdata = rdata_r;
end else begin end else begin
`UNUSED_VAR (rden)
if (BYTEENW > 1) begin if (BYTEENW > 1) begin
`USE_FAST_BRAM reg [BYTEENW-1:0][7:0] mem [SIZE-1:0]; `USE_FAST_BRAM reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
if (INITZERO) begin `RAM_INITIALIZATION
initial mem = '{default: 0};
end
always @(posedge clk) begin always @(posedge clk) begin
for (integer i = 0; i < BYTEENW; i++) begin for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i]) if (wren[i])
mem[addr][i] <= din[i * 8 +: 8]; ram[addr][i] <= wdata[i * 8 +: 8];
end end
end end
assign dout = mem[addr]; assign rdata = ram[addr];
end else begin end else begin
`USE_FAST_BRAM reg [DATAW-1:0] mem [SIZE-1:0]; `USE_FAST_BRAM reg [DATAW-1:0] ram [SIZE-1:0];
if (INITZERO) begin `RAM_INITIALIZATION
initial mem = '{default: 0};
end
always @(posedge clk) begin always @(posedge clk) begin
if (wren) if (wren)
mem[addr] <= din; ram[addr] <= wdata;
end end
assign dout = mem[addr]; assign rdata = ram[addr];
end end
end end
end else begin end else begin
if (OUTPUT_REG) begin if (OUTPUT_REG) begin
reg [DATAW-1:0] dout_r; reg [DATAW-1:0] rdata_r;
if (BYTEENW > 1) begin if (BYTEENW > 1) begin
reg [BYTEENW-1:0][7:0] mem [SIZE-1:0]; reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
if (INITZERO) begin `RAM_INITIALIZATION
initial mem = '{default: 0};
end
always @(posedge clk) begin always @(posedge clk) begin
for (integer i = 0; i < BYTEENW; i++) begin for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i]) if (wren[i])
mem[addr][i] <= din[i * 8 +: 8]; ram[addr][i] <= wdata[i * 8 +: 8];
end end
dout_r <= mem[addr]; if (rden)
rdata_r <= ram[addr];
end end
end else begin end else begin
reg [DATAW-1:0] mem [SIZE-1:0]; reg [DATAW-1:0] ram [SIZE-1:0];
if (INITZERO) begin `RAM_INITIALIZATION
initial mem = '{default: 0};
end
always @(posedge clk) begin always @(posedge clk) begin
if (wren) if (wren)
mem[addr] <= din; ram[addr] <= wdata;
dout_r <= mem[addr]; if (rden)
rdata_r <= ram[addr];
end end
end end
assign dout = dout_r; assign rdata = rdata_r;
end else begin end else begin
if (RWCHECK) begin `UNUSED_VAR (rden)
if (NO_RWCHECK) begin
if (BYTEENW > 1) begin if (BYTEENW > 1) begin
reg [BYTEENW-1:0][7:0] mem [SIZE-1:0]; `NO_RW_RAM_CHECK reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
if (INITZERO) begin `RAM_INITIALIZATION
initial mem = '{default: 0};
end
always @(posedge clk) begin always @(posedge clk) begin
for (integer i = 0; i < BYTEENW; i++) begin for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i]) if (wren[i])
mem[addr][i] <= din[i * 8 +: 8]; ram[addr][i] <= wdata[i * 8 +: 8];
end end
end end
assign dout = mem[addr]; assign rdata = ram[addr];
end else begin end else begin
reg [DATAW-1:0] mem [SIZE-1:0]; `NO_RW_RAM_CHECK reg [DATAW-1:0] ram [SIZE-1:0];
if (INITZERO) begin `RAM_INITIALIZATION
initial mem = '{default: 0};
end
always @(posedge clk) begin always @(posedge clk) begin
if (wren) if (wren)
mem[addr] <= din; ram[addr] <= wdata;
end end
assign dout = mem[addr]; assign rdata = ram[addr];
end end
end else begin end else begin
if (BYTEENW > 1) begin if (BYTEENW > 1) begin
`NO_RW_RAM_CHECK reg [BYTEENW-1:0][7:0] mem [SIZE-1:0]; reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
if (INITZERO) begin `RAM_INITIALIZATION
initial mem = '{default: 0};
end
always @(posedge clk) begin always @(posedge clk) begin
for (integer i = 0; i < BYTEENW; i++) begin for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i]) if (wren[i])
mem[addr][i] <= din[i * 8 +: 8]; ram[addr][i] <= wdata[i * 8 +: 8];
end end
end end
assign dout = mem[addr]; assign rdata = ram[addr];
end else begin end else begin
`NO_RW_RAM_CHECK reg [DATAW-1:0] mem [SIZE-1:0]; reg [DATAW-1:0] ram [SIZE-1:0];
if (INITZERO) begin `RAM_INITIALIZATION
initial mem = '{default: 0};
end
always @(posedge clk) begin always @(posedge clk) begin
if (wren) if (wren)
mem[addr] <= din; ram[addr] <= wdata;
end end
assign dout = mem[addr]; assign rdata = ram[addr];
end end
end end
end end
end end
`else
if (OUTPUT_REG) begin
reg [DATAW-1:0] rdata_r;
if (BYTEENW > 1) begin
reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i])
ram[addr][i] <= wdata[i * 8 +: 8];
end
if (rden)
rdata_r <= ram[addr];
end
end else begin
reg [DATAW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
ram[addr] <= wdata;
if (rden)
rdata_r <= ram[addr];
end
end
assign rdata = rdata_r;
end else begin
`UNUSED_VAR (rden)
if (BYTEENW > 1) begin
reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
reg [DATAW-1:0] prev_data;
reg [ADDRW-1:0] prev_addr;
reg prev_write;
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i])
ram[addr][i] <= wdata[i * 8 +: 8];
end
prev_write <= (| wren);
prev_data <= ram[addr];
prev_addr <= addr;
end
if (LUTRAM || !NO_RWCHECK) begin
`UNUSED_VAR (prev_write)
`UNUSED_VAR (prev_data)
`UNUSED_VAR (prev_addr)
assign rdata = ram[addr];
end else begin
assign rdata = (prev_write && (prev_addr == addr)) ? prev_data : ram[addr];
end
end else begin
reg [DATAW-1:0] ram [SIZE-1:0];
reg [DATAW-1:0] prev_data;
reg [ADDRW-1:0] prev_addr;
reg prev_write;
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
ram[addr] <= wdata;
prev_write <= wren;
prev_data <= ram[addr];
prev_addr <= addr;
end
if (LUTRAM || !NO_RWCHECK) begin
`UNUSED_VAR (prev_write)
`UNUSED_VAR (prev_data)
`UNUSED_VAR (prev_addr)
assign rdata = ram[addr];
end else begin
assign rdata = (prev_write && (prev_addr == addr)) ? prev_data : ram[addr];
end
end
end
`endif
endmodule endmodule
`TRACING_ON `TRACING_ON