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block ram refactoring (multi-porting supporting and simulation support)

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This commit is contained in:
Blaise Tine
2021-08-26 08:19:44 -07:00
parent 06a6857508
commit d91d56d126
14 changed files with 480 additions and 353 deletions
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28
hw/rtl/libs/VX_index_buffer.v
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@@ -2,10 +2,10 @@
`TRACING_OFF
module VX_index_buffer #(
parameter DATAW = 1,
parameter SIZE = 1,
parameter FASTRAM = 1,
parameter ADDRW = `LOG2UP(SIZE)
parameter DATAW = 1,
parameter SIZE = 1,
parameter LUTRAM = 1,
parameter ADDRW = `LOG2UP(SIZE)
) (
input wire clk,
input wire reset,
@@ -68,17 +68,17 @@ module VX_index_buffer #(
end
VX_dp_ram #(
.DATAW(DATAW),
.SIZE(SIZE),
.RWCHECK(1),
.FASTRAM(FASTRAM)
.DATAW (DATAW),
.SIZE (SIZE),
.LUTRAM (LUTRAM)
) data_table (
.clk(clk),
.waddr(write_addr),
.raddr(read_addr),
.wren(acquire_slot),
.din(write_data),
.dout(read_data)
.clk (clk),
.wren (acquire_slot),
.waddr (write_addr),
.wdata (write_data),
.rden (1'b1),
.raddr (read_addr),
.rdata (read_data)
);
assign write_addr = write_addr_r;