block ram refactoring (multi-porting supporting and simulation support)

2021-08-26 08:19:44 -07:00
parent 06a6857508
commit d91d56d126
14 changed files with 480 additions and 353 deletions
--- a/hw/rtl/libs/VX_elastic_buffer.v
+++ b/hw/rtl/libs/VX_elastic_buffer.v
@@ -5,7 +5,7 @@ module VX_elastic_buffer #(
    parameter DATAW      = 1,
    parameter SIZE       = 2,
    parameter OUTPUT_REG = 0,
-    parameter FASTRAM    = 0
+    parameter LUTRAM     = 0
 ) ( 
    input  wire             clk,
    input  wire             reset,
@@ -56,7 +56,7 @@ module VX_elastic_buffer #(
            .DATAW      (DATAW),
            .SIZE       (SIZE),
            .OUTPUT_REG (OUTPUT_REG),
-            .FASTRAM    (FASTRAM)
+            .LUTRAM     (LUTRAM)
        ) queue (
            .clk    (clk),
            .reset  (reset),