block ram refactoring (multi-porting supporting and simulation support)

2021-08-26 08:19:44 -07:00
parent 06a6857508
commit d91d56d126
14 changed files with 480 additions and 353 deletions
--- a/hw/rtl/cache/VX_data_access.v
+++ b/hw/rtl/cache/VX_data_access.v
@@ -65,14 +65,14 @@ module VX_data_access #(
    VX_sp_ram #(
        .DATAW   (CACHE_LINE_SIZE * 8),
        .SIZE    (`LINES_PER_BANK),
-        .BYTEENW (BYTEENW),
-        .RWCHECK (1)
+        .BYTEENW (BYTEENW)
    ) data_store (
-        .clk(clk),        
-        .addr(line_addr),
-        .wren({BYTEENW{writeen}} & byte_enable),
-        .din(wdata),
-        .dout(rdata)
+        .clk   (clk),        
+        .addr  (line_addr),
+        .wren  ({BYTEENW{writeen}} & byte_enable),
+        .wdata (wdata),
+        .rden  (1'b1),
+        .rdata (rdata)
    );

    `UNUSED_VAR (stall)