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This commit is contained in:
Blaise Tine
2020-04-21 03:19:47 -04:00
parent 43a8bf4326
commit d85c0af5d6
75 changed files with 4388 additions and 4382 deletions
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8
hw/rtl/interfaces/VX_branch_rsp_if.v
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@@ -5,10 +5,10 @@
interface VX_branch_rsp_if ();
wire valid_branch;
wire branch_dir;
wire [31:0] branch_dest;
wire [`NW_BITS-1:0] branch_warp_num;
wire valid_branch;
wire branch_dir;
wire [31:0] branch_dest;
wire [`NW_BITS-1:0] branch_warp_num;
endinterface

18
hw/rtl/interfaces/VX_csr_req_if.v
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@@ -5,15 +5,15 @@
interface VX_csr_req_if ();
wire [`NUM_THREADS-1:0] valid;
wire [`NW_BITS-1:0] warp_num;
wire [4:0] rd;
wire [1:0] wb;
wire [4:0] alu_op;
wire is_csr;
wire [11:0] csr_address;
wire csr_immed;
wire [31:0] csr_mask;
wire [`NUM_THREADS-1:0] valid;
wire [`NW_BITS-1:0] warp_num;
wire [4:0] rd;
wire [1:0] wb;
wire [4:0] alu_op;
wire is_csr;
wire [11:0] csr_address;
wire csr_immed;
wire [31:0] csr_mask;
endinterface

12
hw/rtl/interfaces/VX_csr_wb_if.v
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@@ -5,12 +5,12 @@
interface VX_csr_wb_if ();
wire [`NUM_THREADS-1:0] valid;
wire [`NW_BITS-1:0] warp_num;
wire [4:0] rd;
wire [1:0] wb;
wire [`NUM_THREADS-1:0][31:0] csr_result;
wire [`NUM_THREADS-1:0] valid;
wire [`NW_BITS-1:0] warp_num;
wire [4:0] rd;
wire [1:0] wb;
wire [`NUM_THREADS-1:0][31:0] csr_result;
endinterface

60
hw/rtl/interfaces/VX_exec_unit_req_if.v
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@@ -5,44 +5,44 @@
interface VX_exec_unit_req_if ();
// Meta
wire [`NUM_THREADS-1:0] valid;
wire [`NW_BITS-1:0] warp_num;
wire [31:0] curr_PC;
wire [31:0] PC_next;
// Meta
wire [`NUM_THREADS-1:0] valid;
wire [`NW_BITS-1:0] warp_num;
wire [31:0] curr_PC;
wire [31:0] PC_next;
// Write Back Info
wire [4:0] rd;
wire [1:0] wb;
// Write Back Info
wire [4:0] rd;
wire [1:0] wb;
// Data and alu op
wire [`NUM_THREADS-1:0][31:0] a_reg_data;
wire [`NUM_THREADS-1:0][31:0] b_reg_data;
wire [4:0] alu_op;
wire [4:0] rs1;
wire [4:0] rs2;
wire rs2_src;
wire [31:0] itype_immed;
wire [19:0] upper_immed;
// Data and alu op
wire [`NUM_THREADS-1:0][31:0] a_reg_data;
wire [`NUM_THREADS-1:0][31:0] b_reg_data;
wire [4:0] alu_op;
wire [4:0] rs1;
wire [4:0] rs2;
wire rs2_src;
wire [31:0] itype_immed;
wire [19:0] upper_immed;
// Branch type
wire [2:0] branch_type;
// Branch type
wire [2:0] branch_type;
// Jal info
wire jalQual;
wire jal;
wire [31:0] jal_offset;
// Jal info
wire jalQual;
wire jal;
wire [31:0] jal_offset;
`IGNORE_WARNINGS_BEGIN
wire ebreak;
wire wspawn;
wire ebreak;
wire wspawn;
`IGNORE_WARNINGS_END
// CSR info
wire is_csr;
wire [11:0] csr_address;
wire csr_immed;
wire [31:0] csr_mask;
// CSR info
wire is_csr;
wire [11:0] csr_address;
wire csr_immed;
wire [31:0] csr_mask;
endinterface

56
hw/rtl/interfaces/VX_frE_to_bckE_req_if.v
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@@ -5,37 +5,37 @@
interface VX_frE_to_bckE_req_if ();
wire [11:0] csr_address;
wire is_csr;
wire csr_immed;
wire [31:0] csr_mask;
wire [4:0] rd;
wire [4:0] rs1;
wire [4:0] rs2;
wire [4:0] alu_op;
wire [1:0] wb;
wire rs2_src;
wire [31:0] itype_immed;
wire [2:0] mem_read;
wire [2:0] mem_write;
wire [2:0] branch_type;
wire [19:0] upper_immed;
wire [31:0] curr_PC;
wire [11:0] csr_address;
wire is_csr;
wire csr_immed;
wire [31:0] csr_mask;
wire [4:0] rd;
wire [4:0] rs1;
wire [4:0] rs2;
wire [4:0] alu_op;
wire [1:0] wb;
wire rs2_src;
wire [31:0] itype_immed;
wire [2:0] mem_read;
wire [2:0] mem_write;
wire [2:0] branch_type;
wire [19:0] upper_immed;
wire [31:0] curr_PC;
`IGNORE_WARNINGS_BEGIN
wire ebreak;
wire ebreak;
`IGNORE_WARNINGS_END
wire jalQual;
wire jal;
wire [31:0] jal_offset;
wire [31:0] PC_next;
wire [`NUM_THREADS-1:0] valid;
wire [`NW_BITS-1:0] warp_num;
wire jalQual;
wire jal;
wire [31:0] jal_offset;
wire [31:0] PC_next;
wire [`NUM_THREADS-1:0] valid;
wire [`NW_BITS-1:0] warp_num;
// GPGPU stuff
wire is_wspawn;
wire is_tmc;
wire is_split;
wire is_barrier;
// GPGPU stuff
wire is_wspawn;
wire is_tmc;
wire is_split;
wire is_barrier;
endinterface

4
hw/rtl/interfaces/VX_gpr_data_if.v
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@@ -6,8 +6,8 @@
interface VX_gpr_data_if ();
wire [`NUM_THREADS-1:0][31:0] a_reg_data;
wire [`NUM_THREADS-1:0][31:0] b_reg_data;
wire [`NUM_THREADS-1:0][31:0] a_reg_data;
wire [`NUM_THREADS-1:0][31:0] b_reg_data;
endinterface

6
hw/rtl/interfaces/VX_gpr_jal_if.v
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@@ -5,9 +5,9 @@
interface VX_gpr_jal_if ();
wire is_jal;
wire[31:0] curr_PC;
wire is_jal;
wire[31:0] curr_PC;
endinterface
`endif

6
hw/rtl/interfaces/VX_gpr_read_if.v
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@@ -5,9 +5,9 @@
interface VX_gpr_read_if ();
wire [4:0] rs1;
wire [4:0] rs2;
wire [`NW_BITS-1:0] warp_num;
wire [4:0] rs1;
wire [4:0] rs2;
wire [`NW_BITS-1:0] warp_num;
endinterface

2
hw/rtl/interfaces/VX_gpu_dcache_dram_req_if.v
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@@ -7,7 +7,7 @@ interface VX_gpu_dcache_dram_req_if #(
parameter BANK_LINE_WORDS = 2
) ();
// DRAM Request
// DRAM Request
wire dram_req_write;
wire dram_req_read;
wire [31:0] dram_req_addr;

4
hw/rtl/interfaces/VX_gpu_dcache_dram_rsp_if.v
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@@ -4,9 +4,9 @@
`include "../cache/VX_cache_config.vh"
interface VX_gpu_dcache_dram_rsp_if #(
parameter BANK_LINE_WORDS = 2
parameter BANK_LINE_WORDS = 2
) ();
// DRAM Response
// DRAM Response
wire dram_rsp_valid;
wire [31:0] dram_rsp_addr;
wire [BANK_LINE_WORDS-1:0][31:0] dram_rsp_data;

20
hw/rtl/interfaces/VX_gpu_dcache_req_if.v
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@@ -4,22 +4,22 @@
`include "../cache/VX_cache_config.vh"
interface VX_gpu_dcache_req_if #(
parameter NUM_REQUESTS = 32
parameter NUM_REQUESTS = 32
) ();
// Core request
wire [NUM_REQUESTS-1:0] core_req_valid;
wire [NUM_REQUESTS-1:0][2:0] core_req_read;
wire [NUM_REQUESTS-1:0][2:0] core_req_write;
wire [NUM_REQUESTS-1:0][31:0] core_req_addr;
wire [NUM_REQUESTS-1:0][31:0] core_req_data;
wire core_req_ready;
// Core request
wire [NUM_REQUESTS-1:0] core_req_valid;
wire [NUM_REQUESTS-1:0][2:0] core_req_read;
wire [NUM_REQUESTS-1:0][2:0] core_req_write;
wire [NUM_REQUESTS-1:0][31:0] core_req_addr;
wire [NUM_REQUESTS-1:0][31:0] core_req_data;
wire core_req_ready;
// Core request Meta data
// Core request Meta data
wire [4:0] core_req_rd;
wire [NUM_REQUESTS-1:0][1:0] core_req_wb;
wire [`NW_BITS-1:0] core_req_warp_num;
wire [31:0] core_req_pc;
wire [31:0] core_req_pc;
endinterface

2
hw/rtl/interfaces/VX_gpu_dcache_rsp_if.v
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@@ -7,7 +7,7 @@ interface VX_gpu_dcache_rsp_if #(
parameter NUM_REQUESTS = 32
) ();
// Core response
// Core response
wire [NUM_REQUESTS-1:0] core_rsp_valid;
`IGNORE_WARNINGS_BEGIN
wire [4:0] core_rsp_read;

2
hw/rtl/interfaces/VX_gpu_dcache_snp_req_if.v
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@@ -4,7 +4,7 @@
`include "../cache/VX_cache_config.vh"
interface VX_gpu_dcache_snp_req_if ();
// Snoop Req
// Snoop Req
wire snp_req_valid;
wire [31:0] snp_req_addr;

18
hw/rtl/interfaces/VX_gpu_inst_req_if.v
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@@ -5,18 +5,18 @@
interface VX_gpu_inst_req_if();
wire [`NUM_THREADS-1:0] valid;
wire [`NW_BITS-1:0] warp_num;
wire is_wspawn;
wire is_tmc;
wire is_split;
wire [`NUM_THREADS-1:0] valid;
wire [`NW_BITS-1:0] warp_num;
wire is_wspawn;
wire is_tmc;
wire is_split;
wire is_barrier;
wire is_barrier;
wire[31:0] pc_next;
wire[31:0] pc_next;
wire [`NUM_THREADS-1:0][31:0] a_reg_data;
wire [31:0] rd2;
wire [`NUM_THREADS-1:0][31:0] a_reg_data;
wire [31:0] rd2;
endinterface

12
hw/rtl/interfaces/VX_gpu_snp_req_rsp_if.v
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@@ -5,13 +5,13 @@
interface VX_gpu_snp_req_rsp_if ();
// Snoop request
wire snp_req_valid;
wire [31:0] snp_req_addr;
wire snp_req_ready;
// Snoop request
wire snp_req_valid;
wire [31:0] snp_req_addr;
wire snp_req_ready;
// Snoop Response
// TODO:
// Snoop Response
// TODO:
endinterface

8
hw/rtl/interfaces/VX_icache_rsp_if.v
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@@ -5,10 +5,10 @@
interface VX_icache_rsp_if ();
// wire ready;
// wire stall;
wire [31:0] instruction;
wire delay;
// wire ready;
// wire stall;
wire [31:0] instruction;
wire delay;
endinterface

12
hw/rtl/interfaces/VX_inst_exec_wb_if.v
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@@ -6,12 +6,12 @@
interface VX_inst_exec_wb_if ();
wire [`NUM_THREADS-1:0][31:0] alu_result;
wire [31:0] exec_wb_pc;
wire [4:0] rd;
wire [1:0] wb;
wire [`NUM_THREADS-1:0] wb_valid;
wire [`NW_BITS-1:0] wb_warp_num;
wire [`NUM_THREADS-1:0][31:0] alu_result;
wire [31:0] exec_wb_pc;
wire [4:0] rd;
wire [1:0] wb;
wire [`NUM_THREADS-1:0] wb_valid;
wire [`NW_BITS-1:0] wb_warp_num;
endinterface

12
hw/rtl/interfaces/VX_inst_mem_wb_if.v
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@@ -6,12 +6,12 @@
interface VX_inst_mem_wb_if ();
wire [`NUM_THREADS-1:0][31:0] loaded_data;
wire [31:0] mem_wb_pc;
wire [4:0] rd;
wire [1:0] wb;
wire [`NUM_THREADS-1:0] wb_valid;
wire [`NW_BITS-1:0] wb_warp_num;
wire [`NUM_THREADS-1:0][31:0] loaded_data;
wire [31:0] mem_wb_pc;
wire [4:0] rd;
wire [1:0] wb;
wire [`NUM_THREADS-1:0] wb_valid;
wire [`NW_BITS-1:0] wb_warp_num;
endinterface

8
hw/rtl/interfaces/VX_inst_meta_if.v
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@@ -5,10 +5,10 @@
interface VX_inst_meta_if ();
wire [31:0] instruction;
wire [31:0] inst_pc;
wire [`NW_BITS-1:0] warp_num;
wire [`NUM_THREADS-1:0] valid;
wire [31:0] instruction;
wire [31:0] inst_pc;
wire [`NW_BITS-1:0] warp_num;
wire [`NUM_THREADS-1:0] valid;
endinterface

8
hw/rtl/interfaces/VX_jal_rsp_if.v
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@@ -6,10 +6,10 @@
interface VX_jal_rsp_if ();
wire jal;
wire [31:0] jal_dest;
wire [`NW_BITS-1:0] jal_warp_num;
wire jal;
wire [31:0] jal_dest;
wire [`NW_BITS-1:0] jal_warp_num;
endinterface
`endif

4
hw/rtl/interfaces/VX_join_if.v
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@@ -6,8 +6,8 @@
interface VX_join_if ();
wire is_join;
wire [`NW_BITS-1:0] join_warp_num;
wire is_join;
wire [`NW_BITS-1:0] join_warp_num;
endinterface

20
hw/rtl/interfaces/VX_lsu_req_if.v
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@@ -6,16 +6,16 @@
interface VX_lsu_req_if ();
wire [`NUM_THREADS-1:0] valid;
wire [31:0] lsu_pc;
wire [`NW_BITS-1:0] warp_num;
wire [`NUM_THREADS-1:0][31:0] store_data;
wire [`NUM_THREADS-1:0][31:0] base_address; // A reg data
wire [31:0] offset; // itype_immed
wire [2:0] mem_read;
wire [2:0] mem_write;
wire [4:0] rd;
wire [1:0] wb;
wire [`NUM_THREADS-1:0] valid;
wire [31:0] lsu_pc;
wire [`NW_BITS-1:0] warp_num;
wire [`NUM_THREADS-1:0][31:0] store_data;
wire [`NUM_THREADS-1:0][31:0] base_address; // A reg data
wire [31:0] offset; // itype_immed
wire [2:0] mem_read;
wire [2:0] mem_write;
wire [4:0] rd;
wire [1:0] wb;
endinterface

14
hw/rtl/interfaces/VX_mw_wb_if.v
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@@ -6,13 +6,13 @@
interface VX_mw_wb_if ();
wire [`NUM_THREADS-1:0][31:0] alu_result;
wire [`NUM_THREADS-1:0][31:0] mem_result;
wire [4:0] rd;
wire [1:0] wb;
wire [31:0] PC_next;
wire [`NUM_THREADS-1:0] valid;
wire [`NW_BITS-1:0] warp_num;
wire [`NUM_THREADS-1:0][31:0] alu_result;
wire [`NUM_THREADS-1:0][31:0] mem_result;
wire [4:0] rd;
wire [1:0] wb;
wire [31:0] PC_next;
wire [`NUM_THREADS-1:0] valid;
wire [`NW_BITS-1:0] warp_num;
endinterface

34
hw/rtl/interfaces/VX_warp_ctl_if.v
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@@ -6,29 +6,29 @@
interface VX_warp_ctl_if ();
wire [`NW_BITS-1:0] warp_num;
wire change_mask;
wire [`NUM_THREADS-1:0] thread_mask;
wire [`NW_BITS-1:0] warp_num;
wire change_mask;
wire [`NUM_THREADS-1:0] thread_mask;
wire wspawn;
wire [31:0] wspawn_pc;
wire [`NUM_WARPS-1:0] wspawn_new_active;
wire wspawn;
wire [31:0] wspawn_pc;
wire [`NUM_WARPS-1:0] wspawn_new_active;
wire ebreak;
wire ebreak;
// barrier
wire is_barrier;
wire [31:0] barrier_id;
wire [$clog2(`NUM_WARPS):0] num_warps;
// barrier
wire is_barrier;
wire [31:0] barrier_id;
wire [$clog2(`NUM_WARPS):0] num_warps;
wire is_split;
wire dont_split;
wire is_split;
wire dont_split;
`IGNORE_WARNINGS_BEGIN
wire [`NW_BITS-1:0] split_warp_num;
wire [`NW_BITS-1:0] split_warp_num;
`IGNORE_WARNINGS_END
wire [`NUM_THREADS-1:0] split_new_mask;
wire [`NUM_THREADS-1:0] split_later_mask;
wire [31:0] split_save_pc;
wire [`NUM_THREADS-1:0] split_new_mask;
wire [`NUM_THREADS-1:0] split_later_mask;
wire [31:0] split_save_pc;
endinterface

12
hw/rtl/interfaces/VX_wb_if.v
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@@ -5,12 +5,12 @@
interface VX_wb_if ();
wire [`NUM_THREADS-1:0][31:0] write_data;
wire [31:0] wb_pc;
wire [4:0] rd;
wire [1:0] wb;
wire [`NUM_THREADS-1:0] wb_valid;
wire [`NW_BITS-1:0] wb_warp_num;
wire [`NUM_THREADS-1:0][31:0] write_data;
wire [31:0] wb_pc;
wire [4:0] rd;
wire [1:0] wb;
wire [`NUM_THREADS-1:0] wb_valid;
wire [`NW_BITS-1:0] wb_warp_num;
endinterface

4
hw/rtl/interfaces/VX_wstall_if.v
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@@ -5,8 +5,8 @@
interface VX_wstall_if();
wire wstall;
wire [`NW_BITS-1:0] warp_num;
wire wstall;
wire [`NW_BITS-1:0] warp_num;
endinterface