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Merge branch 'master' of https://github.gatech.edu/casl/Vortex

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This commit is contained in:
felsabbagh3
2020-06-29 23:00:53 -07:00
parent b8e8cab1ee f66c251309
commit d7ef5f0bd7
18 changed files with 160 additions and 47 deletions
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13
hw/rtl/VX_alu_unit.v
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@@ -13,9 +13,6 @@ module VX_alu_unit (
output reg [31:0] alu_result,
output reg alu_stall
);
localparam DIV_PIPELINE_LEN = 20;
localparam MUL_PIPELINE_LEN = 8;
wire[31:0] div_result_unsigned;
wire[31:0] div_result_signed;
@@ -37,11 +34,11 @@ module VX_alu_unit (
`ALU_DIV,
`ALU_DIVU,
`ALU_REM,
`ALU_REMU: inst_delay = DIV_PIPELINE_LEN;
`ALU_REMU: inst_delay = `DIV_LATENCY;
`ALU_MUL,
`ALU_MULH,
`ALU_MULHSU,
`ALU_MULHU: inst_delay = MUL_PIPELINE_LEN;
`ALU_MULHU: inst_delay = `MUL_LATENCY;
default: inst_delay = 0;
endcase
end
@@ -91,7 +88,7 @@ module VX_alu_unit (
.WIDTHD(32),
.NSIGNED(0),
.DSIGNED(0),
.PIPELINE(DIV_PIPELINE_LEN)
.PIPELINE(`DIV_LATENCY)
) udiv (
.clk(clk),
.reset(reset),
@@ -106,7 +103,7 @@ module VX_alu_unit (
.WIDTHD(32),
.NSIGNED(1),
.DSIGNED(1),
.PIPELINE(DIV_PIPELINE_LEN)
.PIPELINE(`DIV_LATENCY)
) sdiv (
.clk(clk),
.reset(reset),
@@ -124,7 +121,7 @@ module VX_alu_unit (
.WIDTHB(33),
.WIDTHP(64),
.SIGNED(1),
.PIPELINE(MUL_PIPELINE_LEN)
.PIPELINE(`MUL_LATENCY)
) multiplier (
.clk(clk),
.reset(reset),

4
hw/rtl/VX_config.vh
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@@ -8,7 +8,7 @@
`endif
`ifndef NUM_CORES
`define NUM_CORES 1
`define NUM_CORES 4
`endif
`ifndef NUM_WARPS
@@ -52,7 +52,7 @@
`endif
`ifndef L2_ENABLE
`define L2_ENABLE (`NUM_CORES > 2)
`define L2_ENABLE 0
`endif
`ifndef L3_ENABLE

4
hw/rtl/VX_define.vh
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@@ -72,6 +72,10 @@
`define CSR_WIDTH 12
`define DIV_LATENCY 18
`define MUL_LATENCY 2
///////////////////////////////////////////////////////////////////////////////
`define BYTE_EN_NO 3'h7

2
hw/rtl/VX_lsu_unit.v
View File

@@ -116,7 +116,7 @@ module VX_lsu_unit #(
end
if (mrq_pop_part) begin
mem_rsp_mask[mrq_read_addr] <= mem_rsp_mask_upd;
assert(mrq_read_addr == dbg_mrq_write_addr);
assert(($time < 2) || mrq_read_addr == dbg_mrq_write_addr);
end
end

8
hw/rtl/libs/VX_fair_arbiter.v
View File

@@ -11,7 +11,6 @@ module VX_fair_arbiter #(
output wire grant_valid
);
if (N == 1) begin
`UNUSED_VAR (clk)
@@ -20,8 +19,7 @@ module VX_fair_arbiter #(
assign grant_onehot = requests;
assign grant_valid = requests[0];
end else begin
end else begin
reg [N-1:0] requests_use;
wire [N-1:0] update_value;
@@ -48,7 +46,7 @@ module VX_fair_arbiter #(
reg [N-1:0] grant_onehot_r;
VX_priority_encoder # (
VX_priority_encoder #(
.N(N)
) priority_encoder (
.data_in (requests_use),
@@ -61,7 +59,7 @@ module VX_fair_arbiter #(
grant_onehot_r[grant_index] = 1;
end
assign grant_onehot = grant_onehot_r;
assign late_value = ((refill_original ^ requests) & ~refill_original);
assign late_value = ((refill_original ^ requests) & ~refill_original);
assign update_value = (requests_use & ~grant_onehot_r) | late_value;
end

2
hw/rtl/libs/VX_generic_queue.v
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@@ -3,7 +3,7 @@
module VX_generic_queue #(
parameter DATAW,
parameter SIZE = 16,
parameter BUFFERED_OUTPUT = (SIZE > 8)
parameter BUFFERED_OUTPUT = 1
) (
input wire clk,
input wire reset,