Sim Work miss

2019-05-18 23:42:55 +04:00
parent 8995267cd3
commit d7afef04a9
40 changed files with 2642 additions and 10382 deletions
--- a/rtl/VX_context.v
+++ b/rtl/VX_context.v
@@ -3,7 +3,9 @@

 module VX_context (
  input wire        clk,
+  /* verilator lint_off UNUSED */
  input wire        in_warp,
+  /* verilator lint_on UNUSED */
  input wire        in_wb_warp,
  input wire        in_valid[`NT_M1:0],
  input wire        in_write_register,