cache uuid support
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@@ -96,7 +96,7 @@ module VX_alu_unit #(
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wire alu_ready_in;
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wire alu_valid_out;
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wire alu_ready_out;
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wire [63:0] alu_uuid;
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wire [`UUID_BITS-1:0] alu_uuid;
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wire [`NW_BITS-1:0] alu_wid;
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wire [`NUM_THREADS-1:0] alu_tmask;
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wire [31:0] alu_PC;
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@@ -113,7 +113,7 @@ module VX_alu_unit #(
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assign alu_ready_in = alu_ready_out || ~alu_valid_out;
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VX_pipe_register #(
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.DATAW (1 + 64 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32) + 1 + `INST_BR_BITS + 1 + 1 + 32),
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.DATAW (1 + `UUID_BITS + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32) + 1 + `INST_BR_BITS + 1 + 1 + 32),
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.RESETW (1)
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) pipe_reg (
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.clk (clk),
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@@ -139,7 +139,7 @@ module VX_alu_unit #(
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wire mul_ready_in;
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wire mul_valid_out;
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wire mul_ready_out;
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wire [63:0] mul_uuid;
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wire [`UUID_BITS-1:0] mul_uuid;
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wire [`NW_BITS-1:0] mul_wid;
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wire [`NUM_THREADS-1:0] mul_tmask;
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wire [31:0] mul_PC;
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