Fix divide edge case in verilator and move divide modules out of SYN_FUNC block within alu.

rtl/VX_alu.v

@@ -16,31 +16,11 @@ module VX_alu(
 
 		localparam div_pipeline_len = 3;
 
-		`ifdef SYN_FUNC
-		wire which_in2;
-
-		wire[31:0] ALU_in1;
-		wire[31:0] ALU_in2;
-		wire[63:0] ALU_in1_mult;
-		wire[63:0] ALU_in2_mult;
-		wire[31:0] upper_immed;
 		wire[31:0] unsigned_div_result;
         wire[31:0] unsigned_rem_result;
         wire[31:0] signed_div_result;
         wire[31:0] signed_rem_result;
 
-		reg [15:0] inst_delay;
-		reg [15:0] inst_delay_count;
-
-		assign out_alu_stall = inst_delay != 0 || inst_delay_count != 0;
-
-		assign which_in2  = in_rs2_src == `RS2_IMMED;
-
-		assign ALU_in1 = in_1;
-		assign ALU_in2 = which_in2 ? in_itype_immed : in_2;
-
-		assign upper_immed = {in_upper_immed, {12{1'b0}}};
-
         VX_divide #(
             .WIDTHN(32),
             .WIDTHD(32),
@@ -73,6 +53,58 @@ module VX_alu(
             .remainder(signed_rem_result)
         );
 
+        reg [15:0] curr_inst_delay;
+		reg [15:0] inst_delay;
+		reg inst_was_stalling;
+
+        wire inst_delay_stall = inst_was_stalling ? inst_delay != 0 : curr_inst_delay != 0;
+		assign out_alu_stall = inst_delay_stall;
+
+		always @(*) begin
+            case(in_alu_op)
+                `DIV,
+                `DIVU,
+                `REM,
+                `REMU: curr_inst_delay = div_pipeline_len;
+                default: curr_inst_delay = 0;
+            endcase // in_alu_op
+        end
+
+        always @(posedge clk or posedge reset) begin
+            if (reset) begin
+                inst_delay <= 0;
+                inst_was_stalling <= 0;
+            end
+            else if (inst_delay_stall) begin
+                if (inst_was_stalling) begin
+                    if (inst_delay > 0)
+                        inst_delay <= inst_delay - 1;
+                end
+                else begin
+                    inst_was_stalling <= 1;
+                    inst_delay <= curr_inst_delay - 1;
+                end
+            end
+            else begin
+                inst_was_stalling <= 0;
+            end
+        end
+
+		`ifdef SYN_FUNC
+		wire which_in2;
+
+		wire[31:0] ALU_in1;
+		wire[31:0] ALU_in2;
+		wire[63:0] ALU_in1_mult;
+		wire[63:0] ALU_in2_mult;
+		wire[31:0] upper_immed;
+
+		assign which_in2  = in_rs2_src == `RS2_IMMED;
+
+		assign ALU_in1 = in_1;
+		assign ALU_in2 = which_in2 ? in_itype_immed : in_2;
+
+		assign upper_immed = {in_upper_immed, {12{1'b0}}};
 
 		//always @(posedge `MUL) begin
 
@@ -116,25 +148,6 @@ module VX_alu(
 			endcase // in_alu_op
 		end
 
-		always @(*) begin
-			case(in_alu_op)
-				`DIV,
-				`DIVU,
-				`REM,
-				`REMU: inst_delay = div_pipeline_len;
-				default: inst_delay = 0;
-			endcase // in_alu_op
-		end
-
-		always @(posedge clk or posedge reset) begin
-			if (reset)
-				inst_delay_count <= 0;
-			else if (inst_delay_count > 0)
-				inst_delay_count <= inst_delay_count - 1;
-			else if (inst_delay != 0)
-				inst_delay_count <= inst_delay - 1;
-		end
-
 	`else
 		wire which_in2;
 
@@ -186,10 +199,11 @@ module VX_alu(
 				`MULH:       out_alu_result = mult_signed_result[63:32];
 				`MULHSU:     out_alu_result = mult_signed_un_result[63:32];
 				`MULHU:      out_alu_result = mult_unsigned_result[63:32];
-				`DIV:        out_alu_result = (ALU_in2 == 0) ? 32'hffffffff : $signed($signed(ALU_in1) / $signed(ALU_in2));
+				// TODO profitable to roll these exceptional cases into inst_delay to avoid pipeline when possible?
-				`DIVU:       out_alu_result = (ALU_in2 == 0) ? 32'hffffffff : ALU_in1 / ALU_in2;
+				`DIV:        out_alu_result = (ALU_in2 == 0) ? 32'hffffffff : signed_div_result;
-				`REM:        out_alu_result = (ALU_in2 == 0) ? ALU_in1 : $signed($signed(ALU_in1) % $signed(ALU_in2));
+				`DIVU:       out_alu_result = (ALU_in2 == 0) ? 32'hffffffff : unsigned_div_result;
-				`REMU:       out_alu_result = (ALU_in2 == 0) ? ALU_in1 : ALU_in1 % ALU_in2;
+				`REM:        out_alu_result = (ALU_in2 == 0) ? ALU_in1 : signed_rem_result;
+				`REMU:       out_alu_result = (ALU_in2 == 0) ? ALU_in1 : unsigned_rem_result;
 				default: out_alu_result = 32'h0;
 			endcase // in_alu_op
 		end

rtl/compat/VX_divide.v

@@ -13,8 +13,8 @@ module VX_divide
         input [WIDTHN-1:0] numer,
         input [WIDTHD-1:0] denom,
 
-        output [WIDTHN-1:0] quotient,
+        output reg [WIDTHN-1:0] quotient,
-        output [WIDTHD-1:0] remainder
+        output reg [WIDTHD-1:0] remainder
     );
 
 // synthesis read_comments_as_HDL on
@@ -53,18 +53,14 @@ module VX_divide
             );
 
         end
-        else if (PIPELINE == 0) begin
-            if (NREP == "SIGNED") begin
-                assign quotient = $signed($signed(numer)/$signed(denom));
-                assign remainder = $signed($signed(numer)%$signed(denom));
-            end
-            else begin
-                assign quotient = numer/denom;
-                assign remainder = numer%denom;
-            end
-        end
         else begin
 
+            wire [WIDTHN-1:0] numer_pipe_end;
+            wire [WIDTHD-1:0] denom_pipe_end;
+            if (PIPELINE == 0) begin
+                assign numer_pipe_end = numer;
+                assign denom_pipe_end = denom;
+            end else begin
                 reg [WIDTHN-1:0] numer_pipe [0:PIPELINE-1];
                 reg [WIDTHD-1:0] denom_pipe [0:PIPELINE-1];
 
@@ -93,18 +89,47 @@ module VX_divide
                     end
                 end
 
-            wire [WIDTHN-1:0] numer_pipe_end;
                 assign numer_pipe_end = numer_pipe[PIPELINE-1];
-            wire [WIDTHD-1:0] denom_pipe_end;
                 assign denom_pipe_end = denom_pipe[PIPELINE-1];
+            end
+
+            /* * * * * * * * * * * * * * * * * * * * * * */
+            /*  Do the actual fallback computation here  */
+            /* * * * * * * * * * * * * * * * * * * * * * */
 
             if (NREP == "SIGNED") begin
-                assign quotient = $signed($signed(numer_pipe_end)/$signed(denom_pipe_end));
+
-                assign remainder = $signed($signed(numer_pipe_end)%$signed(denom_pipe_end));
+                /*VX_divide_internal_signed #(
+                    .WIDTHN,
+                    .WIDTHD
+                )div(
+                    .numer(numer_pipe_end),
+                    .denom(denom_pipe_end),
+                    .quotient,
+                    .remainder
+                );*/
+
+                always @(*) begin
+                    if (denom_pipe_end == 0) begin
+                        quotient = 32'hffffffff;
+                        remainder = numer_pipe_end;
+                    end
+                    else if (denom_pipe_end == 32'hffffffff && numer_pipe_end == 32'h80000000) begin
+                        // this edge case kills verilator in some cases by causing a division
+                        // overflow exception. INT_MIN / -1 (on x86)
+                        quotient = 0;
+                        remainder = 0;
                     end
                     else begin
-                assign quotient = numer_pipe_end/denom_pipe_end;
+                        quotient = $signed($signed(numer_pipe_end)/$signed(denom_pipe_end));
-                assign remainder = numer_pipe_end%denom_pipe_end;
+                        remainder = $signed($signed(numer_pipe_end)%$signed(denom_pipe_end));
+                    end
+                end
+
+            end
+            else begin
+                assign quotient = (denom_pipe_end == 0) ? 32'hffffffff : numer_pipe_end/denom_pipe_end;
+                assign remainder = (denom_pipe_end == 0) ? numer_pipe_end : numer_pipe_end%denom_pipe_end;
             end
 
         end