wu-arch/vortex
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

added debug print states or rtl

Browse Source
This commit is contained in:
Blaise Tine
2020-05-16 14:19:17 -04:00
parent 65c2da76cf
commit d6c87dbb0a
24 changed files with 7100 additions and 5980 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
hw/rtl/cache/VX_bank.v vendored
View File

@@ -627,4 +627,18 @@ module VX_bank #(
|| msrq_push_stall
|| dram_fill_req_stall;
`ifdef DBG_PRINT_BANK
always_comb begin
if (1'($time & 1) && dram_fill_req_valid && dram_fill_req_ready) begin
$display("*** %t: bank%02d:%01d dram_fill req: addr=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_fill_req_addr, BANK_ID));
end
if (1'($time & 1) && dram_wb_req_valid && dram_wb_req_ready) begin
$display("*** %t: bank%02d:%01d dram_wb req: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_wb_req_addr, BANK_ID), dram_wb_req_data);
end
if (1'($time & 1) && dram_fill_rsp_valid && dram_fill_rsp_ready) begin
$display("*** %t: bank%02d:%01d dram_fill rsp: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_fill_rsp_addr, BANK_ID), dram_fill_rsp_data);
end
end
`endif
endmodule : VX_bank