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added debug print states or rtl

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This commit is contained in:
Blaise Tine
2020-05-16 14:19:17 -04:00
parent 65c2da76cf
commit d6c87dbb0a
24 changed files with 7100 additions and 5980 deletions
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14
hw/rtl/cache/VX_bank.v vendored
View File

@@ -627,4 +627,18 @@ module VX_bank #(
|| msrq_push_stall
|| dram_fill_req_stall;
`ifdef DBG_PRINT_BANK
always_comb begin
if (1'($time & 1) && dram_fill_req_valid && dram_fill_req_ready) begin
$display("*** %t: bank%02d:%01d dram_fill req: addr=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_fill_req_addr, BANK_ID));
end
if (1'($time & 1) && dram_wb_req_valid && dram_wb_req_ready) begin
$display("*** %t: bank%02d:%01d dram_wb req: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_wb_req_addr, BANK_ID), dram_wb_req_data);
end
if (1'($time & 1) && dram_fill_rsp_valid && dram_fill_rsp_ready) begin
$display("*** %t: bank%02d:%01d dram_fill rsp: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_fill_rsp_addr, BANK_ID), dram_fill_rsp_data);
end
end
`endif
endmodule : VX_bank

4
hw/rtl/cache/VX_cache_config.vh vendored
View File

@@ -70,6 +70,8 @@
`define DRAM_TO_LINE_ADDR(x) x[`DRAM_ADDR_WIDTH-1:`BANK_SELECT_BITS]
`define LINE_TO_DRAM_ADDR(x, i) {x, (`BANK_SELECT_BITS)'(i)};
`define LINE_TO_DRAM_ADDR(x, i) {x, `BANK_SELECT_BITS'(i)}
`define LINE_TO_BYTE_ADDR(x, i) {x, `BANK_SELECT_BITS'(i), `BASE_ADDR_BITS'(0)}
`endif

6
hw/rtl/cache/VX_snp_forwarder.v vendored
View File

@@ -112,7 +112,8 @@ module VX_snp_forwarder #(
assign snp_fwdin_ready[i] = fwdin_ready && (fwdin_sel == `REQS_BITS'(i));
end
/*always_comb begin
`ifdef DBG_PRINT_SNP_FWD
always_comb begin
if (1'($time & 1) && snp_req_valid && snp_req_ready) begin
$display("*** %t: snp req: addr=%0h, tag=%0h", $time, snp_req_addr, snp_req_tag);
end
@@ -125,6 +126,7 @@ module VX_snp_forwarder #(
if (1'($time & 1) && snp_rsp_valid && snp_rsp_ready) begin
$display("*** %t: snp rsp: addr=%0h, tag=%0h", $time, snp_rsp_addr, snp_rsp_tag);
end
end*/
end
`endif
endmodule