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added debug print states or rtl

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This commit is contained in:
Blaise Tine
2020-05-16 14:19:17 -04:00
parent 65c2da76cf
commit d6c87dbb0a
24 changed files with 7100 additions and 5980 deletions
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6
hw/rtl/VX_icache_stage.v
View File

@@ -62,13 +62,15 @@ module VX_icache_stage #(
end
end
/*always_comb begin
`ifdef DBG_PRINT_CORE_ICACHE
always_comb begin
if (1'($time & 1) && icache_req_if.core_req_ready && icache_req_if.core_req_valid) begin
$display("*** %t: I%01d$ req: tag=%0h, pc=%0h, warp=%0d", $time, CORE_ID, icache_req_if.core_req_tag, fe_inst_meta_fi.inst_pc, fe_inst_meta_fi.warp_num);
end
if (1'($time & 1) && icache_rsp_if.core_rsp_ready && icache_rsp_if.core_rsp_valid) begin
$display("*** %t: I%01d$ rsp: tag=%0h, pc=%0h, warp=%0d, instr=%0h", $time, CORE_ID, icache_rsp_if.core_rsp_tag, fe_inst_meta_id.inst_pc, fe_inst_meta_id.warp_num, fe_inst_meta_id.instruction);
end
end*/
end
`endif
endmodule

6
hw/rtl/VX_lsu_unit.v
View File

@@ -62,14 +62,16 @@ module VX_lsu_unit #(
assign dcache_rsp_if.core_rsp_ready = ~no_slot_mem;
assign {mem_wb_if.pc, mem_wb_if.wb, mem_wb_if.rd, mem_wb_if.warp_num} = dcache_rsp_if.core_rsp_tag;
/*always_comb begin
`ifdef DBG_PRINT_CORE_DCACHE
always_comb begin
if (1'($time & 1) && dcache_req_if.core_req_ready && (| dcache_req_if.core_req_valid)) begin
$display("*** %t: D%01d$ req: valid=%b, addr=%0h, tag=%0h, r=%0d, w=%0d, pc=%0h, rd=%0d, warp=%0d, data=%0h", $time, CORE_ID, use_valid, use_address, dcache_req_if.core_req_tag, use_mem_read, use_mem_write, use_pc, use_rd, use_warp_num, use_store_data);
end
if (1'($time & 1) && dcache_rsp_if.core_rsp_ready && (| dcache_rsp_if.core_rsp_valid)) begin
$display("*** %t: D%01d$ rsp: valid=%b, tag=%0h, pc=%0h, rd=%0d, warp=%0d, data=%0h", $time, CORE_ID, mem_wb_if.valid, dcache_rsp_if.core_rsp_tag, mem_wb_if.pc, mem_wb_if.rd, mem_wb_if.warp_num, mem_wb_if.data);
end
end*/
end
`endif
endmodule

6
hw/rtl/Vortex_Socket.v
View File

@@ -328,13 +328,15 @@ module Vortex_Socket (
);
end
/*always_comb begin
`ifdef DBG_PRINT_DRAM
always_comb begin
if (1'($time & 1) && (dram_req_read || dram_req_write) && dram_req_ready) begin
$display("*** %t: DRAM req: w=%b addr=%0h, tag=%0h, data=%0h", $time, dram_req_write, {dram_req_addr, `CLOG2(`GLOBAL_BLOCK_SIZE)'(0)}, dram_req_tag, dram_req_data);
end
if (1'($time & 1) && dram_rsp_valid && dram_rsp_ready) begin
$display("*** %t: DRAM rsp: tag=%0h, data=%0h", $time, dram_rsp_tag, dram_rsp_data);
end
end*/
end
`endif
endmodule

14
hw/rtl/cache/VX_bank.v vendored
View File

@@ -627,4 +627,18 @@ module VX_bank #(
|| msrq_push_stall
|| dram_fill_req_stall;
`ifdef DBG_PRINT_BANK
always_comb begin
if (1'($time & 1) && dram_fill_req_valid && dram_fill_req_ready) begin
$display("*** %t: bank%02d:%01d dram_fill req: addr=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_fill_req_addr, BANK_ID));
end
if (1'($time & 1) && dram_wb_req_valid && dram_wb_req_ready) begin
$display("*** %t: bank%02d:%01d dram_wb req: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_wb_req_addr, BANK_ID), dram_wb_req_data);
end
if (1'($time & 1) && dram_fill_rsp_valid && dram_fill_rsp_ready) begin
$display("*** %t: bank%02d:%01d dram_fill rsp: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_fill_rsp_addr, BANK_ID), dram_fill_rsp_data);
end
end
`endif
endmodule : VX_bank

4
hw/rtl/cache/VX_cache_config.vh vendored
View File

@@ -70,6 +70,8 @@
`define DRAM_TO_LINE_ADDR(x) x[`DRAM_ADDR_WIDTH-1:`BANK_SELECT_BITS]
`define LINE_TO_DRAM_ADDR(x, i) {x, (`BANK_SELECT_BITS)'(i)};
`define LINE_TO_DRAM_ADDR(x, i) {x, `BANK_SELECT_BITS'(i)}
`define LINE_TO_BYTE_ADDR(x, i) {x, `BANK_SELECT_BITS'(i), `BASE_ADDR_BITS'(0)}
`endif

6
hw/rtl/cache/VX_snp_forwarder.v vendored
View File

@@ -112,7 +112,8 @@ module VX_snp_forwarder #(
assign snp_fwdin_ready[i] = fwdin_ready && (fwdin_sel == `REQS_BITS'(i));
end
/*always_comb begin
`ifdef DBG_PRINT_SNP_FWD
always_comb begin
if (1'($time & 1) && snp_req_valid && snp_req_ready) begin
$display("*** %t: snp req: addr=%0h, tag=%0h", $time, snp_req_addr, snp_req_tag);
end
@@ -125,6 +126,7 @@ module VX_snp_forwarder #(
if (1'($time & 1) && snp_rsp_valid && snp_rsp_ready) begin
$display("*** %t: snp rsp: addr=%0h, tag=%0h", $time, snp_rsp_addr, snp_rsp_tag);
end
end*/
end
`endif
endmodule

25
hw/rtl/libs/VX_encoder_onehot.v Normal file
View File

@@ -0,0 +1,25 @@
`include "VX_define.vh"
module VX_encoder_onehot #(
parameter N = 6
) (
input wire [N-1:0] onehot,
output reg valid,
output reg [`LOG2UP(N)-1:0] value
);
integer i;
always @(*) begin
valid = 1'b0;
value = {`LOG2UP(N){1'bx}};
for (i = 0; i < N; i++) begin
if (onehot[i]) begin
valid = 1'b1;
value = `LOG2UP(N)'(i);
break;
end
end
end
endmodule

63
hw/rtl/libs/VX_matrix_arbiter.v
View File

@@ -3,54 +3,51 @@
module VX_matrix_arbiter #(
parameter N = 0
) (
input wire clk,
input wire reset,
input wire [N-1:0] inputs,
output wire [N-1:0] grant
input wire clk,
input wire reset,
input wire [N-1:0] requests,
output wire grant_valid,
output wire [N-1:0] grant_onehot,
output wire [`LOG2UP(N)-1:0] grant_index
);
reg [N-1:1][N-1:0] pri;
reg [N-1:0] state [0:N-1];
wire [N-1:0] dis [0:N-1];
always @(posedge clk) begin
if (reset) begin
integer i, j;
for (i = 0; i < N; ++i) begin
for (j = 0; j < N; ++j) begin
pri[i][j] <= 1;
genvar i, j;
for (i = 0; i < N; ++i) begin
for (j = i + 1; j < N; ++j) begin
always @(posedge clk) begin
if (reset) begin
state[i][j] <= 0;
end else begin
state[i][j] <= (state[i][j] || grant_onehot[j]) && ~grant_onehot[i];
end
end
end else begin
integer i, j;
for (i = 0; i < N; ++i) begin
if (grant[i]) begin
for (j = 0; j < N; ++j) begin
if (j > i)
pri[j][i] <= 1;
else if (j < i)
pri[i][j] <= 0;
end
end
end
end
end
genvar i, j;
end
for (i = 0; i < N; ++i) begin
wire [N-1:0] dis;
for (j = 0; j < N; ++j) begin
if (j > i) begin
assign dis[j] = inputs[j] & pri[j][i];
assign dis[j][i] = requests[i] & state[i][j];
end else if (j < i) begin
assign dis[j] = inputs[j] & ~pri[i][j];
assign dis[j][i] = requests[i] & ~state[j][i];
end else begin
assign dis[j] = 0;
assign dis[j][i] = 0;
end
end
assign grant[i] = inputs[i] & ~(| dis);
assign grant_onehot[i] = requests[i] & ~(| dis[i]);
end
VX_encoder_onehot #(
.N(N)
) encoder (
.onehot(grant_onehot),
.valid(grant_valid),
.value(grant_index)
);
endmodule