cache req datapath optimizations
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19
hw/rtl/cache/VX_bank.v
vendored
19
hw/rtl/cache/VX_bank.v
vendored
@@ -264,7 +264,9 @@ module VX_bank #(
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.full (creq_full)
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);
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reg [$clog2(MSHR_SIZE+1)-1:0] mshr_pending_size;
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reg [$clog2(MSHR_SIZE+1)-1:0] mshr_pending_size;
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wire [$clog2(MSHR_SIZE+1)-1:0] mshr_pending_size_n;
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reg mshr_going_full;
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wire mshr_pop;
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wire mshr_valid_st0;
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wire[`REQS_BITS-1:0] mshr_tid_st0;
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@@ -346,14 +348,12 @@ module VX_bank #(
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wire dreq_push_stall;
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wire srsq_push_stall;
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wire pipeline_stall;
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wire is_mshr_miss_st2 = valid_st2 && is_mshr_st2 && (miss_st2 || force_miss_st2);
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wire is_mshr_miss_st3 = valid_st3 && is_mshr_st3 && (miss_st3 || force_miss_st3);
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wire creq_commit = valid_st1 && core_req_hit_st1 && !pipeline_stall;
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wire mshr_going_full = (mshr_pending_size == MSHR_SIZE);
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// determine which queue to pop next in piority order
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wire mshr_pop_unqual = mshr_valid_st0;
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wire drsq_pop_unqual = !mshr_pop_unqual && !drsq_empty;
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@@ -367,13 +367,16 @@ module VX_bank #(
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assign sreq_pop = sreq_pop_unqual && !pipeline_stall;
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// MSHR pending size
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assign mshr_pending_size_n = mshr_pending_size +
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((creq_pop && !creq_commit) ? 1 : ((creq_commit && !creq_pop) ? -1 : 0));
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always @(posedge clk) begin
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if (reset) begin
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mshr_pending_size <= 0;
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mshr_going_full <= 0;
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end else begin
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mshr_pending_size <= mshr_pending_size +
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((creq_pop && !creq_commit) ? 1 : ((creq_commit && !creq_pop) ? -1 : 0));
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end
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mshr_pending_size <= mshr_pending_size_n;
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mshr_going_full <= (mshr_pending_size_n == MSHR_SIZE);
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end
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end
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assign is_mshr_st0 = mshr_pop_unqual;
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@@ -736,7 +739,7 @@ end
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.enqueue_byteen_st3 (req_byteen_st3),
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.enqueue_is_snp_st3 (is_snp_st3),
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.enqueue_snp_inv_st3(snp_inv_st3),
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.enqueue_mshr_st3 (is_mshr_st3),
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.enqueue_is_mshr_st3(is_mshr_st3),
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.enqueue_ready_st3 (mshr_init_ready_state_st3),
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.enqueue_full (mshr_full),
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