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cache req datapath optimizations

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This commit is contained in:
Blaise Tine
2020-12-08 02:58:08 -08:00
parent 268ad15098
commit d5fa82f5e4
17 changed files with 393 additions and 410 deletions
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10
hw/rtl/VX_dcache_arb.v
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@@ -36,7 +36,7 @@ module VX_dcache_arb (
wire core_req_valid;
VX_skid_buffer #(
.DATAW (REQ_DATAW)
.DATAW (REQ_DATAW)
) req_buffer (
.clk (clk),
.reset (reset),
@@ -121,9 +121,10 @@ module VX_dcache_arb (
assign rsp_valid_in[2] = (| io_rsp_if.valid);
VX_stream_arbiter #(
.NUM_REQS (3),
.DATAW (RSP_DATAW),
.BUFFERED (1)
.NUM_REQS (3),
.DATAW (RSP_DATAW),
.IN_BUFFER (1),
.OUT_BUFFER (1)
) rsp_arb (
.clk (clk),
.reset (reset),
@@ -138,6 +139,7 @@ module VX_dcache_arb (
assign cache_rsp_if.ready = rsp_ready_in[0];
assign smem_rsp_if.ready = rsp_ready_in[1];
assign io_rsp_if.ready = rsp_ready_in[2];
assign core_rsp_if.valid = core_rsp_tmask & {`NUM_THREADS{core_rsp_valid}};
endmodule