merging perf counters
This commit is contained in:
Blaise Tine
178
hw/rtl/cache/VX_cache.v
vendored
178
hw/rtl/cache/VX_cache.v
vendored
@@ -70,7 +70,12 @@ module VX_cache #(
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output wire [NUM_REQS-1:0][`WORD_WIDTH-1:0] core_rsp_data,
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output wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] core_rsp_tag,
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input wire [`CORE_REQ_TAG_COUNT-1:0] core_rsp_ready,
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// PERF
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`ifdef PERF_ENABLE
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VX_perf_cache_if perf_cache_if,
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`endif
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// DRAM request
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output wire dram_req_valid,
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output wire dram_req_rw,
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@@ -130,7 +135,16 @@ module VX_cache #(
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wire [NUM_BANKS-1:0] per_bank_miss;
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assign miss_vec = per_bank_miss;
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`ifdef PERF_ENABLE
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wire [NUM_BANKS-1:0] perf_mshr_stall_per_bank;
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wire [NUM_BANKS-1:0] perf_pipe_stall_per_bank;
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wire [NUM_BANKS-1:0] perf_evict_per_bank;
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wire [NUM_BANKS-1:0] perf_read_miss_per_bank;
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wire [NUM_BANKS-1:0] perf_write_miss_per_bank;
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`endif
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if (NUM_BANKS == 1) begin
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assign snp_req_ready = per_bank_snp_req_ready;
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end else begin
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@@ -139,9 +153,9 @@ module VX_cache #(
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VX_cache_core_req_bank_sel #(
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.BANK_LINE_SIZE (BANK_LINE_SIZE),
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.NUM_BANKS (NUM_BANKS),
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.WORD_SIZE (WORD_SIZE),
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.NUM_REQS (NUM_REQS),
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.NUM_BANKS (NUM_BANKS),
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.WORD_SIZE (WORD_SIZE),
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.NUM_REQS (NUM_REQS),
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.CORE_TAG_ID_BITS (CORE_TAG_ID_BITS)
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) cache_core_req_bank_sel (
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.core_req_valid (core_req_valid),
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@@ -312,6 +326,14 @@ module VX_cache #(
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.dram_rsp_addr (curr_bank_dram_rsp_addr),
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.dram_rsp_ready (curr_bank_dram_rsp_ready),
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`ifdef PERF_ENABLE
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.perf_mshr_stall (perf_mshr_stall_per_bank[i]),
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.perf_pipe_stall (perf_pipe_stall_per_bank[i]),
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.perf_evict (perf_evict_per_bank[i]),
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.perf_read_miss (perf_read_miss_per_bank[i]),
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.perf_write_miss (perf_write_miss_per_bank[i]),
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`endif
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// Snoop request
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.snp_req_valid (curr_bank_snp_req_valid),
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.snp_req_addr (curr_bank_snp_req_addr),
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@@ -408,4 +430,150 @@ module VX_cache #(
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`UNUSED_VAR (snp_rsp_ready)
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end
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`ifdef PERF_ENABLE
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// per cycle: core_req_r, core_req_w
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reg [($clog2(NUM_REQS+1)-1):0] perf_core_req_r_per_cycle, perf_core_req_w_per_cycle;
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reg [($clog2(NUM_REQS+1)-1):0] perf_crsp_stall_per_cycle;
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if (CORE_TAG_ID_BITS != 0) begin
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VX_countones #( // core_req_r
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.N(NUM_REQS)
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) perf_countones_core_req_r_count (
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.valids (core_req_valid & {NUM_REQS{core_req_ready & ~core_req_rw}}),
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.count (perf_core_req_r_per_cycle)
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);
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VX_countones #( // core_req_w
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.N(NUM_REQS)
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) perf_countones_core_req_w_count (
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.valids (core_req_valid & {NUM_REQS{core_req_ready & core_req_rw}}),
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.count (perf_core_req_w_per_cycle)
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);
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VX_countones #( // core_rsp
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.N(NUM_REQS)
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) perf_countones_core_rsp_count (
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.valids (core_rsp_valid & {NUM_REQS{!core_rsp_ready}}),
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.count (perf_crsp_stall_per_cycle)
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);
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end else begin
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VX_countones #( // core_req_r
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.N(NUM_REQS)
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) perf_countones_core_req_r_count (
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.valids (core_req_valid & core_req_ready & ~core_req_rw),
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.count (perf_core_req_r_per_cycle)
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);
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VX_countones #( // core_req_w
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.N(NUM_REQS)
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) perf_countones_core_req_w_count (
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.valids (core_req_valid & core_req_ready & core_req_rw),
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.count (perf_core_req_w_per_cycle)
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);
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VX_countones #( // core_rsp
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.N(NUM_REQS)
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) perf_countones_core_rsp_count (
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.valids (core_rsp_valid & ~core_rsp_ready),
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.count (perf_crsp_stall_per_cycle)
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);
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end
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// per cycle: msrq stalls, pipeline stalls, evictions, read misses, write misses
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reg [($clog2(NUM_BANKS+1)-1):0] perf_mshr_stall_per_cycle;
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reg [($clog2(NUM_BANKS+1)-1):0] perf_pipe_stall_per_cycle;
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reg [($clog2(NUM_BANKS+1)-1):0] perf_evictions_per_cycle;
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reg [($clog2(NUM_BANKS+1)-1):0] perf_read_miss_per_cycle;
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reg [($clog2(NUM_BANKS+1)-1):0] perf_write_miss_per_cycle;
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VX_countones #(
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.N(NUM_BANKS)
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) perf_countones_mshr_stall_count (
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.valids (perf_mshr_stall_per_bank),
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.count (perf_mshr_stall_per_cycle)
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);
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VX_countones #(
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.N(NUM_BANKS)
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) perf_countones_total_stall_count (
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.valids (perf_pipe_stall_per_bank),
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.count (perf_pipe_stall_per_cycle)
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);
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VX_countones #(
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.N(NUM_BANKS)
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) perf_countones_EVICTSict_count (
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.valids (perf_evict_per_bank),
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.count (perf_evictions_per_cycle)
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);
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VX_countones #(
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.N(NUM_BANKS)
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) perf_countones_read_miss_count (
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.valids (perf_read_miss_per_bank),
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.count (perf_read_miss_per_cycle)
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);
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VX_countones #(
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.N(NUM_BANKS)
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) perf_countones_write_miss_count (
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.valids (perf_write_miss_per_bank),
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.count (perf_write_miss_per_cycle)
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);
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reg [63:0] perf_core_req_r;
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reg [63:0] perf_core_req_w;
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reg [63:0] perf_mshr_stall;
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reg [63:0] perf_pipe_stall;
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reg [63:0] perf_evictions;
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reg [63:0] perf_read_miss;
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reg [63:0] perf_write_miss;
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reg [63:0] perf_crsp_stall;
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reg [63:0] perf_dreq_stall;
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always @(posedge clk) begin
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if (reset) begin
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perf_core_req_r <= 0;
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perf_core_req_w <= 0;
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perf_crsp_stall <= 0;
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perf_mshr_stall <= 0;
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perf_pipe_stall <= 0;
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perf_evictions <= 0;
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perf_read_miss <= 0;
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perf_write_miss <= 0;
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perf_dreq_stall <= 0;
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end else begin
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// core requests
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perf_core_req_r <= perf_core_req_r + $bits(perf_core_req_r)'(perf_core_req_r_per_cycle);
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perf_core_req_w <= perf_core_req_w + $bits(perf_core_req_w)'(perf_core_req_w_per_cycle);
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// core response stalls
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perf_crsp_stall <= perf_crsp_stall + $bits(perf_crsp_stall)'(perf_crsp_stall_per_cycle);
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// miss reserve queue stalls
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perf_mshr_stall <= perf_mshr_stall + $bits(perf_mshr_stall)'(perf_mshr_stall_per_cycle);
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// pipeline stalls
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perf_pipe_stall <= perf_pipe_stall + $bits(perf_pipe_stall)'(perf_pipe_stall_per_cycle);
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// total evictions
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perf_evictions <= perf_evictions + $bits(perf_evictions)'(perf_evictions_per_cycle);
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// read misses
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perf_read_miss <= perf_read_miss + $bits(perf_read_miss)'(perf_read_miss_per_cycle);
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// write misses
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perf_write_miss <= perf_write_miss + $bits(perf_write_miss)'(perf_write_miss_per_cycle);
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// dram request stalls
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if (dram_req_valid & !dram_req_ready) begin
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perf_dreq_stall <= perf_dreq_stall + 64'd1;
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end
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end
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end
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assign perf_cache_if.reads = perf_core_req_r;
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assign perf_cache_if.writes = perf_core_req_w;
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assign perf_cache_if.read_misses = perf_read_miss;
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assign perf_cache_if.write_misses = perf_write_miss;
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assign perf_cache_if.evictions = perf_evictions;
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assign perf_cache_if.mshr_stalls = perf_mshr_stall;
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assign perf_cache_if.pipe_stalls = perf_pipe_stall;
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assign perf_cache_if.crsp_stalls = perf_crsp_stall;
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assign perf_cache_if.dreq_stalls = perf_dreq_stall;
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`endif
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endmodule
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