merging perf counters
This commit is contained in:
Blaise Tine
@@ -91,24 +91,240 @@ extern int vx_upload_kernel_file(vx_device_h device, const char* filename) {
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return err;
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}
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extern int vx_get_perf(vx_device_h device, int core_id, size_t* instrs, size_t* cycles) {
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int vx_csr_get_l(vx_device_h device, int core_id, int addr, int addr_h, uint64_t* value) {
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int ret = 0;
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unsigned value_lo, value_hi;
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ret |= vx_csr_get(device, core_id, addr, &value_lo);
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ret |= vx_csr_get(device, core_id, addr_h, &value_hi);
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*value = (uint64_t(value_hi) << 32) | value_lo;
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return ret;
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}
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extern int vx_dump_perf(vx_device_h device, FILE* stream) {
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int ret = 0;
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unsigned value;
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if (instrs) {
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ret |= vx_csr_get(device, core_id, CSR_INSTRET_H, &value);
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*instrs = value;
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ret |= vx_csr_get(device, core_id, CSR_INSTRET, &value);
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*instrs = (*instrs << 32) | value;
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}
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unsigned num_cores;
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vx_csr_get(device, 0, CSR_NC, &num_cores);
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if (cycles) {
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ret |= vx_csr_get(device, core_id, CSR_CYCLE_H, &value);
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*cycles = value;
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ret |= vx_csr_get(device, core_id, CSR_CYCLE, &value);
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*cycles = (*cycles << 32) | value;
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}
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uint64_t instrs = 0;
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uint64_t cycles = 0;
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#ifdef PERF_ENABLE
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// PERF: pipeline stalls
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uint64_t lsu_stalls = 0;
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uint64_t fpu_stalls = 0;
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uint64_t mul_stalls = 0;
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uint64_t csr_stalls = 0;
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uint64_t alu_stalls = 0;
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uint64_t gpu_stalls = 0;
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uint64_t ibuffer_stalls = 0;
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uint64_t scoreboard_stalls = 0;
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uint64_t icache_stalls = 0;
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// PERF: Icache
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uint64_t icache_reads = 0;
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uint64_t icache_read_misses = 0;
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uint64_t icache_pipe_stalls = 0;
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uint64_t icache_dram_stalls = 0;
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uint64_t icache_mshr_stalls = 0;
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uint64_t icache_rsp_stalls = 0;
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// PERF: Dcache
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uint64_t dcache_reads = 0;
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uint64_t dcache_writes = 0;
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uint64_t dcache_read_misses = 0;
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uint64_t dcache_write_misses = 0;
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uint64_t dcache_pipe_stalls = 0;
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uint64_t dcache_dram_stalls = 0;
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uint64_t dcache_mshr_stalls = 0;
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uint64_t dcache_rsp_stalls = 0;
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uint64_t dcache_evictions = 0;
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// PERF: memory
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uint64_t dram_req = 0;
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uint64_t dram_rsp = 0;
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uint64_t dram_lat = 0;
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#endif
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for (unsigned core_id = 0; core_id < num_cores; ++core_id) {
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uint64_t instrs_per_core, cycles_per_core;
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ret |= vx_csr_get_l(device, core_id, CSR_MINSTRET, CSR_MINSTRET_H, &instrs_per_core);
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ret |= vx_csr_get_l(device, core_id, CSR_MCYCLE, CSR_MCYCLE_H, &cycles_per_core);
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float IPC = (float)(double(instrs_per_core) / double(cycles_per_core));
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if (num_cores > 1) fprintf(stream, "PERF: core%d: instrs=%ld, cycles=%ld, IPC=%f\n", core_id, instrs_per_core, cycles_per_core, IPC);
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instrs += instrs_per_core;
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cycles = std::max<uint64_t>(cycles_per_core, cycles);
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#ifdef PERF_ENABLE
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// PERF: pipeline
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// icache_stall
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uint64_t icache_stalls_per_core;
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ret |= vx_csr_get_l(device, core_id, CSR_MPM_ICACHE_ST, CSR_MPM_ICACHE_ST_H, &icache_stalls_per_core);
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if (num_cores > 1) fprintf(stream, "PERF: core%d: icache stalls=%ld\n", core_id, icache_stalls_per_core);
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icache_stalls += icache_stalls_per_core;
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// ibuffer_stall
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uint64_t ibuffer_stalls_per_core;
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ret |= vx_csr_get_l(device, core_id, CSR_MPM_IBUF_ST, CSR_MPM_IBUF_ST_H, &ibuffer_stalls_per_core);
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if (num_cores > 1) fprintf(stream, "PERF: core%d: ibuffer stalls=%ld\n", core_id, ibuffer_stalls_per_core);
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ibuffer_stalls += ibuffer_stalls_per_core;
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// scoreboard_stall
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uint64_t scoreboard_stalls_per_core;
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ret |= vx_csr_get_l(device, core_id, CSR_MPM_SCRB_ST, CSR_MPM_SCRB_ST_H, &scoreboard_stalls_per_core);
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if (num_cores > 1) fprintf(stream, "PERF: core%d: scoreboard stalls=%ld\n", core_id, scoreboard_stalls_per_core);
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scoreboard_stalls += scoreboard_stalls_per_core;
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// alu_stall
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uint64_t alu_stalls_per_core;
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ret |= vx_csr_get_l(device, core_id, CSR_MPM_ALU_ST, CSR_MPM_ALU_ST_H, &alu_stalls_per_core);
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if (num_cores > 1) fprintf(stream, "PERF: core%d: alu stalls=%ld\n", core_id, alu_stalls_per_core);
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alu_stalls += alu_stalls_per_core;
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// lsu_stall
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uint64_t lsu_stalls_per_core;
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ret |= vx_csr_get_l(device, core_id, CSR_MPM_LSU_ST, CSR_MPM_LSU_ST_H, &lsu_stalls_per_core);
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if (num_cores > 1) fprintf(stream, "PERF: core%d: lsu stalls=%ld\n", core_id, lsu_stalls_per_core);
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lsu_stalls += lsu_stalls_per_core;
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// csr_stall
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uint64_t csr_stalls_per_core;
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ret |= vx_csr_get_l(device, core_id, CSR_MPM_CSR_ST, CSR_MPM_CSR_ST_H, &csr_stalls_per_core);
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if (num_cores > 1) fprintf(stream, "PERF: core%d: csr stalls=%ld\n", core_id, csr_stalls_per_core);
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csr_stalls += csr_stalls_per_core;
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// mul_stall
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uint64_t mul_stalls_per_core;
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ret |= vx_csr_get_l(device, core_id, CSR_MPM_MUL_ST, CSR_MPM_MUL_ST_H, &mul_stalls_per_core);
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if (num_cores > 1) fprintf(stream, "PERF: core%d: mul stalls=%ld\n", core_id, mul_stalls_per_core);
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mul_stalls += mul_stalls_per_core;
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// fpu_stall
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uint64_t fpu_stalls_per_core;
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ret |= vx_csr_get_l(device, core_id, CSR_MPM_FPU_ST, CSR_MPM_FPU_ST_H, &fpu_stalls_per_core);
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if (num_cores > 1) fprintf(stream, "PERF: core%d: fpu stalls=%ld\n", core_id, fpu_stalls_per_core);
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fpu_stalls += fpu_stalls_per_core;
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// gpu_stall
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uint64_t gpu_stalls_per_core;
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ret |= vx_csr_get_l(device, core_id, CSR_MPM_GPU_ST, CSR_MPM_GPU_ST_H, &gpu_stalls_per_core);
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if (num_cores > 1) fprintf(stream, "PERF: core%d: gpu stalls=%ld\n", core_id, gpu_stalls_per_core);
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gpu_stalls += gpu_stalls_per_core;
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// PERF: Icache
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// total reads
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uint64_t icache_reads_per_core;
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ret |= vx_csr_get_l(device, core_id, CSR_MPM_ICACHE_READS, CSR_MPM_ICACHE_READS_H, &icache_reads_per_core);
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if (num_cores > 1) fprintf(stream, "PERF: core%d: icache reads=%ld\n", core_id, icache_reads_per_core);
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icache_reads += icache_reads_per_core;
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// read misses
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uint64_t icache_miss_r_per_core;
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ret |= vx_csr_get_l(device, core_id, CSR_MPM_ICACHE_MISS_R, CSR_MPM_ICACHE_MISS_R_H, &icache_miss_r_per_core);
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if (num_cores > 1) fprintf(stream, "PERF: core%d: icache read misses=%ld\n", core_id, icache_miss_r_per_core);
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icache_read_misses += icache_miss_r_per_core;
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// pipeline stalls
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uint64_t icache_pipe_st_per_core;
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ret |= vx_csr_get_l(device, core_id, CSR_MPM_ICACHE_PIPE_ST, CSR_MPM_ICACHE_PIPE_ST_H, &icache_pipe_st_per_core);
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if (num_cores > 1) fprintf(stream, "PERF: core%d: icache pipeline stalls=%ld\n", core_id, icache_pipe_st_per_core);
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icache_pipe_stalls += icache_pipe_st_per_core;
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// response stalls
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uint64_t icache_crsp_st_per_core;
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ret |= vx_csr_get_l(device, core_id, CSR_MPM_ICACHE_CRSP_ST, CSR_MPM_ICACHE_CRSP_ST_H, &icache_crsp_st_per_core);
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if (num_cores > 1) fprintf(stream, "PERF: core%d: icache reponse stalls=%ld\n", core_id, icache_crsp_st_per_core);
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icache_rsp_stalls += icache_crsp_st_per_core;
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// dram_stalls
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uint64_t icache_dram_st_per_core;
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ret |= vx_csr_get_l(device, core_id, CSR_MPM_ICACHE_DREQ_ST, CSR_MPM_ICACHE_DREQ_ST_H, &icache_dram_st_per_core);
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if (num_cores > 1) fprintf(stream, "PERF: core%d: icache dram stalls=%ld\n", core_id, icache_dram_st_per_core);
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icache_dram_stalls += icache_dram_st_per_core;
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// mshr_stalls
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uint64_t icache_mshr_st_per_core;
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ret |= vx_csr_get_l(device, core_id, CSR_MPM_ICACHE_MSHR_ST, CSR_MPM_ICACHE_MSHR_ST_H, &icache_mshr_st_per_core);
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if (num_cores > 1) fprintf(stream, "PERF: core%d: icache mshr stalls=%ld\n", core_id, icache_mshr_st_per_core);
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icache_mshr_stalls += icache_mshr_st_per_core;
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// PERF: Dcache
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// total reads
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uint64_t dcache_reads_per_core;
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ret |= vx_csr_get_l(device, core_id, CSR_MPM_DCACHE_READS, CSR_MPM_DCACHE_READS_H, &dcache_reads_per_core);
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if (num_cores > 1) fprintf(stream, "PERF: core%d: dcache reads=%ld\n", core_id, dcache_reads_per_core);
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dcache_reads += dcache_reads_per_core;
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// total write
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uint64_t dcache_writes_per_core;
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ret |= vx_csr_get_l(device, core_id, CSR_MPM_DCACHE_WRITES, CSR_MPM_DCACHE_WRITES_H, &dcache_writes_per_core);
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if (num_cores > 1) fprintf(stream, "PERF: core%d: dcache writes=%ld\n", core_id, dcache_writes_per_core);
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dcache_writes += dcache_writes_per_core;
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// read misses
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uint64_t dcache_miss_r_per_core;
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ret |= vx_csr_get_l(device, core_id, CSR_MPM_DCACHE_MISS_R, CSR_MPM_DCACHE_MISS_R_H, &dcache_miss_r_per_core);
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if (num_cores > 1) fprintf(stream, "PERF: core%d: dcache read misses=%ld\n", core_id, dcache_miss_r_per_core);
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dcache_read_misses += dcache_miss_r_per_core;
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// read misses
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uint64_t dcache_miss_w_per_core;
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ret |= vx_csr_get_l(device, core_id, CSR_MPM_DCACHE_MISS_W, CSR_MPM_DCACHE_MISS_W_H, &dcache_miss_w_per_core);
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if (num_cores > 1) fprintf(stream, "PERF: core%d: dcache wrire misses=%ld\n", core_id, dcache_miss_w_per_core);
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dcache_write_misses += dcache_miss_w_per_core;
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// total_evictions
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uint64_t dcache_evictions_per_core;
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ret |= vx_csr_get_l(device, core_id, CSR_MPM_DCACHE_EVICTS, CSR_MPM_DCACHE_EVICTS_H, &dcache_evictions_per_core);
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if (num_cores > 1) fprintf(stream, "PERF: core%d: dcache evictions_per_core=%ld\n", core_id, dcache_evictions_per_core);
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dcache_evictions += dcache_evictions_per_core;
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// pipeline stalls
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uint64_t dcache_pipe_st_per_core;
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ret |= vx_csr_get_l(device, core_id, CSR_MPM_DCACHE_PIPE_ST, CSR_MPM_DCACHE_PIPE_ST_H, &dcache_pipe_st_per_core);
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if (num_cores > 1) fprintf(stream, "PERF: core%d: dcache pipeline stalls=%ld\n", core_id, dcache_pipe_st_per_core);
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dcache_pipe_stalls += dcache_pipe_st_per_core;
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// response stalls
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uint64_t dcache_crsp_st_per_core;
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ret |= vx_csr_get_l(device, core_id, CSR_MPM_DCACHE_CRSP_ST, CSR_MPM_DCACHE_CRSP_ST_H, &dcache_crsp_st_per_core);
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if (num_cores > 1) fprintf(stream, "PERF: core%d: dcache reponse stalls=%ld\n", core_id, dcache_crsp_st_per_core);
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dcache_rsp_stalls += dcache_crsp_st_per_core;
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// dram_stalls
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uint64_t dcache_dram_st_per_core;
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ret |= vx_csr_get_l(device, core_id, CSR_MPM_DCACHE_DREQ_ST, CSR_MPM_DCACHE_DREQ_ST_H, &dcache_dram_st_per_core);
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if (num_cores > 1) fprintf(stream, "PERF: core%d: dcache dram stalls=%ld\n", core_id, dcache_dram_st_per_core);
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dcache_dram_stalls += dcache_dram_st_per_core;
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// mshr_stalls
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uint64_t dcache_mshr_st_per_core;
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ret |= vx_csr_get_l(device, core_id, CSR_MPM_DCACHE_MSHR_ST, CSR_MPM_DCACHE_MSHR_ST_H, &dcache_mshr_st_per_core);
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if (num_cores > 1) fprintf(stream, "PERF: core%d: dcache mshr stalls=%ld\n", core_id, dcache_mshr_st_per_core);
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dcache_mshr_stalls += dcache_mshr_st_per_core;
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// PERF: dram_latency
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uint64_t dram_req_per_core, dram_rsp_per_core, dram_lat_per_core;
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ret |= vx_csr_get_l(device, core_id, CSR_MPM_DRAM_REQ, CSR_MPM_DRAM_REQ_H, &dram_req_per_core);
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ret |= vx_csr_get_l(device, core_id, CSR_MPM_DRAM_RSP, CSR_MPM_DRAM_RSP_H, &dram_rsp_per_core);
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ret |= vx_csr_get_l(device, core_id, CSR_MPM_DRAM_LAT, CSR_MPM_DRAM_LAT_H, &dram_lat_per_core);
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int avg_dram_lat_per_core = (int)(double(dram_lat_per_core) / double(dram_rsp_per_core));
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if (num_cores > 1) fprintf(stream, "PERF: core%d: dram requests=%ld (reads=%ld, writes=%ld)\n", core_id, dram_req_per_core, dram_rsp_per_core, dram_req_per_core - dram_rsp_per_core);
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if (num_cores > 1) fprintf(stream, "PERF: core%d: average dram latency=%d cycles\n", core_id, avg_dram_lat_per_core);
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dram_req += dram_req_per_core;
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dram_rsp += dram_rsp_per_core;
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dram_lat += dram_lat_per_core;
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#endif
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}
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float IPC = (float)(double(instrs) / double(cycles));
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fprintf(stream, "PERF: instrs=%ld, cycles=%ld, IPC=%f\n", instrs, cycles, IPC);
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#ifdef PERF_ENABLE
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fprintf(stream, "PERF: icache stalls=%ld\n", icache_stalls);
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fprintf(stream, "PERF: ibuffer stalls=%ld\n", ibuffer_stalls);
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fprintf(stream, "PERF: scoreboard stalls=%ld\n", scoreboard_stalls);
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fprintf(stream, "PERF: alu stalls=%ld\n", alu_stalls);
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fprintf(stream, "PERF: lsu stalls=%ld\n", lsu_stalls);
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fprintf(stream, "PERF: csr stalls=%ld\n", csr_stalls);
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fprintf(stream, "PERF: mul stalls=%ld\n", mul_stalls);
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fprintf(stream, "PERF: fpu stalls=%ld\n", fpu_stalls);
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fprintf(stream, "PERF: gpu stalls=%ld\n", gpu_stalls);
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fprintf(stream, "PERF: icache reads=%ld\n", icache_reads);
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fprintf(stream, "PERF: icache read misses=%ld\n", icache_read_misses);
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fprintf(stream, "PERF: icache reponse stalls=%ld\n", icache_rsp_stalls);
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fprintf(stream, "PERF: icache pipeline stalls=%ld\n", icache_pipe_stalls);
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fprintf(stream, "PERF: icache dram stalls=%ld\n", icache_dram_stalls);
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fprintf(stream, "PERF: icache mshr stalls=%ld\n", icache_mshr_stalls);
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fprintf(stream, "PERF: dcache reads=%ld\n", dcache_reads);
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fprintf(stream, "PERF: dcache writes=%ld\n", dcache_writes);
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fprintf(stream, "PERF: dcache read misses=%ld\n", dcache_read_misses);
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fprintf(stream, "PERF: dcache wrire misses=%ld\n", dcache_write_misses);
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fprintf(stream, "PERF: dcache evictions=%ld\n", dcache_evictions);
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fprintf(stream, "PERF: dcache pipeline stalls=%ld\n", dcache_pipe_stalls);
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fprintf(stream, "PERF: dcache reponse stalls=%ld\n", dcache_rsp_stalls);
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fprintf(stream, "PERF: dcache dram stalls=%ld\n", dcache_dram_stalls);
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fprintf(stream, "PERF: dcache mshr stalls=%ld\n", dcache_mshr_stalls);
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fprintf(stream, "PERF: dram requests=%ld (reads=%ld, writes=%ld)\n", dram_req, dram_rsp, dram_req - dram_rsp);
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int avg_dram_lat = (int)(double(dram_lat) / double(dram_rsp));
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fprintf(stream, "PERF: average dram latency=%d cycles\n", avg_dram_lat);
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#endif
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return ret;
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}
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