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afu mem controller refactoring

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Blaise Tine
2021-05-01 08:39:52 -07:00
parent 269c06f7ea
commit d504adb236
9 changed files with 235 additions and 199 deletions
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8
hw/syn/opae/Makefile
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@@ -3,14 +3,6 @@ FPGA_BUILD_DIR ?= build_fpga
DEVICE_FAMILY ?= arria10
RTL_DIR=../../rtl
ifeq ($(DEVICE_FAMILY),arria10)
CFLAGS += -DMEM_BLOCK_SIZE=64
endif
ifeq ($(DEVICE_FAMILY),stratix10)
CFLAGS += -DMEM_BLOCK_SIZE=16
endif
ifeq ($(shell which qsub-synth),)
RUN_SYNTH=$(OPAE_PLATFORM_ROOT)/bin/run.sh > build.log 2>&1 &
else