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cache refactoring

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This commit is contained in:
Blaise Tine
2021-01-17 00:18:56 -08:00
parent 5b80484123
commit d4e7b28be8
12 changed files with 189 additions and 332 deletions
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45
hw/rtl/libs/VX_dp_ram.v
View File

@@ -9,7 +9,8 @@ module VX_dp_ram #(
parameter RWCHECK = 1,
parameter ADDRW = $clog2(SIZE),
parameter SIZEW = $clog2(SIZE+1),
parameter FASTRAM = 0
parameter FASTRAM = 0,
parameter INITZERO = 0
) (
input wire clk,
input wire [ADDRW-1:0] waddr,
@@ -30,6 +31,10 @@ module VX_dp_ram #(
if (BYTEENW > 1) begin
`USE_FAST_BRAM reg [BYTEENW-1:0][7:0] mem [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
end
always @(posedge clk) begin
if (wren) begin
for (integer i = 0; i < BYTEENW; i++) begin
@@ -43,6 +48,10 @@ module VX_dp_ram #(
end else begin
`USE_FAST_BRAM reg [DATAW-1:0] mem [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
end
always @(posedge clk) begin
if (wren && byteen)
mem[waddr] <= din;
@@ -57,6 +66,10 @@ module VX_dp_ram #(
if (BYTEENW > 1) begin
`USE_FAST_BRAM reg [BYTEENW-1:0][7:0] mem [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
end
always @(posedge clk) begin
if (wren) begin
for (integer i = 0; i < BYTEENW; i++) begin
@@ -69,6 +82,10 @@ module VX_dp_ram #(
end else begin
`USE_FAST_BRAM reg [DATAW-1:0] mem [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
end
always @(posedge clk) begin
if (wren && byteen)
mem[waddr] <= din;
@@ -83,6 +100,10 @@ module VX_dp_ram #(
if (BYTEENW > 1) begin
reg [BYTEENW-1:0][7:0] mem [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
end
always @(posedge clk) begin
if (wren) begin
for (integer i = 0; i < BYTEENW; i++) begin
@@ -96,6 +117,10 @@ module VX_dp_ram #(
end else begin
reg [DATAW-1:0] mem [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
end
always @(posedge clk) begin
if (wren && byteen)
mem[waddr] <= din;
@@ -111,6 +136,10 @@ module VX_dp_ram #(
if (BYTEENW > 1) begin
reg [BYTEENW-1:0][7:0] mem [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
end
always @(posedge clk) begin
if (wren) begin
for (integer i = 0; i < BYTEENW; i++) begin
@@ -123,6 +152,10 @@ module VX_dp_ram #(
end else begin
reg [DATAW-1:0] mem [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
end
always @(posedge clk) begin
if (wren && byteen)
mem[waddr] <= din;
@@ -133,6 +166,10 @@ module VX_dp_ram #(
if (BYTEENW > 1) begin
`NO_RW_RAM_CHECK reg [BYTEENW-1:0][7:0] mem [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
end
always @(posedge clk) begin
if (wren) begin
for (integer i = 0; i < BYTEENW; i++) begin
@@ -143,7 +180,11 @@ module VX_dp_ram #(
end
assign dout = mem[raddr];
end else begin
`NO_RW_RAM_CHECK reg [DATAW-1:0] mem [SIZE-1:0];
`NO_RW_RAM_CHECK reg [DATAW-1:0] mem [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
end
always @(posedge clk) begin
if (wren && byteen)

45
hw/rtl/libs/VX_sp_ram.v
View File

@@ -9,7 +9,8 @@ module VX_sp_ram #(
parameter RWCHECK = 1,
parameter ADDRW = $clog2(SIZE),
parameter SIZEW = $clog2(SIZE+1),
parameter FASTRAM = 0
parameter FASTRAM = 0,
parameter INITZERO = 0
) (
input wire clk,
input wire [ADDRW-1:0] addr,
@@ -29,6 +30,10 @@ module VX_sp_ram #(
if (BYTEENW > 1) begin
`USE_FAST_BRAM reg [BYTEENW-1:0][7:0] mem [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
end
always @(posedge clk) begin
if (wren) begin
for (integer i = 0; i < BYTEENW; i++) begin
@@ -42,6 +47,10 @@ module VX_sp_ram #(
end else begin
`USE_FAST_BRAM reg [DATAW-1:0] mem [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
end
always @(posedge clk) begin
if (wren && byteen)
mem[addr] <= din;
@@ -55,6 +64,10 @@ module VX_sp_ram #(
if (BYTEENW > 1) begin
`USE_FAST_BRAM reg [BYTEENW-1:0][7:0] mem [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
end
always @(posedge clk) begin
if (wren) begin
for (integer i = 0; i < BYTEENW; i++) begin
@@ -67,6 +80,10 @@ module VX_sp_ram #(
end else begin
`USE_FAST_BRAM reg [DATAW-1:0] mem [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
end
always @(posedge clk) begin
if (wren && byteen)
mem[addr] <= din;
@@ -81,6 +98,10 @@ module VX_sp_ram #(
if (BYTEENW > 1) begin
reg [BYTEENW-1:0][7:0] mem [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
end
always @(posedge clk) begin
if (wren) begin
for (integer i = 0; i < BYTEENW; i++) begin
@@ -94,6 +115,10 @@ module VX_sp_ram #(
end else begin
reg [DATAW-1:0] mem [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
end
always @(posedge clk) begin
if (wren && byteen)
mem[addr] <= din;
@@ -108,6 +133,10 @@ module VX_sp_ram #(
if (BYTEENW > 1) begin
reg [BYTEENW-1:0][7:0] mem [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
end
always @(posedge clk) begin
if (wren) begin
for (integer i = 0; i < BYTEENW; i++) begin
@@ -120,6 +149,10 @@ module VX_sp_ram #(
end else begin
reg [DATAW-1:0] mem [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
end
always @(posedge clk) begin
if (wren && byteen)
mem[addr] <= din;
@@ -130,6 +163,10 @@ module VX_sp_ram #(
if (BYTEENW > 1) begin
`NO_RW_RAM_CHECK reg [BYTEENW-1:0][7:0] mem [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
end
always @(posedge clk) begin
if (wren) begin
for (integer i = 0; i < BYTEENW; i++) begin
@@ -140,7 +177,11 @@ module VX_sp_ram #(
end
assign dout = mem[addr];
end else begin
`NO_RW_RAM_CHECK reg [DATAW-1:0] mem [SIZE-1:0];
`NO_RW_RAM_CHECK reg [DATAW-1:0] mem [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
end
always @(posedge clk) begin
if (wren && byteen)