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cache refactoring

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This commit is contained in:
Blaise Tine
2021-01-17 00:18:56 -08:00
parent 5b80484123
commit d4e7b28be8
12 changed files with 189 additions and 332 deletions
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12
hw/rtl/VX_config.vh
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@@ -264,7 +264,7 @@
// Size of cache in bytes
`ifndef ICACHE_SIZE
`define ICACHE_SIZE 8192
`define ICACHE_SIZE 16384
`endif
// Core Request Queue Size
@@ -296,7 +296,7 @@
// Size of cache in bytes
`ifndef DCACHE_SIZE
`define DCACHE_SIZE 8192
`define DCACHE_SIZE 16384
`endif
// Number of banks
@@ -360,7 +360,7 @@
// Size of cache in bytes
`ifndef L2CACHE_SIZE
`define L2CACHE_SIZE 131072
`define L2CACHE_SIZE 262144
`endif
// Number of banks
@@ -380,7 +380,7 @@
// Miss Handling Register Size
`ifndef L2MSHR_SIZE
`define L2MSHR_SIZE 8
`define L2MSHR_SIZE 16
`endif
// DRAM Request Queue Size
@@ -397,7 +397,7 @@
// Size of cache in bytes
`ifndef L3CACHE_SIZE
`define L3CACHE_SIZE 262144
`define L3CACHE_SIZE 1048576
`endif
// Number of banks
@@ -417,7 +417,7 @@
// Miss Handling Register Size
`ifndef L3MSHR_SIZE
`define L3MSHR_SIZE 8
`define L3MSHR_SIZE 16
`endif
// DRAM Request Queue Size