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fixed renaem table reset logic

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Blaise Tine
2020-05-20 18:24:09 -04:00
parent 72d54c749c
commit d4cb8b6f66
1 changed files with 1 additions and 7 deletions
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8
hw/rtl/VX_scheduler.v
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@@ -48,15 +48,9 @@ module VX_scheduler (
|| (gpr_stage_delay && (is_mem || is_exec)) || (gpr_stage_delay && (is_mem || is_exec))
|| (exec_delay && is_exec)); || (exec_delay && is_exec));
integer i, w;
always @(posedge clk) begin always @(posedge clk) begin
if (reset) begin if (reset) begin
for (w = 0; w < `NUM_WARPS; w=w+1) begin //--
for (i = 0; i < 32; i++) begin
rename_table[w][i] <= 0;
end
end
end else begin end else begin
if (valid_wb) begin if (valid_wb) begin
rename_table[writeback_if.warp_num][writeback_if.rd] <= rename_table[writeback_if.warp_num][writeback_if.rd] & (~writeback_if.valid); rename_table[writeback_if.warp_num][writeback_if.rd] <= rename_table[writeback_if.warp_num][writeback_if.rd] & (~writeback_if.valid);