Vortex 2.0 changes:

+ Microarchitecture optimizations
+ 64-bit support
+ Xilinx FPGA support
+ LLVM-16 support
+ Refactoring and quality control fixes

sim/simx/instr.h

@@ -1,3 +1,16 @@
+// Copyright © 2019-2023
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+// http://www.apache.org/licenses/LICENSE-2.0
+// 
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
 #pragma once
 
 #include "types.h"
@@ -7,7 +20,7 @@ namespace vortex {
 class Warp;
 
 enum Opcode {   
-  NOP       = 0,    
+  NONE      = 0,    
   R_INST    = 0x33,
   L_INST    = 0x3,
   I_INST    = 0x13,
@@ -19,6 +32,7 @@ enum Opcode {
   JALR_INST = 0x67,
   SYS_INST  = 0x73,
   FENCE     = 0x0f,
+  AMO       = 0x2f,
   // F Extension
   FL        = 0x7,
   FS        = 0x27,
@@ -26,19 +40,20 @@ enum Opcode {
   FMADD     = 0x43,
   FMSUB     = 0x47,
   FMNMSUB   = 0x4b,
-  FMNMADD   = 0x4f,
-  // Vector Extension  
-  VSET      = 0x57,
-  // GPGPU Extension
-  GPGPU     = 0x6b,
-  GPU       = 0x5b,
-  // RV64 Standard Extensions
+  FMNMADD   = 0x4f,  
+  // RV64 Standard Extension
   R_INST_W  = 0x3b,
   I_INST_W  = 0x1b,
+  // Vector Extension  
+  VSET      = 0x57,
+  // Custom Extensions
+  EXT1      = 0x0b,
+  EXT2      = 0x2b,
+  EXT3      = 0x5b,
+  EXT4      = 0x7b
 };
 
-enum InstType { 
-  N_TYPE, 
+enum InstType {
   R_TYPE, 
   I_TYPE, 
   S_TYPE, 
@@ -52,25 +67,45 @@ enum InstType {
 class Instr {
 public:
   Instr() 
-    : opcode_(Opcode::NOP)
+    : opcode_(Opcode::NONE)
     , num_rsrcs_(0)
     , has_imm_(false)
     , rdest_type_(RegType::None)
+    , imm_(0)
     , rdest_(0)
     , func2_(0)
     , func3_(0)
     , func6_(0)
-    , func7_(0) {
+    , func7_(0)
+    , vmask_(0)
+    , vlsWidth_(0)
+    , vMop_(0)
+    , vNf_(0)
+    , vs3_(0)
+    , vlmul_(0)
+    , vsew_(0)
+    , vediv_(0)   {
     for (uint32_t i = 0; i < MAX_REG_SOURCES; ++i) {
        rsrc_type_[i] = RegType::None;
+       rsrc_[i] = 0;
     }
   }
 
   void setOpcode(Opcode opcode)  { opcode_ = opcode; }
-  void setDestReg(uint32_t destReg, RegType type) { rdest_type_ = type; rdest_ = destReg; }
-  void setSrcReg(uint32_t srcReg, RegType type) { rsrc_type_[num_rsrcs_] = type; rsrc_[num_rsrcs_++] = srcReg; }
-  void setDestVReg(uint32_t destReg) { rdest_type_ = RegType::Vector; rdest_ = destReg; }
-  void setSrcVReg(uint32_t srcReg) { rsrc_type_[num_rsrcs_] = RegType::Vector; rsrc_[num_rsrcs_++] = srcReg;  }
+  void setDestReg(uint32_t destReg, RegType type) { 
+    rdest_type_ = type; 
+    rdest_ = destReg; 
+  }
+  void addSrcReg(uint32_t srcReg, RegType type) { 
+    rsrc_type_[num_rsrcs_] = type; 
+    rsrc_[num_rsrcs_] = srcReg; 
+    ++num_rsrcs_;
+  }
+  void setSrcReg(uint32_t index, uint32_t srcReg, RegType type) { 
+    rsrc_type_[index] = type; 
+    rsrc_[index] = srcReg; 
+    num_rsrcs_ = std::max<uint32_t>(num_rsrcs_, index+1); 
+  }
   void setFunc2(uint32_t func2) { func2_ = func2; }
   void setFunc3(uint32_t func3) { func3_ = func3; }
   void setFunc7(uint32_t func7) { func7_ = func7; }
@@ -85,17 +120,17 @@ public:
   void setVediv(uint32_t ediv) { vediv_ = 1 << ediv; }
   void setFunc6(uint32_t func6) { func6_ = func6; }
 
-  Opcode getOpcode() const { return opcode_; }
+  Opcode   getOpcode() const { return opcode_; }
   uint32_t getFunc2() const { return func2_; }
   uint32_t getFunc3() const { return func3_; }
   uint32_t getFunc6() const { return func6_; }
   uint32_t getFunc7() const { return func7_; }
   uint32_t getNRSrc() const { return num_rsrcs_; }
   uint32_t getRSrc(uint32_t i) const { return rsrc_[i]; }
-  RegType getRSType(uint32_t i) const { return rsrc_type_[i]; }
+  RegType  getRSType(uint32_t i) const { return rsrc_type_[i]; }
   uint32_t getRDest() const { return rdest_; }  
-  RegType getRDType() const { return rdest_type_; }  
-  bool hasImm() const { return has_imm_; }
+  RegType  getRDType() const { return rdest_type_; }  
+  bool     hasImm() const { return has_imm_; }
   uint32_t getImm() const { return imm_; }
   uint32_t getVlsWidth() const { return vlsWidth_; }
   uint32_t getVmop() const { return vMop_; }