Vortex 2.0 changes:
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
This commit is contained in:
Blaise Tine
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sim/simx/cluster.cpp
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222
sim/simx/cluster.cpp
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// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "cluster.h"
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using namespace vortex;
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Cluster::Cluster(const SimContext& ctx,
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uint32_t cluster_id,
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ProcessorImpl* processor,
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const Arch &arch, const
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DCRS &dcrs)
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: SimObject(ctx, "cluster")
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, mem_req_port(this)
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, mem_rsp_port(this)
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, cluster_id_(cluster_id)
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, cores_(arch.num_cores())
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, barriers_(arch.num_barriers(), 0)
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, sharedmems_(arch.num_cores())
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, processor_(processor)
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{
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auto num_cores = arch.num_cores();
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char sname[100];
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snprintf(sname, 100, "cluster%d-l2cache", cluster_id);
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l2cache_ = CacheSim::Create(sname, CacheSim::Config{
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!L2_ENABLED,
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log2ceil(L2_CACHE_SIZE), // C
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log2ceil(MEM_BLOCK_SIZE), // B
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log2ceil(L2_NUM_WAYS), // W
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0, // A
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XLEN, // address bits
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L2_NUM_BANKS, // number of banks
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1, // number of ports
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5, // request size
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true, // write-through
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false, // write response
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0, // victim size
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L2_MSHR_SIZE, // mshr
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2, // pipeline latency
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});
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l2cache_->MemReqPort.bind(&this->mem_req_port);
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this->mem_rsp_port.bind(&l2cache_->MemRspPort);
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snprintf(sname, 100, "cluster%d-icaches", cluster_id);
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icaches_ = CacheCluster::Create(sname, num_cores, NUM_ICACHES, 1, CacheSim::Config{
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!ICACHE_ENABLED,
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log2ceil(ICACHE_SIZE), // C
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log2ceil(L1_LINE_SIZE), // B
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log2ceil(sizeof(uint32_t)), // W
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log2ceil(ICACHE_NUM_WAYS),// A
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XLEN, // address bits
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1, // number of banks
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1, // number of ports
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1, // number of inputs
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true, // write-through
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false, // write response
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0, // victim size
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(uint8_t)arch.num_warps(), // mshr
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2, // pipeline latency
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});
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icaches_->MemReqPort.bind(&l2cache_->CoreReqPorts.at(0));
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l2cache_->CoreRspPorts.at(0).bind(&icaches_->MemRspPort);
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snprintf(sname, 100, "cluster%d-dcaches", cluster_id);
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dcaches_ = CacheCluster::Create(sname, num_cores, NUM_DCACHES, NUM_LSU_LANES, CacheSim::Config{
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!DCACHE_ENABLED,
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log2ceil(DCACHE_SIZE), // C
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log2ceil(L1_LINE_SIZE), // B
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log2ceil(sizeof(Word)), // W
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log2ceil(DCACHE_NUM_WAYS),// A
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XLEN, // address bits
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DCACHE_NUM_BANKS, // number of banks
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1, // number of ports
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DCACHE_NUM_BANKS, // number of inputs
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true, // write-through
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false, // write response
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0, // victim size
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DCACHE_MSHR_SIZE, // mshr
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4, // pipeline latency
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});
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dcaches_->MemReqPort.bind(&l2cache_->CoreReqPorts.at(1));
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l2cache_->CoreRspPorts.at(1).bind(&dcaches_->MemRspPort);
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///////////////////////////////////////////////////////////////////////////
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// create shared memory blocks
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for (uint32_t i = 0; i < num_cores; ++i) {
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snprintf(sname, 100, "cluster%d-shared_mem%d", cluster_id, i);
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sharedmems_.at(i) = SharedMem::Create(sname, SharedMem::Config{
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(1 << SMEM_LOG_SIZE),
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sizeof(Word),
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NUM_LSU_LANES,
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NUM_LSU_LANES,
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false
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});
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}
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// create cores
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for (uint32_t i = 0; i < num_cores; ++i) {
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uint32_t core_id = cluster_id * num_cores + i;
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cores_.at(i) = Core::Create(core_id,
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this,
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arch,
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dcrs,
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sharedmems_.at(i));
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cores_.at(i)->icache_req_ports.at(0).bind(&icaches_->CoreReqPorts.at(i).at(0));
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icaches_->CoreRspPorts.at(i).at(0).bind(&cores_.at(i)->icache_rsp_ports.at(0));
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for (uint32_t j = 0; j < NUM_LSU_LANES; ++j) {
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snprintf(sname, 100, "cluster%d-smem_demux%d_%d", cluster_id, i, j);
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auto smem_demux = SMemDemux::Create(sname);
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cores_.at(i)->dcache_req_ports.at(j).bind(&smem_demux->ReqIn);
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smem_demux->RspIn.bind(&cores_.at(i)->dcache_rsp_ports.at(j));
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smem_demux->ReqDc.bind(&dcaches_->CoreReqPorts.at(i).at(j));
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dcaches_->CoreRspPorts.at(i).at(j).bind(&smem_demux->RspDc);
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smem_demux->ReqSm.bind(&sharedmems_.at(i)->Inputs.at(j));
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sharedmems_.at(i)->Outputs.at(j).bind(&smem_demux->RspSm);
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}
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}
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}
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Cluster::~Cluster() {
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//--
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}
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void Cluster::reset() {
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for (auto& barrier : barriers_) {
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barrier.reset();
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}
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}
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void Cluster::tick() {
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//--
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}
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void Cluster::attach_ram(RAM* ram) {
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for (auto core : cores_) {
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core->attach_ram(ram);
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}
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}
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bool Cluster::running() const {
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for (auto& core : cores_) {
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if (core->running())
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return true;
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}
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return false;
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}
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bool Cluster::check_exit(Word* exitcode, bool riscv_test) const {
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bool done = true;
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Word exitcode_ = 0;
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for (auto& core : cores_) {
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Word ec;
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if (core->check_exit(&ec, riscv_test)) {
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exitcode_ |= ec;
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} else {
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done = false;
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}
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}
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*exitcode = exitcode_;
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return done;
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}
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void Cluster::barrier(uint32_t bar_id, uint32_t count, uint32_t core_id) {
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auto& barrier = barriers_.at(bar_id);
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uint32_t local_core_id = core_id % cores_.size();
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barrier.set(local_core_id);
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DP(3, "*** Suspend core #" << core_id << " at barrier #" << bar_id);
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if (barrier.count() == (size_t)count) {
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// resume all suspended cores
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for (uint32_t i = 0; i < cores_.size(); ++i) {
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if (barrier.test(i)) {
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DP(3, "*** Resume core #" << i << " at barrier #" << bar_id);
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cores_.at(i)->resume();
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}
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}
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barrier.reset();
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}
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}
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ProcessorImpl* Cluster::processor() const {
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return processor_;
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}
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Cluster::PerfStats Cluster::perf_stats() const {
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Cluster::PerfStats perf;
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perf.icache = icaches_->perf_stats();
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perf.dcache = dcaches_->perf_stats();
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perf.tcache = tcaches_->perf_stats();
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perf.ocache = ocaches_->perf_stats();
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perf.rcache = rcaches_->perf_stats();
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perf.l2cache = l2cache_->perf_stats();
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for (auto sharedmem : sharedmems_) {
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perf.sharedmem += sharedmem->perf_stats();
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}
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return perf;
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}
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