Vortex 2.0 changes:
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
This commit is contained in:
Blaise Tine
1
hw/syn/yosys/.gitignore
vendored
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1
hw/syn/yosys/.gitignore
vendored
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@@ -0,0 +1 @@
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build_*/*
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@@ -1,20 +1,99 @@
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PROJECT = Vortex
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TOP_LEVEL_ENTITY = Vortex
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SRC_FILE = Vortex.sv
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RTL_DIR = ../../rtl
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TOP_LEVEL_ENTITY ?= Vortex
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PREFIX ?= build
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NUM_CORES ?= 1
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XLEN ?= 32
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DEFINES = -DNDEBUG -DSYNTHESIS -DEXT_F_DISABLE -DNUM_CORES=1 -DNUM_THREADS=2 -DNUM_WARPS=2 -DMEM_BLOCK_SIZE=64
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SCRIPT_DIR = ../../../scripts
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RTL_DIR = ../../../rtl
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DPI_DIR = ../../../dpi
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THIRD_PARTY_DIR = ../../../../third_party
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RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache
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CP = cp -rf
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RMDIR = rm -rf
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ECHO = @echo
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BUILD_DIR = $(PREFIX)_$(TOP_LEVEL_ENTITY)
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BIN_DIR = $(BUILD_DIR)/bin
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# control RTL debug tracing states
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DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_PIPELINE
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DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_ICACHE
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DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_DCACHE
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DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_MEM
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DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_BANK
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DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_MSHR
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DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_TAG
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DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_DATA
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DBG_TRACE_FLAGS += -DDBG_TRACE_AFU
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DBG_TRACE_FLAGS += -DDBG_TRACE_TEX
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DBG_TRACE_FLAGS += -DDBG_TRACE_RASTER
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DBG_TRACE_FLAGS += -DDBG_TRACE_ROP
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DBG_TRACE_FLAGS += -DDBG_TRACE_GBAR
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# Control logic analyzer monitors
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DBG_SCOPE_FLAGS += -DDBG_SCOPE_AFU
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DBG_SCOPE_FLAGS += -DDBG_SCOPE_ISSUE
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DBG_SCOPE_FLAGS += -DDBG_SCOPE_FETCH
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DBG_SCOPE_FLAGS += -DDBG_SCOPE_LSU
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DBG_SCOPE_FLAGS += -DDBG_SCOPE_RASTER
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DBG_SCOPE_FLAGS += -DDBG_SCOPE_MSCHED
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# cluster configuration
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CONFIGS_1c := -DNUM_CLUSTERS=1 -DNUM_CORES=1
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CONFIGS_2c := -DNUM_CLUSTERS=1 -DNUM_CORES=2
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CONFIGS_4c := -DNUM_CLUSTERS=1 -DNUM_CORES=4 -DL2_ENABLE
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CONFIGS_8c := -DNUM_CLUSTERS=1 -DNUM_CORES=8 -DL2_ENABLE
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CONFIGS_16c := -DNUM_CLUSTERS=1 -DNUM_CORES=16 -DL2_ENABLE
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CONFIGS_32c := -DNUM_CLUSTERS=2 -DNUM_CORES=16 -DL2_ENABLE
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CONFIGS_64c := -DNUM_CLUSTERS=4 -DNUM_CORES=16 -DL2_ENABLE
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CONFIGS += $(CONFIGS_$(NUM_CORES)c)
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# include paths
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FPU_INCLUDE = -I$(RTL_DIR)/fpu
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ifneq (,$(findstring FPU_FPNEW,$(CONFIGS)))
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FPU_INCLUDE += -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -J$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/fpnew/src
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endif
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RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache
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RTL_INCLUDE += $(FPU_INCLUDE)
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# Debugigng
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ifdef DEBUG
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CFLAGS += -DNDEBUG -DSCOPE $(DBG_SCOPE_FLAGS)
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SCOPE_JSON += $(BUILD_DIR)/scope.json
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else
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CFLAGS += -DNDEBUG
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endif
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# Enable scope analyzer
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ifdef SCOPE
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CFLAGS += -DSCOPE
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endif
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# Enable perf counters
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ifdef PERF
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CFLAGS += -DPERF_ENABLE
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endif
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CFLAGS += -DSYNTHESIS -DYOSYS
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CFLAGS += -DXLEN_$(XLEN)
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CFLAGS += $(CONFIGS)
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CFLAGS += $(RTL_INCLUDE)
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# Build targets
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all: build
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all: clean build
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output.v:
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./sv2v.sh $(DEFINES) $(RTL_INCLUDE) -ooutput.v
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gen-sources: $(BUILD_DIR)/sources.txt
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$(BUILD_DIR)/sources.txt:
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mkdir -p $(BUILD_DIR); cd $(BUILD_DIR); $(SCRIPT_DIR)/gen_sources.sh -P $(CFLAGS) -Csrc -Osources.txt
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build: output.v
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./synth.sh -t$(TOP_LEVEL_ENTITY) -soutput.v
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$(BUILD_DIR)/project.v: gen-sources
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cd $(BUILD_DIR); $(SCRIPT_DIR)/sv2v.sh -t$(TOP_LEVEL_ENTITY) -Isrc -oproject.v
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build: $(BUILD_DIR)/project.v
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cd $(BUILD_DIR); ../synth.sh -t$(TOP_LEVEL_ENTITY) -sproject.v
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elaborate: $(BUILD_DIR)/project.v
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cd $(BUILD_DIR); ../synth.sh -t$(TOP_LEVEL_ENTITY) -sproject.v -P="elaborate"
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clean:
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rm -rf output.v *.ys *.log
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$(RMDIR) $(BUILD_DIR)
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@@ -1,57 +0,0 @@
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#!/bin/bash
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# this script uses sv2v and yosys tools to run.
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# sv2v: https://github.com/zachjs/sv2v
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# yosys: http://www.clifford.at/yosys/
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# exit when any command fails
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set -e
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source=""
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includes=()
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macro_args=""
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output_file=out.v
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usage() { echo "$0 usage:" && grep " .)\ #" $0; exit 0; }
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[ $# -eq 0 ] && usage
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while getopts "o:I:D:h" arg; do
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case $arg in
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s) # source
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source=${OPTARG}
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;;
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o) # output-file
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output_file=${OPTARG}
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;;
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I) # include directory
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includes+=(${OPTARG})
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;;
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D) # macro definition
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macro_args="$macro_args -D${OPTARG}"
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;;
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h | *)
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usage
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exit 0
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;;
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esac
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done
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# process include paths
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inc_args=""
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for dir in "${includes[@]}"
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do
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inc_args="$inc_args -I$dir"
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done
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# process source files
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file_args=$source
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for dir in "${includes[@]}"
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do
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for file in $(find $dir -maxdepth 1 -name '*.v' -o -name '*.sv' -type f)
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do
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echo "file: $file"
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file_args="$file_args $file"
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done
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done
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# system-verilog to verilog conversion
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sv2v $macro_args $inc_args $file_args -v -w $output_file
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@@ -1,5 +1,18 @@
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#!/bin/bash
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# Copyright © 2019-2023
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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# this script uses sv2v and yosys tools to run.
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# sv2v: https://github.com/zachjs/sv2v
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# yosys: http://www.clifford.at/yosys/
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@@ -12,10 +25,48 @@ top_level=""
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dir_list=()
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inc_args=""
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macro_args=""
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no_warnings=1
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process="elaborate,netlist,techmap,verilog"
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declare -a excluded_warnings=("Resizing cell port")
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is_excluded_warning() {
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local warning_text="$1"
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for exclusion in "${excluded_warnings[@]}"; do
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if [[ "$warning_text" == *"$exclusion"* ]]; then
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return $no_warnings
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fi
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done
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return 1
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}
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checkErrors()
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{
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log_file="$1"
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if grep -q "Error: " "$log_file"; then
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echo "Error: found errors during synthesis!"
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exit 1
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fi
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count=0
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while IFS= read -r line; do
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if [[ "$line" == *"Warning:"* ]]; then
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warning_text="${line#Warning: }"
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if ! is_excluded_warning "$warning_text"; then
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count=$(expr $count + 1)
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fi
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fi
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done < $log_file
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if [ "$count" -ne 0 ]; then
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echo "Error: found $count unexpected warnings during synthesis!"
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exit $count
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fi
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}
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usage() { echo "$0 usage:" && grep " .)\ #" $0; exit 0; }
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[ $# -eq 0 ] && usage
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while getopts "s:t:I:D:h" arg; do
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while getopts "s:t:I:D:P:Wh" arg; do
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case $arg in
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s) # source
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source=${OPTARG}
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@@ -30,6 +81,12 @@ while getopts "s:t:I:D:h" arg; do
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D) # macro definition
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macro_args="$macro_args -D${OPTARG}"
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;;
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P) # process
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process=${OPTARG}
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;;
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W) # allow warnings
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no_warnings=0
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;;
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h | *)
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usage
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exit 0
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@@ -43,23 +100,34 @@ done
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do
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for file in $(find $dir -maxdepth 1 -name '*.v' -o -name '*.sv' -type f)
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do
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echo "read_verilog $macro_args $inc_args -sv $file"
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echo "read_verilog -defer -nolatches $macro_args $inc_args -sv $file"
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done
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done
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if [ -n "$source" ]; then
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echo "read_verilog $macro_args $inc_args -sv $source"
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echo "read_verilog -defer -nolatches $macro_args $inc_args -sv $source"
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fi
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# generic synthesis
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echo "synth -top $top_level"
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# elaborate
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if echo "$process" | grep -q "elaborate"; then
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echo "hierarchy -top $top_level"
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fi
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# convert to netlist
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if echo "$process" | grep -q "netlist"; then
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echo "proc; opt"
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fi
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# mapping to mycells.lib
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echo "dfflibmap -liberty mycells.lib"
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echo "abc -liberty mycells.lib"
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echo "clean"
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# convert to gate logic
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if echo "$process" | grep -q "techmap"; then
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echo "techmap; opt"
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fi
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# write synthesized design
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echo "write_verilog synth.v"
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if echo "$process" | grep -q "verilog"; then
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echo "write_verilog synth.v"
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fi
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} > synth.ys
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yosys -l yosys.log synth.ys
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yosys -l yosys.log synth.ys
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checkErrors yosys.log
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