Vortex 2.0 changes:

+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
2023-10-19 20:51:22 -07:00
parent d69a64c32c
commit d47cccc157
1300 changed files with 247321 additions and 311189 deletions
--- a/hw/syn/xilinx/NOTEBOOK
+++ b/hw/syn/xilinx/NOTEBOOK
@@ -0,0 +1,73 @@
+## Xilinx synthesis Notebook
+
+# check installed FPGAs
+platforminfo -l
+
+# check FPGA status
+xbutil validate --device 0000:09:00.1 --verbose
+
+# generate FPU IPs
+vivado -mode batch -source scripts/gen_ip.tcl -tclargs ip/xilinx_u50_gen3x16_xdma_5_202210_1
+
+# build FPGA
+PREFIX=build_base_1c NUM_CORES=1 TARGET=hw_emu PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 make > build_u50_hw_emu_base_1c.log 2>&1 &
+PREFIX=build_base_1c NUM_CORES=1 TARGET=hw PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 make > build_u50_hw_base_1c.log 2>&1 &
+
+PREFIX=build_gfx_1c NUM_CORES=1 TARGET=hw_emu PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 CONFIGS="-DEXT_GFX_ENABLE" make > build_u50_hw_emu_gfx_1c.log 2>&1 &
+PREFIX=build_gfx_1c NUM_CORES=1 TARGET=hw PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 CONFIGS="-DEXT_GFX_ENABLE" make > build_u50_hw_gfx_1c.log 2>&1 &
+
+PREFIX=build_gfx_dbg_1c DEBUG=3 NUM_CORES=1 TARGET=hw_emu PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 CONFIGS="-DEXT_GFX_ENABLE" make > build_u50_hw_emu_gfx_dbg_1c.log 2>&1 &
+PREFIX=build_gfx_dbg_1c DEBUG=3 NUM_CORES=1 TARGET=hw PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 CONFIGS="-DEXT_GFX_ENABLE" make > build_u50_hw_gfx_dbg_1c.log 2>&1 &
+
+PREFIX=build_base_2c NUM_CORES=2 TARGET=hw_emu PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 make > build_u50_hw_emu_base_2c.log 2>&1 &
+PREFIX=build_base_2c NUM_CORES=2 TARGET=hw PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 make > build_u50_hw_base_2c.log 2>&1 &
+
+PREFIX=build_gfx_2c NUM_CORES=2 TARGET=hw_emu PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 CONFIGS="-DEXT_GFX_ENABLE" make > build_u50_hw_emu_gfx_2c.log 2>&1 &
+PREFIX=build_gfx_2c NUM_CORES=2 TARGET=hw PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 CONFIGS="-DEXT_GFX_ENABLE" make > build_u50_hw_gfx_2c.log 2>&1 &
+
+PREFIX=build_gfx_dbg_1c DEBUG=3 NUM_CORES=1 TARGET=hw_emu PLATFORM=xilinx_u280_gen3x16_xdma_1_202211_1 CONFIGS="-DEXT_GFX_ENABLE" make > build_u280_hw_emu_gfx_dbg_1c.log 2>&1 &
+PREFIX=build_gfx_dbg_1c DEBUG=3 NUM_CORES=1 TARGET=hw PLATFORM=xilinx_u280_gen3x16_xdma_1_202211_1 CONFIGS="-DEXT_GFX_ENABLE" make > build_u280_hw_gfx_dbg_1c.log 2>&1 &
+PREFIX=build_dbg_1c DEBUG=3 NUM_CORES=1 TARGET=hw_emu PLATFORM=xilinx_u280_gen3x16_xdma_1_202211_1 make > build_u280_hw_emu_dbg_1c.log 2>&1 &
+PREFIX=build_dbg_1c DEBUG=3 NUM_CORES=1 TARGET=hw PLATFORM=xilinx_u280_gen3x16_xdma_1_202211_1 make > build_u280_hw_dbg_1c.log 2>&1 &
+PREFIX=build_base_1c NUM_CORES=1 TARGET=hw_emu PLATFORM=xilinx_u280_gen3x16_xdma_1_202211_1 make > build_u280_hw_emu_base_1c.log 2>&1 &
+PREFIX=build_base_1c NUM_CORES=1 TARGET=hw PLATFORM=xilinx_u280_gen3x16_xdma_1_202211_1 make > build_u280_hw_base_1c.log 2>&1 &
+PREFIX=build_gfx_1c NUM_CORES=1 TARGET=hw_emu PLATFORM=xilinx_u280_gen3x16_xdma_1_202211_1 CONFIGS="-DEXT_GFX_ENABLE" make > build_u280_hw_emu_gfx_1c.log 2>&1 &
+PREFIX=build_gfx_1c NUM_CORES=1 TARGET=hw PLATFORM=xilinx_u280_gen3x16_xdma_1_202211_1 CONFIGS="-DEXT_GFX_ENABLE" make > build_u280_hw_gfx_1c.log 2>&1 &
+
+PREFIX=build TARGET=hw_emu PLATFORM=xilinx_vck5000_gen3x16_xdma_1_202120_1 make > build_vck5k_hw_emu.log 2>&1 &
+PREFIX=build TARGET=hw_emu PLATFORM=xilinx_vck5000_gen3x16_xdma_1_202120_1 make > build_vck5k_hw.log 2>&1 &
+
+# debug hw_emu using xsim
+xsim --gui xilinx_u50_gen3x16_xdma_5_202210_1-0-vortex_afu.wdb &
+
+# debug hw using ILA
+platforminfo --json="hardwarePlatform.extensions.chipscope_debug" xilinx_u50_gen3x16_xdma_5_202210_1
+ls /dev/xfpga/xvc_pub*
+ls /dev/xvc_pub*
+debug_hw --xvc_pcie /dev/xfpga/xvc_pub.u2305.0 --hw_server
+debug_hw --xvc_pcie /dev/xvc_pub.u0 --hw_server
+debug_hw --vivado --host localhost --ltx_file ./build_xilinx_u50_gen3x16_xdma_5_202210_1_hw/_x/link/vivado/vpl/prj/prj.runs/impl_1/debug_nets.ltx &
+make chipscope TARGET=hw PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1
+
+# analyze build report
+vitis_analyzer build_xilinx_u50_gen3x16_xdma_5_202210_1_hw_4c/bin/vortex_afu.xclbin.link_summary
+
+# running test
+TARGET=hw PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 ./ci/blackbox.sh --driver=xrt --app=demo
+TARGET=hw_emu PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 ./ci/blackbox.sh --driver=xrt --app=demo
+TARGET=hw PLATFORM=xilinx_vck5000_gen3x16_xdma_1_202120_1 ./ci/blackbox.sh --driver=xrt --app=demo
+TARGET=hw_emu PLATFORM=xilinx_vck5000_gen3x16_xdma_1_202120_1 ./ci/blackbox.sh --driver=xrt --app=demo
+FPGA_BIN_DIR=<bin_dir> TARGET=hw_emu PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 ./ci/blackbox.sh --driver=xrt --app=demo
+FPGA_BIN_DIR=<bin_dir> TARGET=hw PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 ./ci/blackbox.sh --driver=xrt --app=demo
+FPGA_BIN_DIR=<bin_dir> TARGET=hw_emu PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 ./ci/blackbox.sh --driver=xrt --app=draw3d --args="-tbox.cgltrace -rbox_ref_128.png"
+FPGA_BIN_DIR=<bin_dir> TARGET=hw PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 ./ci/blackbox.sh --driver=xrt --app=draw3d --args="-tbox.cgltrace -rbox_ref_128.png"
+FPGA_BIN_DIR=<bin_dir> TARGET=hw_emu PLATFORM=xilinx_u280_gen3x16_xdma_1_202211_1 ./ci/blackbox.sh --driver=xrt --app=demo
+FPGA_BIN_DIR=<bin_dir> XRT_DEVICE_INDEX=1 TARGET=hw PLATFORM=xilinx_u280_gen3x16_xdma_1_202211_1 ./ci/blackbox.sh --driver=xrt --app=demo
+FPGA_BIN_DIR=<bin_dir> TARGET=hw_emu PLATFORM=xilinx_u280_gen3x16_xdma_1_202211_1 ./ci/blackbox.sh --driver=xrt --app=draw3d --args="-tbox.cgltrace -rbox_ref_128.png"
+FPGA_BIN_DIR=<bin_dir> XRT_DEVICE_INDEX=1 TARGET=hw PLATFORM=xilinx_u280_gen3x16_xdma_1_202211_1 ./ci/blackbox.sh --driver=xrt --app=draw3d --args="-tbox.cgltrace -rbox_ref_128.png"
+
+# build report logs
+<build_dir>/bin/vortex_afu.xclbin.info
+<build_dir>/_x/reports/link/link/imp/impl_1_full_util_routed.rpt
+<build_dir>/_x/reports/link/imp/impl_1_hw_bb_locked_timing_summary_routed.rpt # search for keyword "VIOLATED"
+<build_dir>/_x/logs/link/syn/ulp_vortex_afu_1_0_synth_1_runme.log
--- a/hw/syn/xilinx/test/.gitignore
+++ b/hw/syn/xilinx/test/.gitignore
@@ -0,0 +1,2 @@
+/project_1/*
+/.Xil/*
--- a/hw/syn/xilinx/test/Makefile
+++ b/hw/syn/xilinx/test/Makefile
@@ -0,0 +1,49 @@
+VIVADO = $(XILINX_VIVADO)/bin/vivado
+
+RTL_DIR = ../../../rtl
+AFU_DIR = $(RTL_DIR)/afu/xrt
+SCRIPT_DIR = ../../../scripts
+THIRD_PARTY_DIR = ../../../../third_party
+
+# include paths
+FPU_INCLUDE = -I$(RTL_DIR)/fpu
+ifneq (,$(findstring FPU_FPNEW,$(CONFIGS)))
+	FPU_INCLUDE += -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -I$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(THIRD_PARTY_DIR)/fpnew/src
+endif
+RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache
+RTL_INCLUDE += $(FPU_INCLUDE)
+RTL_INCLUDE += -Iproject_1_files
+
+# compilation flags
+CFLAGS += -DNDEBUG -DSYNTHESIS -DVIVADO
+CFLAGS += $(CONFIGS)
+CFLAGS += $(RTL_INCLUDE)
+CFLAGS += -DEXT_F_DISABLE
+#CFLAGS += -DNUM_CORES 4
+
+# update memory layout for 2MB RAM
+CFLAGS += -DSTARTUP_ADDR=32\'h80000
+CFLAGS += -DIO_BASE_ADDR=32\'hFF000
+
+COE_FILE := $(realpath project_1_files)/kernel.bin.coe
+ESCAPED_COE_FILE := $(shell echo "$(COE_FILE)" | sed -e 's/[\/&]/\\&/g')
+
+all: build
+
+gen-sources: project_1/sources.txt
+project_1/sources.txt:
+	mkdir -p project_1
+	$(SCRIPT_DIR)/gen_sources.sh $(CFLAGS) -P -Cproject_1/src -Oproject_1/sources.txt
+
+project.tcl: project.tcl.in
+	sed -e 's/%COE_FILE%/$(ESCAPED_COE_FILE)/g' < $< > $@
+
+build: project_1/vortex.xpr
+project_1/vortex.xpr: project_1/sources.txt project.tcl
+	$(VIVADO) -mode batch -source project.tcl -tclargs project_1/sources.txt project_1/src $(SCRIPT_DIR)
+
+run: project_1/vortex.xpr
+	$(VIVADO) project_1/vortex.xpr &
+
+clean:
+	rm -rf project_1 project.tcl
--- a/hw/syn/xilinx/test/kernel/Makefile
+++ b/hw/syn/xilinx/test/kernel/Makefile
@@ -0,0 +1,51 @@
+XLEN ?= 32
+
+ifeq ($(XLEN),64)
+RISCV_TOOLCHAIN_PATH ?= /opt/riscv64-gnu-toolchain
+CFLAGS += -march=rv64imafd -mabi=lp64d
+else
+RISCV_TOOLCHAIN_PATH ?= /opt/riscv-gnu-toolchain
+CFLAGS += -march=rv32imaf -mabi=ilp32f
+endif
+
+RISCV_PREFIX ?= riscv$(XLEN)-unknown-elf
+
+VORTEX_RT_PATH ?= $(realpath ../../../../../kernel)
+BIN2COE_PATH ?= ../../../../../../bin2coe
+
+CC = $(RISCV_TOOLCHAIN_PATH)/bin/$(RISCV_PREFIX)-gcc
+AR = $(RISCV_TOOLCHAIN_PATH)/bin/$(RISCV_PREFIX)-gcc-ar
+DP = $(RISCV_TOOLCHAIN_PATH)/bin/$(RISCV_PREFIX)-objdump
+CP = $(RISCV_TOOLCHAIN_PATH)/bin/$(RISCV_PREFIX)-objcopy
+
+CFLAGS += -O3 -Wstack-usage=1024 -ffreestanding -nostartfiles -fdata-sections -ffunction-sections
+CFLAGS += -I$(VORTEX_RT_PATH)/include -I$(VORTEX_RT_PATH)/../hw
+
+LDFLAGS += -lm -Wl,-Bstatic,-T,$(VORTEX_RT_PATH)/linker/vx_link$(XLEN).ld,--defsym=STARTUP_ADDR=0x80000000
+
+PROJECT = kernel
+
+SRCS = main.c start.S
+
+all: $(PROJECT).elf $(PROJECT).hex $(PROJECT).bin $(PROJECT).dump $(PROJECT).bin.coe
+
+$(PROJECT).dump: $(PROJECT).elf
+	$(DP) -D $(PROJECT).elf > $(PROJECT).dump
+
+$(PROJECT).hex: $(PROJECT).elf
+	$(CP) -O ihex $(PROJECT).elf $(PROJECT).hex
+
+$(PROJECT).bin: $(PROJECT).elf
+	$(CP) -O binary $(PROJECT).elf $(PROJECT).bin
+
+$(PROJECT).bin.coe: $(PROJECT).bin
+	$(BIN2COE_PATH)/bin2coe $(PROJECT).bin --out=$(PROJECT).bin.coe --binary=$(PROJECT).bin --data=$(PROJECT).dat --binaddr=8192 --depth=16384 --wordsize=64
+
+$(PROJECT).elf: $(SRCS)
+	$(CC) $(CFLAGS) $(SRCS) $(LDFLAGS) -o $(PROJECT).elf
+
+.depend: $(SRCS)
+	$(CC) $(CFLAGS) -MM $^ > .depend;
+
+clean:
+	rm -rf *.bin *.elf *.hex *.dump *.coe .depend 
--- a/hw/syn/xilinx/test/kernel/kernel.dat
+++ b/hw/syn/xilinx/test/kernel/kernel.dat
@@ -0,0 +1,3 @@
+@1
+000000C00000008000000002,
+00000003000000020000000100000000,
--- a/hw/syn/xilinx/test/kernel/main.c
+++ b/hw/syn/xilinx/test/kernel/main.c
@@ -0,0 +1,38 @@
+// Copyright © 2019-2023
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+// http://www.apache.org/licenses/LICENSE-2.0
+// 
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include <stdint.h>
+#include <vx_intrinsics.h>
+
+#define KERNEL_ARG_DEV_MEM_ADDR 0x40
+
+typedef struct {
+  uint32_t count;
+  uint32_t src_addr;
+  uint32_t dst_addr;  
+} kernel_arg_t;
+
+int main() {
+	kernel_arg_t* arg = (kernel_arg_t*)KERNEL_ARG_DEV_MEM_ADDR;
+	uint32_t count   = arg->count;
+	int32_t* src_ptr = (int32_t*)arg->src_addr;
+	int32_t* dst_ptr = (int32_t*)arg->dst_addr;
+
+	uint32_t offset  = vx_core_id() * count;
+	
+	for (uint32_t i = 0; i < count; ++i) {
+		dst_ptr[offset + i] = src_ptr[offset + i];
+	}
+	
+	return 0;
+}
--- a/hw/syn/xilinx/test/kernel/start.S
+++ b/hw/syn/xilinx/test/kernel/start.S
@@ -0,0 +1,23 @@
+// Copyright © 2019-2023
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+// http://www.apache.org/licenses/LICENSE-2.0
+// 
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+.section .init, "ax"
+.global _start
+.type _start, @function
+_start:
+  # call main routine
+  call main
+
+  # end execution
+  .insn r 0x0b, 0, 0, x0, x0, x0
+.size _start, .-_start
--- a/hw/syn/xilinx/test/project.tcl.in
+++ b/hw/syn/xilinx/test/project.tcl.in
--- a/hw/syn/xilinx/test/project_1_files/Vortex_top.v
+++ b/hw/syn/xilinx/test/project_1_files/Vortex_top.v
@@ -0,0 +1,208 @@
+// Copyright © 2019-2023
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+// http://www.apache.org/licenses/LICENSE-2.0
+// 
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+`include "VX_define.vh"
+
+module Vortex_top #(
+	parameter C_M_AXI_GMEM_DATA_WIDTH = 512,
+	parameter C_M_AXI_GMEM_ADDR_WIDTH = `XLEN,
+	parameter C_M_AXI_GMEM_ID_WIDTH   = 32,
+	parameter C_M_AXI_MEM_NUM_BANKS   = 1
+) (
+	input wire                                  clk,
+	input wire                                  reset,
+
+	// AXI4 memory interface 
+	output wire                                 m_axi_mem_awvalid,
+	input  wire                                 m_axi_mem_awready,
+	output wire [C_M_AXI_GMEM_ADDR_WIDTH-1:0]   m_axi_mem_awaddr,
+	output wire [C_M_AXI_GMEM_ID_WIDTH - 1:0]   m_axi_mem_awid,
+	output wire [7:0]                           m_axi_mem_awlen,
+	output wire [2:0]                           m_axi_mem_awsize,
+	output wire [1:0]                           m_axi_mem_awburst,
+	output wire [1:0]                           m_axi_mem_awlock,
+	output wire [3:0]                           m_axi_mem_awcache,
+	output wire [2:0]                           m_axi_mem_awprot,
+	output wire [3:0]                           m_axi_mem_awqos,
+	output wire                                 m_axi_mem_wvalid,
+	input  wire                                 m_axi_mem_wready,
+	output wire [C_M_AXI_GMEM_DATA_WIDTH-1:0]   m_axi_mem_wdata,
+	output wire [C_M_AXI_GMEM_DATA_WIDTH/8-1:0] m_axi_mem_wstrb,
+	output wire                                 m_axi_mem_wlast,
+	output wire                                 m_axi_mem_arvalid,
+	input  wire                                 m_axi_mem_arready,
+	output wire [C_M_AXI_GMEM_ADDR_WIDTH-1:0]   m_axi_mem_araddr,
+	output wire [C_M_AXI_GMEM_ID_WIDTH-1:0]     m_axi_mem_arid,
+	output wire [7:0]                           m_axi_mem_arlen,
+	output wire [2:0]                           m_axi_mem_arsize,
+	output wire [1:0]                           m_axi_mem_arburst,
+	output wire [1:0]                           m_axi_mem_arlock,
+	output wire [3:0]                           m_axi_mem_arcache,
+	output wire [2:0]                           m_axi_mem_arprot,
+	output wire [3:0]                           m_axi_mem_arqos,
+	input  wire                                 m_axi_mem_rvalid,
+	output wire                                 m_axi_mem_rready,
+	input  wire [C_M_AXI_GMEM_DATA_WIDTH - 1:0] m_axi_mem_rdata,
+	input  wire                                 m_axi_mem_rlast,
+	input  wire [C_M_AXI_GMEM_ID_WIDTH - 1:0]   m_axi_mem_rid,
+	input  wire [1:0]                           m_axi_mem_rresp,
+	input  wire                                 m_axi_mem_bvalid,
+	output wire                                 m_axi_mem_bready,
+	input  wire [1:0]                           m_axi_mem_bresp,
+	input  wire [C_M_AXI_GMEM_ID_WIDTH - 1:0]	m_axi_mem_bid,
+
+	input  wire                         		dcr_wr_valid,
+    input  wire [`VX_DCR_ADDR_WIDTH-1:0]		dcr_wr_addr,
+    input  wire [`VX_DCR_DATA_WIDTH-1:0] 		dcr_wr_data,
+
+	output wire                                 busy
+);
+
+	wire                                 m_axi_mem_awvalid_a [C_M_AXI_MEM_NUM_BANKS];
+	wire                                 m_axi_mem_awready_a [C_M_AXI_MEM_NUM_BANKS];
+	wire [C_M_AXI_GMEM_ADDR_WIDTH-1:0]   m_axi_mem_awaddr_a [C_M_AXI_MEM_NUM_BANKS];
+	wire [C_M_AXI_GMEM_ID_WIDTH - 1:0]   m_axi_mem_awid_a [C_M_AXI_MEM_NUM_BANKS];
+	wire [7:0]                           m_axi_mem_awlen_a [C_M_AXI_MEM_NUM_BANKS];
+	wire [2:0]                           m_axi_mem_awsize_a [C_M_AXI_MEM_NUM_BANKS];
+	wire [1:0]                           m_axi_mem_awburst_a [C_M_AXI_MEM_NUM_BANKS];
+	wire [1:0]                           m_axi_mem_awlock_a [C_M_AXI_MEM_NUM_BANKS];
+	wire [3:0]                           m_axi_mem_awcache_a [C_M_AXI_MEM_NUM_BANKS];
+	wire [2:0]                           m_axi_mem_awprot_a [C_M_AXI_MEM_NUM_BANKS];
+	wire [3:0]                           m_axi_mem_awqos_a [C_M_AXI_MEM_NUM_BANKS];
+	wire                                 m_axi_mem_wvalid_a [C_M_AXI_MEM_NUM_BANKS];
+	wire                                 m_axi_mem_wready_a [C_M_AXI_MEM_NUM_BANKS];
+	wire [C_M_AXI_GMEM_DATA_WIDTH-1:0]   m_axi_mem_wdata_a [C_M_AXI_MEM_NUM_BANKS];
+	wire [C_M_AXI_GMEM_DATA_WIDTH/8-1:0] m_axi_mem_wstrb_a [C_M_AXI_MEM_NUM_BANKS];
+	wire                                 m_axi_mem_wlast_a [C_M_AXI_MEM_NUM_BANKS];
+	wire                                 m_axi_mem_arvalid_a [C_M_AXI_MEM_NUM_BANKS];
+	wire                                 m_axi_mem_arready_a [C_M_AXI_MEM_NUM_BANKS];
+	wire [C_M_AXI_GMEM_ADDR_WIDTH-1:0]   m_axi_mem_araddr_a [C_M_AXI_MEM_NUM_BANKS];
+	wire [C_M_AXI_GMEM_ID_WIDTH-1:0]     m_axi_mem_arid_a [C_M_AXI_MEM_NUM_BANKS];
+	wire [7:0]                           m_axi_mem_arlen_a [C_M_AXI_MEM_NUM_BANKS];
+	wire [2:0]                           m_axi_mem_arsize_a [C_M_AXI_MEM_NUM_BANKS];
+	wire [1:0]                           m_axi_mem_arburst_a [C_M_AXI_MEM_NUM_BANKS];
+	wire [1:0]                           m_axi_mem_arlock_a [C_M_AXI_MEM_NUM_BANKS];
+	wire [3:0]                           m_axi_mem_arcache_a [C_M_AXI_MEM_NUM_BANKS];
+	wire [2:0]                           m_axi_mem_arprot_a [C_M_AXI_MEM_NUM_BANKS];
+	wire [3:0]                           m_axi_mem_arqos_a [C_M_AXI_MEM_NUM_BANKS];
+	wire                                 m_axi_mem_rvalid_a [C_M_AXI_MEM_NUM_BANKS];
+	wire                                 m_axi_mem_rready_a [C_M_AXI_MEM_NUM_BANKS];
+	wire [C_M_AXI_GMEM_DATA_WIDTH - 1:0] m_axi_mem_rdata_a [C_M_AXI_MEM_NUM_BANKS];
+	wire                                 m_axi_mem_rlast_a [C_M_AXI_MEM_NUM_BANKS];
+	wire [C_M_AXI_GMEM_ID_WIDTH - 1:0]   m_axi_mem_rid_a [C_M_AXI_MEM_NUM_BANKS];
+	wire [1:0]                           m_axi_mem_rresp_a [C_M_AXI_MEM_NUM_BANKS];
+	wire                                 m_axi_mem_bvalid_a [C_M_AXI_MEM_NUM_BANKS];
+	wire                                 m_axi_mem_bready_a [C_M_AXI_MEM_NUM_BANKS];
+	wire [1:0]                           m_axi_mem_bresp_a [C_M_AXI_MEM_NUM_BANKS];
+	wire [C_M_AXI_GMEM_ID_WIDTH - 1:0]	 m_axi_mem_bid_a [C_M_AXI_MEM_NUM_BANKS];
+
+	assign m_axi_mem_awvalid = m_axi_mem_awvalid_a[0];
+	assign m_axi_mem_awready_a[0] = m_axi_mem_awready;
+	assign m_axi_mem_awaddr = m_axi_mem_awaddr_a[0];
+	assign m_axi_mem_awid = m_axi_mem_awid_a[0];
+	assign m_axi_mem_awlen = m_axi_mem_awlen_a[0];
+	assign m_axi_mem_awsize = m_axi_mem_awsize_a[0];
+	assign m_axi_mem_awburst = m_axi_mem_awburst_a[0];
+	assign m_axi_mem_awlock = m_axi_mem_awlock_a[0];
+	assign m_axi_mem_awcache = m_axi_mem_awcache_a[0];
+	assign m_axi_mem_awprot = m_axi_mem_awprot_a[0];
+	assign m_axi_mem_awqos = m_axi_mem_awqos_a[0];
+
+	assign m_axi_mem_wvalid = m_axi_mem_wvalid_a[0];
+	assign m_axi_mem_wready_a[0] = m_axi_mem_wready;
+	assign m_axi_mem_wdata = m_axi_mem_wdata_a[0];
+	assign m_axi_mem_wstrb = m_axi_mem_wstrb_a[0];
+	assign m_axi_mem_wlast = m_axi_mem_wlast_a[0];
+
+	assign m_axi_mem_arvalid = m_axi_mem_arvalid_a[0];
+	assign m_axi_mem_arready_a[0] = m_axi_mem_arready;
+	assign m_axi_mem_araddr = m_axi_mem_araddr_a[0];
+	assign m_axi_mem_arid = m_axi_mem_arid_a[0];
+	assign m_axi_mem_arlen = m_axi_mem_arlen_a[0];
+	assign m_axi_mem_arsize = m_axi_mem_arsize_a[0];
+	assign m_axi_mem_arburst = m_axi_mem_arburst_a[0];
+	assign m_axi_mem_arlock = m_axi_mem_arlock_a[0];
+	assign m_axi_mem_arcache = m_axi_mem_arcache_a[0];
+	assign m_axi_mem_arprot = m_axi_mem_arprot_a[0];
+	assign m_axi_mem_arqos = m_axi_mem_arqos_a[0];
+
+	assign m_axi_mem_rvalid_a[0] = m_axi_mem_rvalid;
+	assign m_axi_mem_rready = m_axi_mem_rready_a[0];
+	assign m_axi_mem_rdata_a[0] = m_axi_mem_rdata;					
+	assign m_axi_mem_rlast_a[0] = m_axi_mem_rlast;
+	assign m_axi_mem_rid_a[0] = m_axi_mem_rid;
+	assign m_axi_mem_rresp_a[0] = m_axi_mem_rresp;
+
+	assign m_axi_mem_bvalid_a[0] = m_axi_mem_bvalid;
+	assign m_axi_mem_bready = m_axi_mem_bready_a[0];		
+	assign m_axi_mem_bresp_a[0] = m_axi_mem_bresp;
+	assign m_axi_mem_bid_a[0] = m_axi_mem_bid;
+
+	Vortex_axi #(
+		.AXI_DATA_WIDTH (C_M_AXI_GMEM_DATA_WIDTH),
+		.AXI_ADDR_WIDTH (C_M_AXI_GMEM_ADDR_WIDTH),
+		.AXI_TID_WIDTH  (C_M_AXI_GMEM_ID_WIDTH)
+	) inst (
+		.clk			(clk),
+		.reset			(reset),
+
+		.m_axi_awvalid	(m_axi_mem_awvalid_a),
+		.m_axi_awready	(m_axi_mem_awready_a),
+		.m_axi_awaddr	(m_axi_mem_awaddr_a),
+		.m_axi_awid		(m_axi_mem_awid_a),
+		.m_axi_awlen	(m_axi_mem_awlen_a),
+		.m_axi_awsize	(m_axi_mem_awsize_a),
+		.m_axi_awburst	(m_axi_mem_awburst_a),
+		.m_axi_awlock	(m_axi_mem_awlock_a),
+		.m_axi_awcache	(m_axi_mem_awcache_a),
+		.m_axi_awprot	(m_axi_mem_awprot_a),
+		.m_axi_awqos	(m_axi_mem_awqos_a),
+
+		.m_axi_wvalid	(m_axi_mem_wvalid_a),
+		.m_axi_wready	(m_axi_mem_wready_a),
+		.m_axi_wdata	(m_axi_mem_wdata_a),
+		.m_axi_wstrb	(m_axi_mem_wstrb_a),
+		.m_axi_wlast	(m_axi_mem_wlast_a),
+
+		.m_axi_bvalid	(m_axi_mem_bvalid_a),
+		.m_axi_bready	(m_axi_mem_bready_a),
+		.m_axi_bid		(m_axi_mem_bid_a),
+		.m_axi_bresp	(m_axi_mem_bresp_a),		
+
+		.m_axi_arvalid	(m_axi_mem_arvalid_a),
+		.m_axi_arready	(m_axi_mem_arready_a),
+		.m_axi_araddr	(m_axi_mem_araddr_a),
+		.m_axi_arid		(m_axi_mem_arid_a),
+		.m_axi_arlen	(m_axi_mem_arlen_a),
+		.m_axi_arsize	(m_axi_mem_arsize_a),
+		.m_axi_arburst	(m_axi_mem_arburst_a),
+		.m_axi_arlock	(m_axi_mem_arlock_a),
+		.m_axi_arcache	(m_axi_mem_arcache_a),
+		.m_axi_arprot	(m_axi_mem_arprot_a),
+		.m_axi_arqos	(m_axi_mem_arqos_a),
+
+		.m_axi_rvalid	(m_axi_mem_rvalid_a),
+		.m_axi_rready	(m_axi_mem_rready_a),
+		.m_axi_rdata	(m_axi_mem_rdata_a),	
+		.m_axi_rid    	(m_axi_mem_rid_a),
+		.m_axi_rresp	(m_axi_mem_rresp_a),
+		.m_axi_rlast	(m_axi_mem_rlast_a),
+
+		.dcr_wr_valid	(dcr_wr_valid),
+		.dcr_wr_addr	(dcr_wr_addr),
+		.dcr_wr_data	(dcr_wr_data),
+
+		.busy           (busy)
+	);
+	
+endmodule
--- a/hw/syn/xilinx/test/project_1_files/kernel.bin.coe
+++ b/hw/syn/xilinx/test/project_1_files/kernel.bin.coe
--- a/hw/syn/xilinx/test/project_1_files/testbench.v
+++ b/hw/syn/xilinx/test/project_1_files/testbench.v
@@ -0,0 +1,119 @@
+// Copyright © 2019-2023
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+// http://www.apache.org/licenses/LICENSE-2.0
+// 
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+`include "VX_define.vh"
+
+`timescale 10ns / 1ns
+
+`define CYCLE_TIME  4
+
+module testbench;
+    reg clk;
+    reg resetn;
+    reg [43:0] cycles;
+
+    reg vx_running;
+    reg vx_reset_wait;
+    reg vx_busy_wait;
+    wire vx_busy;
+
+    reg dcr_wr_valid;
+    reg [11:0] dcr_wr_addr;
+    reg [31:0] dcr_wr_data;
+
+    design_1_wrapper UUD(
+        .clk_100MHz     (clk),
+        .resetn         (resetn),
+        .vx_reset       (~resetn || ~vx_running),
+        .dcr_wr_valid   (dcr_wr_valid),
+        .dcr_wr_addr    (dcr_wr_addr),
+        .dcr_wr_data    (dcr_wr_data),
+        .vx_busy        (vx_busy)
+    );
+
+    always #(`CYCLE_TIME/2) 
+        clk = ~clk;
+    
+    initial begin
+        clk    = 1'b0;
+        resetn = 1'b0;
+     #4 resetn = 1'b1;
+    end
+    
+    always @(posedge clk) begin
+        if (~resetn) begin
+            cycles <= 0;
+        end else begin
+            cycles <= cycles + 1;
+        end
+    end
+
+    reg [7:0] vx_reset_ctr;
+    always @(posedge clk) begin
+        if (vx_reset_wait) begin
+            vx_reset_ctr <= vx_reset_ctr + 1;
+        end else begin
+            vx_reset_ctr <= 0;
+        end
+    end
+
+    always @(posedge clk) begin
+        if (~resetn) begin
+            vx_running    <= 0;
+            vx_reset_wait <= 0;
+            vx_busy_wait  <= 0;
+            dcr_wr_valid  <= 0;
+            dcr_wr_addr   <= 0;
+            dcr_wr_data   <= 0;
+        end else begin            
+            case (cycles)
+            1:  begin
+                dcr_wr_valid <= 1;
+                dcr_wr_addr  <= `VX_DCR_BASE_STARTUP_ADDR0;
+                dcr_wr_data  <= `STARTUP_ADDR;                    
+            end
+            2: begin
+                dcr_wr_valid <= 0;
+                dcr_wr_addr  <= 0;
+                dcr_wr_data  <= 0;
+            end
+            3: begin
+                vx_reset_wait <= 1;
+            end
+            default:;
+            endcase
+            
+            if (vx_running) begin
+                if (vx_busy_wait) begin
+                    if (vx_busy) begin
+                        vx_busy_wait <= 0;
+                    end
+                end else begin
+                    if (~vx_busy) begin
+                        vx_running <= 0;   
+                        $display("done!");
+                        $finish;           
+                    end
+                end
+            end else begin
+                if (vx_reset_wait && vx_reset_ctr == (`RESET_DELAY-1)) begin
+                    $display("start!");
+                    vx_reset_wait <= 0;
+                    vx_running    <= 1;                    
+                    vx_busy_wait  <= 1;
+                end
+            end
+        end
+    end
+
+endmodule
--- a/hw/syn/xilinx/xrt/.gitignore
+++ b/hw/syn/xilinx/xrt/.gitignore
@@ -0,0 +1 @@
+/build*/*
--- a/hw/syn/xilinx/xrt/Makefile
+++ b/hw/syn/xilinx/xrt/Makefile
@@ -0,0 +1,200 @@
+ifneq ($(findstring Makefile, $(MAKEFILE_LIST)), Makefile)
+help:
+	$(ECHO) "Makefile Usage:"
+	$(ECHO) "  make all TARGET=<sw_emu/hw_emu/hw> PLATFORM=<FPGA platform>"
+	$(ECHO) "      Command to generate the design for specified Target and Device."
+	$(ECHO) ""
+	$(ECHO) "  make clean"
+	$(ECHO) "      Command to remove the generated non-hardware files."
+	$(ECHO) ""
+endif
+
+TARGET ?= hw
+PLATFORM ?=
+XLEN ?= 32
+NUM_CORES ?= 1
+PREFIX ?= build$(XLEN)
+MAX_JOBS ?= 8
+
+RTL_DIR = ../../../../rtl
+AFU_DIR = $(RTL_DIR)/afu/xrt
+DPI_DIR = ../../../../dpi
+SCRIPT_DIR = ../../../../scripts
+THIRD_PARTY_DIR = ../../../../../third_party
+
+VIVADO = $(XILINX_VIVADO)/bin/vivado
+VPP = $(XILINX_VITIS)/bin/v++
+CP = cp -rf
+RMDIR = rm -rf
+ECHO = @echo
+
+NCPUS := $(shell grep -c ^processor /proc/cpuinfo)
+JOBS ?= $(shell echo $$(( $(NCPUS) > $(MAX_JOBS) ? $(MAX_JOBS) : $(NCPUS) )))
+
+PLATFORM_TO_XSA = $(strip $(patsubst %.xpfm, % , $(shell basename $(PLATFORM))))
+XSA := $(call PLATFORM_TO_XSA, $(PLATFORM))
+
+DEV_ARCH := $(shell platforminfo -p $(PLATFORM) | grep 'FPGA Family' | sed 's/.*://' | sed '/ai_engine/d' | sed 's/^[[:space:]]*//')
+CPU_TYPE := $(shell platforminfo -p $(PLATFORM) | grep 'CPU Type' | sed 's/.*://' | sed '/ai_engine/d' | sed 's/^[[:space:]]*//')
+
+BUILD_DIR = $(PREFIX)_$(XSA)_$(TARGET)
+BIN_DIR   = $(BUILD_DIR)/bin
+
+XO_CONTAINER = $(BIN_DIR)/vortex_afu.xo
+XCLBIN_CONTAINER = $(BIN_DIR)/vortex_afu.xclbin
+
+# Control RTL debug tracing states
+DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_PIPELINE  
+DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_ICACHE
+DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_DCACHE
+DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_MEM
+DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_BANK 
+DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_MSHR
+DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_TAG
+DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_DATA
+DBG_TRACE_FLAGS += -DDBG_TRACE_AFU
+DBG_TRACE_FLAGS += -DDBG_TRACE_TEX
+DBG_TRACE_FLAGS += -DDBG_TRACE_RASTER
+DBG_TRACE_FLAGS += -DDBG_TRACE_ROP
+DBG_TRACE_FLAGS += -DDBG_TRACE_GBAR
+
+# Control logic analyzer monitors
+DBG_SCOPE_FLAGS += -DDBG_SCOPE_AFU
+DBG_SCOPE_FLAGS += -DDBG_SCOPE_ISSUE
+DBG_SCOPE_FLAGS += -DDBG_SCOPE_FETCH
+DBG_SCOPE_FLAGS += -DDBG_SCOPE_LSU
+DBG_SCOPE_FLAGS += -DDBG_SCOPE_RASTER
+DBG_SCOPE_FLAGS += -DDBG_SCOPE_MSCHED
+
+# cluster configuration
+CONFIGS_1c  := -DNUM_CLUSTERS=1 -DNUM_CORES=1
+CONFIGS_2c  := -DNUM_CLUSTERS=1 -DNUM_CORES=2
+CONFIGS_4c  := -DNUM_CLUSTERS=1 -DNUM_CORES=4
+CONFIGS_8c	:= -DNUM_CLUSTERS=1 -DNUM_CORES=8
+CONFIGS_16c	:= -DNUM_CLUSTERS=1 -DNUM_CORES=16 -DL2_ENABLE
+CONFIGS_32c := -DNUM_CLUSTERS=2 -DNUM_CORES=16 -DL2_ENABLE
+CONFIGS_64c := -DNUM_CLUSTERS=4 -DNUM_CORES=16 -DL2_ENABLE
+CONFIGS += $(CONFIGS_$(NUM_CORES)c)
+
+# include paths
+FPU_INCLUDE = -I$(RTL_DIR)/fpu
+ifneq (,$(findstring FPU_FPNEW,$(CONFIGS)))
+	FPU_INCLUDE += -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -I$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(THIRD_PARTY_DIR)/fpnew/src
+endif
+RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache -I$(AFU_DIR)
+RTL_INCLUDE += $(FPU_INCLUDE)
+
+# Kernel compiler global settings
+VPP_FLAGS += --link --target $(TARGET) --platform $(PLATFORM) --save-temps --no_ip_cache
+VPP_FLAGS += --vivado.synth.jobs $(JOBS) --vivado.impl.jobs $(JOBS)
+
+ifeq ($(DEV_ARCH), zynquplus)
+# ztnq
+else ifeq ($(DEV_ARCH), versal)
+# versal
+else
+# alveo
+VPP_FLAGS += --connectivity.sp vortex_afu_1.m_axi_mem_0:HBM[0:15]
+endif
+
+VPP_FLAGS += --report_level 2
+VPP_FLAGS += --config ../vitis.ini
+
+# Enable perf counters
+ifdef PERF
+	CFLAGS += -DPERF_ENABLE
+endif
+
+# Generates profile summary report
+ifdef PROFILE
+	VPP_FLAGS += --profile_kernel data:all:all:all
+	VPP_FLAGS += --profile_kernel stall:all:all:all
+endif
+
+ifeq ($(TARGET), hw_emu)
+	CFLAGS += -DSIMULATION
+endif
+
+# Debugigng
+ifdef DEBUG
+	VPP_FLAGS += -g --debug.protocol all
+	ifeq ($(TARGET), hw)
+		CFLAGS += -DNDEBUG -DSCOPE $(DBG_SCOPE_FLAGS)
+		SCOPE_JSON += $(BUILD_DIR)/scope.json		
+		#CFLAGS += -DNDEBUG -DCHIPSCOPE $(DBG_SCOPE_FLAGS)
+		#VPP_FLAGS += --debug.chipscope vortex_afu_1
+	else		
+		VPP_FLAGS += --vivado.prop fileset.sim_1.xsim.elaborate.debug_level=all
+		CFLAGS += $(DBG_TRACE_FLAGS)
+	endif
+else
+	VPP_FLAGS += --optimize 3
+	CFLAGS += -DNDEBUG
+endif
+
+# compilation flags
+CFLAGS += -DSYNTHESIS -DVIVADO
+CFLAGS += -DXLEN_$(XLEN)
+CFLAGS += $(CONFIGS)
+CFLAGS += $(RTL_INCLUDE)
+
+# ast dump flags
+XML_CFLAGS = $(filter-out -DSYNTHESIS -DVIVADO, $(CFLAGS)) -I$(DPI_DIR)
+
+# RTL Kernel only supports Hardware and Hardware Emulation.
+ifneq ($(TARGET),$(findstring $(TARGET), hw hw_emu))
+	$(warning WARNING:Application supports only hw hw_emu TARGET. Please use the target for running the application)
+endif
+
+.PHONY: all clean gen-sources gen-ast emconfig check-devices
+
+all: check-devices emconfig $(XCLBIN_CONTAINER) report
+
+gen-sources: $(BUILD_DIR)/sources.txt
+$(BUILD_DIR)/sources.txt:
+	mkdir -p $(BUILD_DIR); cd $(BUILD_DIR); $(SCRIPT_DIR)/gen_sources.sh -P $(CFLAGS) -Csrc -Osources.txt
+
+gen-ast: $(BUILD_DIR)/vortex.xml
+$(BUILD_DIR)/vortex.xml:	
+	mkdir -p $(BUILD_DIR); cd $(BUILD_DIR); verilator --xml-only -O0 $(XML_CFLAGS) vortex_afu.v --xml-output vortex.xml
+
+scope-json: $(BUILD_DIR)/scope.json
+$(BUILD_DIR)/scope.json: $(BUILD_DIR)/vortex.xml
+	mkdir -p $(BUILD_DIR); cd $(BUILD_DIR); $(SCRIPT_DIR)/scope.py vortex.xml -o scope.json
+
+gen-xo: $(XO_CONTAINER)
+$(XO_CONTAINER): $(BUILD_DIR)/sources.txt
+	mkdir -p $(BUILD_DIR); cd $(BUILD_DIR);	$(VIVADO) -mode batch -source ../scripts/gen_xo.tcl -tclargs ../$(XO_CONTAINER) vortex_afu sources.txt $(SCRIPT_DIR) ../$(BUILD_DIR)
+
+gen-bin: $(XCLBIN_CONTAINER)
+$(XCLBIN_CONTAINER): $(XO_CONTAINER) $(SCOPE_JSON)
+	mkdir -p $(BIN_DIR); cd $(BUILD_DIR); $(VPP) $(VPP_FLAGS) -o ../$(XCLBIN_CONTAINER) ../$(XO_CONTAINER)
+
+emconfig: $(BIN_DIR)/emconfig.json
+$(BIN_DIR)/emconfig.json:
+	mkdir -p $(BIN_DIR); cd $(BUILD_DIR); emconfigutil --platform $(PLATFORM) --od ../$(BIN_DIR)
+
+report: $(XCLBIN_CONTAINER)
+ifeq ($(TARGET),$(findstring $(TARGET), hw))
+	cp $(BUILD_DIR)/_x/logs/link/syn/ulp_vortex_afu_1_0_synth_1_runme.log $(BUILD_DIR)/bin/runme.log
+	cp $(BUILD_DIR)/_x/reports/link/imp/impl_1_full_util_routed.rpt $(BUILD_DIR)/bin/synthesis.log
+	cp $(BUILD_DIR)/_x/reports/link/imp/impl_1_hw_bb_locked_timing_summary_routed.rpt $(BUILD_DIR)/bin/timing.log	
+endif
+	
+hwserver:
+	debug_hw --xvc_pcie /dev/xfpga/xvc_pub.u2305.0 --hw_server &
+
+chipscope:	
+	debug_hw --vivado --host localhost --ltx_file $(BUILD_DIR)/_x/link/vivado/vpl/prj/prj.runs/impl_1/debug_nets.ltx &
+
+clean:
+	$(RMDIR) $(BUILD_DIR)
+
+# Check the devices avaiable
+check-devices:
+ifndef PLATFORM
+	$(error PLATFORM not set. Please set the PLATFORM properly and rerun. Run "make help" for more details.)
+endif
+ifndef XILINX_VITIS
+	$(error XILINX_VITIS variable is not set, please set correctly and rerun)
+endif
--- a/hw/syn/xilinx/xrt/kill_build.sh
+++ b/hw/syn/xilinx/xrt/kill_build.sh
@@ -0,0 +1,25 @@
+#!/bin/sh
+
+# Copyright © 2019-2023
+# 
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+# http://www.apache.org/licenses/LICENSE-2.0
+# 
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+ps -A | grep xrcserver | awk '{print $1}' | xargs kill -9 $1
+ps -A | grep loader | awk '{print $1}' | xargs kill -9 $1
+ps -A | grep vpl | awk '{print $1}' | xargs kill -9 $1
+ps -A | grep v++ | awk '{print $1}' | xargs kill -9 $1
+ps -A | grep vivado | awk '{print $1}' | xargs kill -9 $1
+ps -A | grep runme.sh | awk '{print $1}' | xargs kill -9 $1
+ps -A | grep ISEWrap.sh | awk '{print $1}' | xargs kill -9 $1
+ps -A | grep vrs | awk '{print $1}' | xargs kill -9 $1
+ps -A | grep xcd | awk '{print $1}' | xargs kill -9 $1
+ps -A | grep make | awk '{print $1}' | xargs kill -9 $1
--- a/hw/syn/xilinx/xrt/kill_hwserver.sh
+++ b/hw/syn/xilinx/xrt/kill_hwserver.sh
@@ -0,0 +1,19 @@
+#!/bin/bash
+
+# Copyright © 2019-2023
+# 
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+# http://www.apache.org/licenses/LICENSE-2.0
+# 
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+ps -A | grep debug_hw | awk '{print $1}' | xargs kill -9 $1
+ps -A | grep python3 | awk '{print $1}' | xargs kill -9 $1
+ps -A | grep xvc_pcie | awk '{print $1}' | xargs kill -9 $1
+ps -A | grep hw_server | awk '{print $1}' | xargs kill -9 $1
--- a/hw/syn/xilinx/xrt/kill_sim.sh
+++ b/hw/syn/xilinx/xrt/kill_sim.sh
@@ -0,0 +1,19 @@
+#!/bin/sh
+
+# Copyright © 2019-2023
+# 
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+# http://www.apache.org/licenses/LICENSE-2.0
+# 
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+ps -A | grep launch_hw_emu.s | awk '{print $1}' | xargs kill -9 $1
+ps -A | grep simulate.sh | awk '{print $1}' | xargs kill -9 $1
+ps -A | grep xsim | awk '{print $1}' | xargs kill -9 $1
+ps -A | grep xsimk | awk '{print $1}' | xargs kill -9 $1
--- a/hw/syn/xilinx/xrt/scripts/gen_ip.tcl
+++ b/hw/syn/xilinx/xrt/scripts/gen_ip.tcl
@@ -0,0 +1,40 @@
+# Copyright © 2019-2023
+# 
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+# http://www.apache.org/licenses/LICENSE-2.0
+# 
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+if { $::argc != 1 } {
+    puts "ERROR: Program \"$::argv0\" requires 1 arguments!\n"
+    puts "Usage: $::argv0 <ip_dir>\n"
+    exit
+}
+
+set ip_dir [lindex $::argv 0]
+
+# IP folder does not exist. Create IP folder
+file mkdir ${ip_dir}
+
+# create_ip requires that a project is open in memory. 
+# Create project but don't do anything with it
+create_project -in_memory
+
+create_ip -name floating_point -vendor xilinx.com -library ip -version 7.1 -module_name xil_fdiv -dir ${ip_dir}
+set_property -dict [list CONFIG.Component_Name {xil_fdiv} CONFIG.Operation_Type {Divide} CONFIG.Flow_Control {NonBlocking} CONFIG.Has_ACLKEN {true} CONFIG.C_Has_UNDERFLOW {true} CONFIG.C_Has_OVERFLOW {true} CONFIG.C_Has_INVALID_OP {true} CONFIG.C_Has_DIVIDE_BY_ZERO {true} CONFIG.A_Precision_Type {Single} CONFIG.C_A_Exponent_Width {8} CONFIG.C_A_Fraction_Width {24} CONFIG.Result_Precision_Type {Single} CONFIG.C_Result_Exponent_Width {8} CONFIG.C_Result_Fraction_Width {24} CONFIG.C_Mult_Usage {No_Usage} CONFIG.Has_RESULT_TREADY {false} CONFIG.C_Latency {28} CONFIG.C_Rate {1}] [get_ips xil_fdiv]
+
+create_ip -name floating_point -vendor xilinx.com -library ip -version 7.1 -module_name xil_fsqrt -dir ${ip_dir}
+set_property -dict [list CONFIG.Component_Name {xil_fsqrt} CONFIG.Operation_Type {Square_root} CONFIG.Flow_Control {NonBlocking} CONFIG.Has_ACLKEN {true} CONFIG.C_Has_INVALID_OP {true} CONFIG.A_Precision_Type {Single} CONFIG.C_A_Exponent_Width {8} CONFIG.C_A_Fraction_Width {24} CONFIG.Result_Precision_Type {Single} CONFIG.C_Result_Exponent_Width {8} CONFIG.C_Result_Fraction_Width {24} CONFIG.C_Mult_Usage {No_Usage} CONFIG.Has_RESULT_TREADY {false} CONFIG.C_Latency {28} CONFIG.C_Rate {1}] [get_ips xil_fsqrt]
+
+create_ip -name floating_point -vendor xilinx.com -library ip -version 7.1 -module_name xil_fma -dir ${ip_dir}
+set_property -dict [list CONFIG.Component_Name {xil_fma} CONFIG.Operation_Type {FMA} CONFIG.Add_Sub_Value {Add} CONFIG.Flow_Control {NonBlocking} CONFIG.Has_ACLKEN {true} CONFIG.C_Has_UNDERFLOW {true} CONFIG.C_Has_OVERFLOW {true} CONFIG.C_Has_INVALID_OP {true} CONFIG.Has_A_TUSER {false} CONFIG.A_Precision_Type {Single} CONFIG.C_A_Exponent_Width {8} CONFIG.C_A_Fraction_Width {24} CONFIG.Result_Precision_Type {Single} CONFIG.C_Result_Exponent_Width {8} CONFIG.C_Result_Fraction_Width {24} CONFIG.C_Mult_Usage {Medium_Usage} CONFIG.Has_RESULT_TREADY {false} CONFIG.C_Latency {16} CONFIG.C_Rate {1} CONFIG.A_TUSER_Width {1}] [get_ips xil_fma]
+
+generate_target all [get_ips]
+
+close_project -delete
--- a/hw/syn/xilinx/xrt/scripts/gen_xo.tcl
+++ b/hw/syn/xilinx/xrt/scripts/gen_xo.tcl
@@ -0,0 +1,40 @@
+# Copyright © 2019-2023
+# 
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+# http://www.apache.org/licenses/LICENSE-2.0
+# 
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+if { $::argc != 5 } {
+    puts "ERROR: Program \"$::argv0\" requires 4 arguments!\n"
+    puts "Usage: $::argv0 <xoname> <krnl_name> <vcs_file> <tool_dir> <build_dir>\n"
+    exit
+}
+
+set xoname    [lindex $::argv 0]
+set krnl_name [lindex $::argv 1]
+set vcs_file  [lindex $::argv 2]
+set tool_dir  [lindex $::argv 3]
+set build_dir [lindex $::argv 4]
+
+set script_path [ file dirname [ file normalize [ info script ] ] ]
+
+if {[file exists "${xoname}"]} {
+    file delete -force "${xoname}"
+}
+
+set argv [list ${build_dir}/ip]
+set argc 1
+source ${script_path}/gen_ip.tcl
+
+set argv [list ${krnl_name} ${vcs_file} ${tool_dir} ${build_dir}]
+set argc 4
+source ${script_path}/package_kernel.tcl
+
+package_xo -xo_path ${xoname} -kernel_name ${krnl_name} -ip_directory "${build_dir}/xo/packaged_kernel"
--- a/hw/syn/xilinx/xrt/scripts/package_kernel.tcl
+++ b/hw/syn/xilinx/xrt/scripts/package_kernel.tcl
@@ -0,0 +1,268 @@
+# Copyright © 2019-2023
+# 
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+# http://www.apache.org/licenses/LICENSE-2.0
+# 
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+if { $::argc != 4 } {
+    puts "ERROR: Program \"$::argv0\" requires 4 arguments!\n"
+    puts "Usage: $::argv0 <krnl_name> <vcs_file> <tool_dir> <build_dir>\n"
+    exit
+}
+
+set krnl_name [lindex $::argv 0]
+set vcs_file  [lindex $::argv 1]
+set tool_dir  [lindex $::argv 2]
+set build_dir [lindex $::argv 3]
+
+set path_to_packaged "${build_dir}/xo/packaged_kernel"
+set path_to_tmp_project "${build_dir}/xo/project"
+
+source "${tool_dir}/parse_vcs_list.tcl"
+set vlist [parse_vcs_list "${vcs_file}"]
+
+set vsources_list  [lindex $vlist 0]
+set vincludes_list [lindex $vlist 1]
+set vdefines_list  [lindex $vlist 2]
+
+#puts ${vsources_list}
+#puts ${vincludes_list}
+#puts ${vdefines_list}
+
+# find if chipscope is enabled
+set chipscope 0
+foreach def $vdefines_list {
+    set fields [split $def "="]
+    set name [lindex $fields 0]
+    if { $name == "CHIPSCOPE" } {
+        set chipscope 1
+    }
+}
+
+create_project -force kernel_pack $path_to_tmp_project
+
+add_files -norecurse ${vsources_list}
+
+set obj [get_filesets sources_1]
+set files [list \
+ [file normalize "${build_dir}/ip/xil_fdiv/xil_fdiv.xci"] \
+ [file normalize "${build_dir}/ip/xil_fma/xil_fma.xci"] \
+ [file normalize "${build_dir}/ip/xil_fsqrt/xil_fsqrt.xci"] \
+]
+add_files -verbose -norecurse -fileset $obj $files
+
+set_property include_dirs ${vincludes_list} [current_fileset]
+#set_property verilog_define ${vdefines_list} [current_fileset]
+
+set obj [get_filesets sources_1]
+set_property -verbose -name "top" -value ${krnl_name} -objects $obj
+
+if { $chipscope == 1 } {
+    # hw debugging
+    create_ip -name axis_ila -vendor xilinx.com -library ip -version 1.1 -module_name ila_afu
+    set_property -dict [list CONFIG.C_ADV_TRIGGER {true} \
+                             CONFIG.C_EN_STRG_QUAL {1} \
+                             CONFIG.C_DATA_DEPTH {4096} \
+                             CONFIG.C_NUM_OF_PROBES {2} \
+                             CONFIG.C_PROBE0_WIDTH {8} \
+                             CONFIG.C_PROBE1_WIDTH {24} \
+                        ] [get_ips ila_afu]
+    generate_target {instantiation_template} [get_files ila_afu.xci]
+    set_property generate_synth_checkpoint false [get_files ila_afu.xci]
+
+    create_ip -name axis_ila -vendor xilinx.com -library ip -version 1.1 -module_name ila_fetch
+    set_property -dict [list CONFIG.C_ADV_TRIGGER {true} \
+                             CONFIG.C_EN_STRG_QUAL {1} \
+                             CONFIG.C_DATA_DEPTH {4096} \
+                             CONFIG.C_NUM_OF_PROBES {3} \
+                             CONFIG.C_PROBE0_WIDTH {128} \
+                             CONFIG.C_PROBE1_WIDTH {128} \
+                             CONFIG.C_PROBE2_WIDTH {128} \
+                        ] [get_ips ila_fetch]
+    generate_target {instantiation_template} [get_files ila_fetch.xci]
+    set_property generate_synth_checkpoint false [get_files ila_fetch.xci]
+
+    create_ip -name axis_ila -vendor xilinx.com -library ip -version 1.1 -module_name ila_issue
+    set_property -dict [list CONFIG.C_ADV_TRIGGER {true} \
+                             CONFIG.C_EN_STRG_QUAL {1} \
+                             CONFIG.C_DATA_DEPTH {4096} \
+                             CONFIG.C_NUM_OF_PROBES {2} \
+                             CONFIG.C_PROBE0_WIDTH {256} \
+                             CONFIG.C_PROBE1_WIDTH {128} \
+                        ] [get_ips ila_issue]
+    generate_target {instantiation_template} [get_files ila_issue.xci]
+    set_property generate_synth_checkpoint false [get_files ila_issue.xci]
+
+    create_ip -name axis_ila -vendor xilinx.com -library ip -version 1.1 -module_name ila_lsu
+    set_property -dict [list CONFIG.C_ADV_TRIGGER {true} \
+                             CONFIG.C_EN_STRG_QUAL {1} \
+                             CONFIG.C_DATA_DEPTH {4096} \
+                             CONFIG.C_NUM_OF_PROBES {4} \
+                             CONFIG.C_PROBE0_WIDTH {256} \
+                             CONFIG.C_PROBE1_WIDTH {128} \
+                             CONFIG.C_PROBE2_WIDTH {288} \
+                             CONFIG.C_PROBE3_WIDTH {256} \
+                        ] [get_ips ila_lsu]
+    generate_target {instantiation_template} [get_files ila_lsu.xci]
+    set_property generate_synth_checkpoint false [get_files ila_lsu.xci]
+
+    create_ip -name axis_ila -vendor xilinx.com -library ip -version 1.1 -module_name ila_msched
+    set_property -dict [list CONFIG.C_ADV_TRIGGER {true} \
+                             CONFIG.C_EN_STRG_QUAL {1} \
+                             CONFIG.C_DATA_DEPTH {4096} \
+                             CONFIG.C_NUM_OF_PROBES {4} \
+                             CONFIG.C_PROBE0_WIDTH {128} \
+                             CONFIG.C_PROBE1_WIDTH {128} \
+                             CONFIG.C_PROBE2_WIDTH {128} \
+                             CONFIG.C_PROBE3_WIDTH {128} \
+                        ] [get_ips ila_msched]
+    generate_target {instantiation_template} [get_files ila_msched.xci]
+    set_property generate_synth_checkpoint false [get_files ila_msched.xci]
+
+    create_ip -name axis_ila -vendor xilinx.com -library ip -version 1.1 -module_name ila_raster
+    set_property -dict [list CONFIG.C_ADV_TRIGGER {true} \
+                             CONFIG.C_EN_STRG_QUAL {1} \
+                             CONFIG.C_DATA_DEPTH {4096} \
+                             CONFIG.C_NUM_OF_PROBES {2} \
+                             CONFIG.C_PROBE0_WIDTH {128} \
+                             CONFIG.C_PROBE1_WIDTH {128} \
+                        ] [get_ips ila_raster]
+    generate_target {instantiation_template} [get_files ila_raster.xci]
+    set_property generate_synth_checkpoint false [get_files ila_raster.xci]
+}
+
+update_compile_order -fileset sources_1
+update_compile_order -fileset sim_1
+ipx::package_project -root_dir $path_to_packaged -vendor xilinx.com -library RTLKernel -taxonomy /KernelIP -import_files -set_current false
+ipx::unload_core $path_to_packaged/component.xml
+ipx::edit_ip_in_project -upgrade true -name tmp_edit_project -directory $path_to_packaged $path_to_packaged/component.xml
+
+set core [ipx::current_core]
+
+set_property core_revision 2 $core
+foreach up [ipx::get_user_parameters] {
+  ipx::remove_user_parameter [get_property NAME $up] $core
+}
+
+ipx::associate_bus_interfaces -busif s_axi_ctrl -clock ap_clk $core
+
+for {set i 0} {$i < 1} {incr i} {
+    ipx::associate_bus_interfaces -busif m_axi_mem_$i -clock ap_clk $core
+}
+
+set mem_map [::ipx::add_memory_map -quiet "s_axi_ctrl" $core]
+set addr_block [::ipx::add_address_block -quiet "reg0" $mem_map]
+
+set reg [::ipx::add_register "CTRL" $addr_block]
+  set_property description    "Control signals"    $reg
+  set_property address_offset 0x000 $reg
+  set_property size           32    $reg
+
+set field [ipx::add_field AP_START $reg]
+  set_property ACCESS {read-write} $field
+  set_property BIT_OFFSET {0} $field
+  set_property BIT_WIDTH {1} $field
+  set_property DESCRIPTION {Control signal Register for 'ap_start'.} $field
+  set_property MODIFIED_WRITE_VALUE {modify} $field
+
+set field [ipx::add_field AP_DONE $reg]
+  set_property ACCESS {read-only} $field
+  set_property BIT_OFFSET {1} $field
+  set_property BIT_WIDTH {1} $field
+  set_property DESCRIPTION {Control signal Register for 'ap_done'.} $field
+  set_property READ_ACTION {modify} $field
+
+set field [ipx::add_field AP_IDLE $reg]
+  set_property ACCESS {read-only} $field
+  set_property BIT_OFFSET {2} $field
+  set_property BIT_WIDTH {1} $field
+  set_property DESCRIPTION {Control signal Register for 'ap_idle'.} $field
+  set_property READ_ACTION {modify} $field
+
+set field [ipx::add_field AP_READY $reg]
+  set_property ACCESS {read-only} $field
+  set_property BIT_OFFSET {3} $field
+  set_property BIT_WIDTH {1} $field
+  set_property DESCRIPTION {Control signal Register for 'ap_ready'.} $field
+  set_property READ_ACTION {modify} $field
+
+set field [ipx::add_field RESERVED_1 $reg]
+  set_property ACCESS {read-only} $field
+  set_property BIT_OFFSET {4} $field
+  set_property BIT_WIDTH {3} $field
+  set_property DESCRIPTION {Reserved.  0s on read.} $field
+  set_property READ_ACTION {modify} $field
+
+set field [ipx::add_field AUTO_RESTART $reg]
+  set_property ACCESS {read-write} $field
+  set_property BIT_OFFSET {7} $field
+  set_property BIT_WIDTH {1} $field
+  set_property DESCRIPTION {Control signal Register for 'auto_restart'.} $field
+  set_property MODIFIED_WRITE_VALUE {modify} $field
+
+set field [ipx::add_field RESERVED_2 $reg]
+  set_property ACCESS {read-only} $field
+  set_property BIT_OFFSET {8} $field
+  set_property BIT_WIDTH {24} $field
+  set_property DESCRIPTION {Reserved.  0s on read.} $field
+  set_property READ_ACTION {modify} $field
+
+set reg [::ipx::add_register "GIER" $addr_block]
+  set_property description    "Global Interrupt Enable Register"    $reg
+  set_property address_offset 0x004 $reg
+  set_property size           32    $reg
+
+set reg [::ipx::add_register "IP_IER" $addr_block]
+  set_property description    "IP Interrupt Enable Register"    $reg
+  set_property address_offset 0x008 $reg
+  set_property size           32    $reg
+
+set reg [::ipx::add_register "IP_ISR" $addr_block]
+  set_property description    "IP Interrupt Status Register"    $reg
+  set_property address_offset 0x00C $reg
+  set_property size           32    $reg
+
+set reg [::ipx::add_register -quiet "DEV" $addr_block]
+  set_property address_offset 0x010 $reg
+  set_property size           [expr {8*8}]   $reg
+
+set reg [::ipx::add_register -quiet "ISA" $addr_block]
+  set_property address_offset 0x01C $reg
+  set_property size           [expr {8*8}]   $reg
+
+set reg [::ipx::add_register -quiet "DCR" $addr_block]
+  set_property address_offset 0x028 $reg
+  set_property size           [expr {8*8}]   $reg
+
+set reg [::ipx::add_register -quiet "SCP" $addr_block]
+  set_property address_offset 0x034 $reg
+  set_property size           [expr {8*8}]   $reg
+
+for {set i 0} {$i < 1} {incr i} {
+    set reg [::ipx::add_register -quiet "MEM_$i" $addr_block]
+    set_property address_offset [expr {0x040 + $i * 12}] $reg
+    set_property size           [expr {8*8}]   $reg
+    set regparam [::ipx::add_register_parameter -quiet {ASSOCIATED_BUSIF} $reg] 
+    set_property value m_axi_mem_$i $regparam
+}
+
+set_property slave_memory_map_ref "s_axi_ctrl" [::ipx::get_bus_interfaces -of $core "s_axi_ctrl"]
+
+set_property xpm_libraries {XPM_CDC XPM_MEMORY XPM_FIFO} $core
+set_property sdx_kernel true $core
+set_property sdx_kernel_type rtl $core
+set_property supported_families { } $core
+set_property auto_family_support_level level_2 $core
+
+ipx::create_xgui_files $core
+ipx::update_checksums $core
+ipx::check_integrity -kernel $core
+ipx::save_core $core
+close_project -delete
--- a/hw/syn/xilinx/xrt/scripts/xsim.tcl
+++ b/hw/syn/xilinx/xrt/scripts/xsim.tcl
@@ -0,0 +1,25 @@
+#
+# Copyright 2021 Xilinx, Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+#log_wave -r *
+#run all
+#exit
+
+open_vcd xsim_dump.vcd
+log_vcd /*
+run all
+close_vcd
+exit
--- a/hw/syn/xilinx/xrt/vitis.ini
+++ b/hw/syn/xilinx/xrt/vitis.ini
@@ -0,0 +1,9 @@
+[connectivity]
+#nk=vortex_afu:1
+#sp=vortex_afu_1.m_axi_mem_0:HBM[0:15]
+
+[vivado]
+#prop=fileset.sim_1.xsim.elaborate.debug_level=all
+
+[advanced]
+#param=compiler.userPostDebugProfileOverlayTcl=../scripts/post_dbg_profile_overlay.tcl
--- a/hw/syn/xilinx/xrt/xrt.ini
+++ b/hw/syn/xilinx/xrt/xrt.ini
@@ -0,0 +1,11 @@
+[Runtime] 
+runtime_log=console
+
+[Emulation]
+#debug_mode=batch
+#user_pre_sim_script=xsim.tcl
+
+[Debug]
+profile=true
+timeline_trace=true
+data_transfer_trace=fine