Vortex 2.0 changes:

+ Microarchitecture optimizations
+ 64-bit support
+ Xilinx FPGA support
+ LLVM-16 support
+ Refactoring and quality control fixes

hw/syn/altera/quartus/.gitignore

@@ -0,0 +1,41 @@
+/unittest/*
+!/unittest/Makefile
+
+/smem/*
+!/smem/Makefile
+
+/cache/*
+!/cache/Makefile
+
+/vortex/*
+!/vortex/Makefile
+
+/pipeline/*
+!/pipeline/Makefile
+
+/core/*
+!/core/Makefile
+
+/top/*
+!/top/Makefile
+
+/top-gfx/*
+!/top-gfx/Makefile
+
+/test/*
+!/test/Makefile
+
+/fpu/*
+!/fpu/Makefile
+
+/tex/*
+!/tex/Makefile
+
+/rop/*
+!/rop/Makefile
+
+/raster/*
+!/raster/Makefile
+
+/vortex-gfx/*
+!/vortex-gfx/Makefile

hw/syn/altera/quartus/Makefile

@@ -0,0 +1,61 @@
+PREFIX ?= build
+
+BUILD_DIR=$(PREFIX)_$(DEVICE_FAMILY)
+
+IP_CACHE_DIR=../ip_cache/$(DEVICE_FAMILY)
+
+.PHONY: dogfood unittest pipeline smem cache fpu core vortex top test
+
+ip-gen: $(IP_CACHE_DIR)/ip_gen.log
+$(IP_CACHE_DIR)/ip_gen.log:
+	../ip_gen.sh $(IP_CACHE_DIR)
+
+dogfood:
+	mkdir -p dogfood/$(BUILD_DIR)
+	cp dogfood/Makefile dogfood/$(BUILD_DIR)
+	$(MAKE) -C dogfood/$(BUILD_DIR) clean && $(MAKE) -C dogfood/$(BUILD_DIR) > dogfood/$(BUILD_DIR)/build.log 2>&1 &
+
+unittest:
+	mkdir -p unittest/$(BUILD_DIR)
+	cp unittest/Makefile unittest/$(BUILD_DIR)
+	$(MAKE) -C unittest/$(BUILD_DIR) clean && $(MAKE) -C unittest/$(BUILD_DIR) > unittest/$(BUILD_DIR)/build.log 2>&1 &
+
+pipeline:
+	mkdir -p pipeline/$(BUILD_DIR)
+	cp pipeline/Makefile pipeline/$(BUILD_DIR)
+	$(MAKE) -C pipeline/$(BUILD_DIR) clean && $(MAKE) -C pipeline/$(BUILD_DIR) > pipeline/$(BUILD_DIR)/build.log 2>&1 &
+
+smem:
+	mkdir -p smem/$(BUILD_DIR)
+	cp smem/Makefile smem/$(BUILD_DIR)
+	$(MAKE) -C smem/$(BUILD_DIR) clean && $(MAKE) -C smem/$(BUILD_DIR) > smem/$(BUILD_DIR)/build.log 2>&1 &
+
+cache:
+	mkdir -p cache/$(BUILD_DIR)
+	cp cache/Makefile cache/$(BUILD_DIR)
+	$(MAKE) -C cache/$(BUILD_DIR) clean && $(MAKE) -C cache/$(BUILD_DIR) > cache/$(BUILD_DIR)/build.log 2>&1 &
+
+fpu: ip-gen
+	mkdir -p fpu/$(BUILD_DIR)
+	cp fpu/Makefile fpu/$(BUILD_DIR)
+	$(MAKE) -C fpu/$(BUILD_DIR) clean && $(MAKE) -C fpu/$(BUILD_DIR) > fpu/$(BUILD_DIR)/build.log 2>&1 &
+
+core:
+	mkdir -p core/$(BUILD_DIR)
+	cp core/Makefile core/$(BUILD_DIR)
+	$(MAKE) -C core/$(BUILD_DIR) clean && $(MAKE) -C core/$(BUILD_DIR) > core/$(BUILD_DIR)/build.log 2>&1 &
+
+vortex: ip-gen
+	mkdir -p vortex/$(BUILD_DIR)
+	cp vortex/Makefile vortex/$(BUILD_DIR)
+	$(MAKE) -C vortex/$(BUILD_DIR) clean && $(MAKE) -C vortex/$(BUILD_DIR) > vortex/$(BUILD_DIR)/build.log 2>&1 &
+
+top: ip-gen
+	mkdir -p top/$(BUILD_DIR)
+	cp top/Makefile top/$(BUILD_DIR)
+	$(MAKE) -C top/$(BUILD_DIR) clean && $(MAKE) -C top/$(BUILD_DIR) > top/$(BUILD_DIR)/build.log 2>&1 &
+
+test: ip-gen
+	mkdir -p test/$(BUILD_DIR)
+	cp test/Makefile test/$(BUILD_DIR)
+	$(MAKE) -C test/$(BUILD_DIR) clean && $(MAKE) -C test/$(BUILD_DIR) > test/$(BUILD_DIR)/build.log 2>&1 &

hw/syn/altera/quartus/cache/Makefile

@@ -0,0 +1,7 @@
+PROJECT = VX_cache_cluster_top
+TOP_LEVEL_ENTITY = $(PROJECT)
+SRC_FILE = VX_cache_cluster.sv
+
+include ../../common.mk
+
+RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache

hw/syn/altera/quartus/common.mk

@@ -0,0 +1,99 @@
+RTL_DIR = ../../../../../rtl
+AFU_DIR = $(RTL_DIR)/afu/opae
+THIRD_PARTY_DIR = ../../../../../../third_party
+IP_CACHE_DIR = ../../../ip_cache/$(DEVICE_FAMILY)
+SCRIPT_DIR = ../../../../../scripts
+THIRD_PARTY_DIR = ../../../../../../third_party
+
+ifeq ($(DEVICE_FAMILY), stratix10)
+    FAMILY = "Stratix 10"
+	DEVICE = 1SX280HN2F43E2VG
+endif
+ifeq ($(DEVICE_FAMILY), arria10)
+    FAMILY = "Arria 10"
+	DEVICE = 10AX115N3F40E2SG
+endif
+
+CONFIGS += -DNDEBUG
+CONFIGS += -DQUARTUS
+CONFIGS += -DSYNTHESIS
+CONFIGS += -DNOGLOBALS
+
+PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
+
+# Executable Configuration
+SYN_ARGS = --parallel --read_settings_files=on
+FIT_ARGS = --parallel --part=$(DEVICE) --read_settings_files=on
+ASM_ARGS =
+STA_ARGS = --parallel --do_report_timing
+POW_ARGS = --no_input_file --default_input_io_toggle_rate=60% --default_toggle_rate=20% --use_vectorless_estimation=off
+
+# Build targets
+all: gen-sources $(PROJECT).sta.rpt $(PROJECT).pow.rpt
+
+gen-sources: src
+src:
+	mkdir -p src
+	$(SCRIPT_DIR)/gen_sources.sh $(CONFIGS) $(RTL_INCLUDE) -P -Csrc
+
+syn: $(PROJECT).syn.rpt
+
+fit: $(PROJECT).fit.rpt
+
+asm: $(PROJECT).asm.rpt
+
+sta: $(PROJECT).sta.rpt
+
+pow: $(PROJECT).pow.rpt
+
+smart: smart.log
+
+# Target implementations
+STAMP = echo done >
+
+$(PROJECT).syn.rpt: smart.log syn.chg
+	quartus_syn $(SYN_ARGS) $(PROJECT)
+	$(STAMP) fit.chg
+
+$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt
+	quartus_fit $(FIT_ARGS) $(PROJECT)
+	$(STAMP) asm.chg
+	$(STAMP) sta.chg
+
+$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt
+	quartus_asm $(ASM_ARGS) $(PROJECT)
+	$(STAMP) pow.chg
+
+$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt
+	quartus_sta $(STA_ARGS) $(PROJECT)
+
+$(PROJECT).pow.rpt: smart.log pow.chg $(PROJECT).asm.rpt
+	quartus_pow $(POW_ARGS) $(PROJECT)
+
+smart.log: $(PROJECT_FILES)
+	quartus_sh --determine_smart_action $(PROJECT) > smart.log
+
+# Project initialization
+$(PROJECT_FILES): gen-sources
+	quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "src"
+	
+syn.chg:
+	$(STAMP) syn.chg
+
+fit.chg:
+	$(STAMP) fit.chg
+
+sta.chg:
+	$(STAMP) sta.chg
+
+asm.chg:
+	$(STAMP) asm.chg
+
+pow.chg:
+	$(STAMP) pow.chg
+
+program: $(PROJECT).sof
+	quartus_pgm --no_banner --mode=jtag -o "$(PROJECT).sof"
+	
+clean:
+	rm -rf src bin *.rpt *.chg *.qsf *.qpf *.qws *.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox

hw/syn/altera/quartus/core/Makefile

@@ -0,0 +1,14 @@
+PROJECT = VX_core_top
+TOP_LEVEL_ENTITY = $(PROJECT)
+SRC_FILE = VX_core.sv
+
+include ../../common.mk
+
+#CONFIGS += -DNUM_WARPS=32
+#CONFIGS += -DNUM_THREADS=32
+
+FPU_INCLUDE = -I$(RTL_DIR)/fpu
+ifneq (,$(findstring FPU_FPNEW,$(CONFIGS)))
+	FPU_INCLUDE += -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -J$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/fpnew/src
+endif
+RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache -I$(IP_CACHE_DIR) $(FPU_INCLUDE)

hw/syn/altera/quartus/fpu/Makefile

@@ -0,0 +1,11 @@
+PROJECT = VX_fpu_dsp
+TOP_LEVEL_ENTITY = $(PROJECT)
+SRC_FILE = $(PROJECT).sv
+
+include ../../common.mk
+
+FPU_INCLUDE = -I$(RTL_DIR)/fpu
+ifneq (,$(findstring FPU_FPNEW,$(CONFIGS)))
+	FPU_INCLUDE += -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -J$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/fpnew/src
+endif
+RTL_INCLUDE = $(FPU_INCLUDE) -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(IP_CACHE_DIR)

hw/syn/altera/quartus/project.sdc

@@ -0,0 +1 @@
+create_clock -name {clk} -period "200 MHz" -waveform { 0.000 1.0 } [get_ports {clk}]

hw/syn/altera/quartus/project.tcl

@@ -0,0 +1,104 @@
+# Copyright © 2019-2023
+# 
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+# http://www.apache.org/licenses/LICENSE-2.0
+# 
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+load_package flow
+package require cmdline
+
+set options { 
+    { "project.arg" "" "Project name" } 
+    { "family.arg" "" "Device family name" } 
+    { "device.arg" "" "Device name" } 
+    { "top.arg" "" "Top level module" }     
+    { "src.arg" "" "Verilog source file" } 
+    { "inc.arg" "" "Include path (optional)" } 
+    { "sdc.arg" "" "Timing Design Constraints file (optional)" } 
+    { "set.arg" "" "Macro value (optional)" } 
+}
+
+set q_args_orig $quartus(args)
+
+array set opts [::cmdline::getoptions quartus(args) $options]
+
+# Verify required parameters
+set requiredParameters {project family device top src}
+foreach p $requiredParameters {
+    if {$opts($p) == ""} {
+        puts stderr "Missing required parameter: -$p"
+        exit 1
+    }
+}
+
+project_new $opts(project) -overwrite
+
+set_global_assignment -name FAMILY $opts(family)
+set_global_assignment -name DEVICE $opts(device)
+set_global_assignment -name TOP_LEVEL_ENTITY $opts(top)
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY bin
+
+set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
+set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009
+set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS ON
+set_global_assignment -name MESSAGE_DISABLE 16818
+set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
+
+set_global_assignment -name SEED 1
+
+switch $opts(family) {
+    "Arria 10" {
+        set_global_assignment -name VERILOG_MACRO ALTERA_A10    
+    }
+    "Stratix 10" {
+        set_global_assignment -name VERILOG_MACRO ALTERA_S10    
+    }
+    default {
+        puts stderr "Invalid device family"
+        exit 1
+    }
+}
+
+set idx 0
+foreach arg $q_args_orig {
+    incr idx
+    if [string match "-src" $arg] {
+        set_global_assignment -name VERILOG_FILE [lindex $q_args_orig $idx]
+    }
+    if [string match "-inc" $arg] {
+        set_global_assignment -name SEARCH_PATH [lindex $q_args_orig $idx]
+    }
+    if [string match "-sdc" $arg] {
+        set_global_assignment -name SDC_FILE [lindex $q_args_orig $idx]
+    }
+    if [string match "-set" $arg] {
+        set_global_assignment -name VERILOG_MACRO [lindex $q_args_orig $idx]
+    }
+}
+
+proc make_all_pins_virtual {} {
+    execute_module -tool map
+    set excludes { clk }
+    set name_ids [get_names -filter * -node_type pin]
+    foreach_in_collection name_id $name_ids {        
+        set pin_name [get_name_info -info full_path $name_id]
+        if { [lsearch -exact -nocase $excludes $pin_name] >= 0 } {
+            post_message "Skipping VIRTUAL_PIN assignment to $pin_name"
+        } else {
+            post_message "Making VIRTUAL_PIN assignment to $pin_name"
+            set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON
+        }
+    }
+    export_assignments
+}
+
+make_all_pins_virtual
+
+project_close

hw/syn/altera/quartus/smem/Makefile

@@ -0,0 +1,7 @@
+PROJECT = VX_shared_mem
+TOP_LEVEL_ENTITY = $(PROJECT)
+SRC_FILE = $(PROJECT).sv
+
+include ../../common.mk
+
+RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/mem

hw/syn/altera/quartus/test/Makefile

@@ -0,0 +1,11 @@
+PROJECT = Vortex
+TOP_LEVEL_ENTITY = $(PROJECT)
+SRC_FILE = $(PROJECT).sv
+
+include ../../common.mk
+
+FPU_INCLUDE = -I$(RTL_DIR)/fpu
+ifneq (,$(findstring FPU_FPNEW,$(CONFIGS)))
+	FPU_INCLUDE += -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -J$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/fpnew/src
+endif
+RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache -I$(IP_CACHE_DIR) $(FPU_INCLUDE)

hw/syn/altera/quartus/timing-html.tcl

@@ -0,0 +1,53 @@
+# Copyright © 2019-2023
+# 
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+# http://www.apache.org/licenses/LICENSE-2.0
+# 
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+package require cmdline
+
+set options { 
+    { "project.arg" "" "Project name" }
+    { "outdir.arg" "timing-html" "Output directory" } 
+}
+
+array set opts [::cmdline::getoptions quartus(args) $options]
+
+# Verify required parameters
+set requiredParameters {project}
+foreach p $requiredParameters {
+    if {$opts($p) == ""} {
+        puts stderr "Missing required parameter: -$p"
+        exit 1
+    }
+}
+
+project_open $opts(project)
+
+set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
+
+create_timing_netlist
+read_sdc
+update_timing_netlist
+
+foreach_in_collection op [get_available_operating_conditions] {
+  set_operating_conditions $op
+
+  report_timing -setup -npaths 150 -detail full_path -multi_corner -pairs_only -nworst 8 \
+    -file "$opts(outdir)/timing_paths_$op.html" \
+    -panel_name "Critical paths for $op"
+
+  create_slack_histogram -num_bins 50 -clock clk -multi_corner -file "$opts(outdir)/slack_histogram_$op.html"
+}
+
+
+
+
+

hw/syn/altera/quartus/top/Makefile

@@ -0,0 +1,18 @@
+PROJECT = vortex_afu
+TOP_LEVEL_ENTITY = $(PROJECT)
+SRC_FILE = $(PROJECT).sv
+
+include ../../common.mk
+
+CONFIGS += -DNOPAE
+
+#CONFIGS += -DNUM_CORES=2
+#CONFIGS += -DNUM_WARPS=32
+#CONFIGS += -DNUM_THREADS=32
+#CONFIGS += -DL2_ENABLE
+
+FPU_INCLUDE = -I$(RTL_DIR)/fpu
+ifneq (,$(findstring FPU_FPNEW,$(CONFIGS)))
+	FPU_INCLUDE += -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -J$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/fpnew/src
+endif
+RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache -I$(AFU_DIR) -I$(AFU_DIR)/ccip -I$(IP_CACHE_DIR) $(FPU_INCLUDE)

hw/syn/altera/quartus/unittest/Makefile

@@ -0,0 +1,11 @@
+PROJECT = Unittest
+TOP_LEVEL_ENTITY = $(PROJECT)
+SRC_FILE = $(PROJECT).sv
+
+include ../../common.mk
+
+FPU_INCLUDE = -I$(RTL_DIR)/fpu
+ifneq (,$(findstring FPU_FPNEW,$(CONFIGS)))
+	FPU_INCLUDE += -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -J$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/fpnew/src
+endif
+RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache -I$(IP_CACHE_DIR) $(FPU_INCLUDE)

hw/syn/altera/quartus/vortex/Makefile

@@ -0,0 +1,16 @@
+PROJECT = Vortex
+TOP_LEVEL_ENTITY = $(PROJECT)
+SRC_FILE = $(PROJECT).sv
+
+include ../../common.mk
+
+#CONFIGS += -DNUM_CORES=2
+#CONFIGS += -DNUM_WARPS=32
+#CONFIGS += -DNUM_THREADS=32
+#CONFIGS += -DL2_ENABLE
+
+FPU_INCLUDE = -I$(RTL_DIR)/fpu
+ifneq (,$(findstring FPU_FPNEW,$(CONFIGS)))
+	FPU_INCLUDE += -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -J$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/fpnew/src
+endif
+RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache -I$(IP_CACHE_DIR) $(FPU_INCLUDE)