Vortex 2.0 changes:
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
This commit is contained in:
Blaise Tine
152
hw/syn/altera/opae/Makefile
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152
hw/syn/altera/opae/Makefile
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DEVICE_FAMILY ?= arria10
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XLEN ?= 32
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PREFIX ?= build$(XLEN)
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TARGET ?= fpga
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NUM_CORES ?= 1
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SCRIPT_DIR = ../../../scripts
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RTL_DIR = ../../../rtl
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DPI_DIR = ../../../dpi
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AFU_DIR = $(RTL_DIR)/afu/opae
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THIRD_PARTY_DIR = ../../../../third_party
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IP_CACHE_DIR = ../ip_cache/$(DEVICE_FAMILY)
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BUILD_DIR = $(PREFIX)_$(DEVICE_FAMILY)_$(TARGET)_$(NUM_CORES)c
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ifeq ($(shell which qsub-synth),)
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RUN_SYNTH=$(OPAE_PLATFORM_ROOT)/bin/run.sh > build.log 2>&1 &
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else
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RUN_SYNTH=qsub-synth
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endif
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# control RTL debug tracing states
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DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_PIPELINE
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DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_ICACHE
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DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_DCACHE
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DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_MEM
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DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_BANK
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DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_MSHR
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DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_TAG
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DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_DATA
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DBG_TRACE_FLAGS += -DDBG_TRACE_AFU
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DBG_TRACE_FLAGS += -DDBG_TRACE_TEX
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DBG_TRACE_FLAGS += -DDBG_TRACE_RASTER
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DBG_TRACE_FLAGS += -DDBG_TRACE_ROP
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DBG_TRACE_FLAGS += -DDBG_TRACE_GBAR
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# Control logic analyzer monitors
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DBG_SCOPE_FLAGS += -DDBG_SCOPE_AFU
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DBG_SCOPE_FLAGS += -DDBG_SCOPE_ISSUE
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DBG_SCOPE_FLAGS += -DDBG_SCOPE_FETCH
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DBG_SCOPE_FLAGS += -DDBG_SCOPE_LSU
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DBG_SCOPE_FLAGS += -DDBG_SCOPE_RASTER
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DBG_SCOPE_FLAGS += -DDBG_SCOPE_MSCHED
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ifeq ($(DEVICE_FAMILY), stratix10)
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CONFIGS += -DALTERA_S10
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endif
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ifeq ($(DEVICE_FAMILY), arria10)
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CONFIGS += -DALTERA_A10
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endif
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# cluster configuration
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CONFIGS_1c := -DNUM_CLUSTERS=1 -DNUM_CORES=1
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CONFIGS_2c := -DNUM_CLUSTERS=1 -DNUM_CORES=2
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CONFIGS_4c := -DNUM_CLUSTERS=1 -DNUM_CORES=4
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CONFIGS_8c := -DNUM_CLUSTERS=1 -DNUM_CORES=8
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CONFIGS_16c := -DNUM_CLUSTERS=1 -DNUM_CORES=16 -DL2_ENABLE
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CONFIGS_32c := -DNUM_CLUSTERS=2 -DNUM_CORES=16 -DL2_ENABLE
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CONFIGS_64c := -DNUM_CLUSTERS=4 -DNUM_CORES=16 -DL2_ENABLE
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CONFIGS += $(CONFIGS_$(NUM_CORES)c)
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# include paths
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FPU_INCLUDE = -I$(RTL_DIR)/fpu
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ifneq (,$(findstring FPU_FPNEW,$(CONFIGS)))
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FPU_INCLUDE += -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -J$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/fpnew/src
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endif
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RTL_INCLUDE = -I$(RTL_DIR) -I$(DPI_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache -I$(AFU_DIR) -I$(IP_CACHE_DIR)
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RTL_INCLUDE += $(FPU_INCLUDE)
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# compilation flags
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CFLAGS += -DSYNTHESIS -DQUARTUS
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CFLAGS += -DXLEN_$(XLEN)
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CFLAGS += $(CONFIGS)
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CFLAGS += $(RTL_INCLUDE)
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ifneq ($(TARGET), fpga)
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CFLAGS += -DSIMULATION
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endif
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# Debugigng
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ifdef DEBUG
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ifeq ($(TARGET), fpga)
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CFLAGS += -DNDEBUG -DSCOPE $(DBG_SCOPE_FLAGS)
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SCOPE_JSON += $(BUILD_DIR)/scope.json
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else
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CFLAGS += $(DBG_TRACE_FLAGS)
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endif
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else
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CFLAGS += -DNDEBUG
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endif
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# Enable scope analyzer
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ifdef SCOPE
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CFLAGS += -DSCOPE
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endif
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# Enable perf counters
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ifdef PERF
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CFLAGS += -DPERF_ENABLE
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endif
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# ast dump flags
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XML_CFLAGS = $(filter-out -DSYNTHESIS -DQUARTUS, $(CFLAGS)) -I$(AFU_DIR)/ccip -I$(DPI_DIR) -DNOPAE
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all: swconfig ip-gen setup build
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ip-gen: $(IP_CACHE_DIR)/ip-gen.log
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$(IP_CACHE_DIR)/ip-gen.log:
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../ip_gen.sh $(IP_CACHE_DIR)
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swconfig: vortex_afu.h
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vortex_afu.h: vortex_afu.json
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afu_json_mgr json-info --afu-json=$^ --c-hdr=$@
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$(BUILD_DIR)/setup.cfg:
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mkdir -p $(BUILD_DIR); cp setup.cfg $(BUILD_DIR)/setup.cfg
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$(BUILD_DIR)/vortex_afu.qsf:
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mkdir -p $(BUILD_DIR); cp vortex_afu.qsf $(BUILD_DIR)/vortex_afu.qsf
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$(BUILD_DIR)/vortex_afu.json:
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mkdir -p $(BUILD_DIR); cp vortex_afu.json $(BUILD_DIR)/vortex_afu.json
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gen-sources: $(BUILD_DIR)/sources.txt
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$(BUILD_DIR)/sources.txt:
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mkdir -p $(BUILD_DIR); $(SCRIPT_DIR)/gen_sources.sh $(CFLAGS) -C$(BUILD_DIR)/src -O$(BUILD_DIR)/sources.txt
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setup: $(BUILD_DIR)/synth
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$(BUILD_DIR)/synth: $(BUILD_DIR)/sources.txt $(BUILD_DIR)/setup.cfg $(BUILD_DIR)/vortex_afu.qsf $(BUILD_DIR)/vortex_afu.json
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ifeq ($(TARGET), asesim)
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afu_sim_setup -s $(BUILD_DIR)/setup.cfg $(BUILD_DIR)/synth
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else
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afu_synth_setup -s $(BUILD_DIR)/setup.cfg $(BUILD_DIR)/synth
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endif
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build: ip-gen setup $(SCOPE_JSON)
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ifeq ($(TARGET), asesim)
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make -C $(BUILD_DIR)/synth > $(BUILD_DIR)/synth/build.log 2>&1 &
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else
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cd $(BUILD_DIR)/synth && $(RUN_SYNTH)
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endif
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gen-ast: $(BUILD_DIR)/vortex.xml
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$(BUILD_DIR)/vortex.xml: setup
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verilator --xml-only -O0 $(XML_CFLAGS) vortex_afu.sv --xml-output $(BUILD_DIR)/vortex.xml
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scope-json: $(BUILD_DIR)/scope.json
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$(BUILD_DIR)/scope.json: $(BUILD_DIR)/vortex.xml
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$(SCRIPT_DIR)/scope.py $(BUILD_DIR)/vortex.xml -o $(BUILD_DIR)/scope.json
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clean:
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rm -rf vortex_afu.h $(BUILD_DIR)
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