Vortex 2.0 changes:
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
This commit is contained in:
Blaise Tine
1
hw/syn/altera/.gitignore
vendored
Normal file
1
hw/syn/altera/.gitignore
vendored
Normal file
@@ -0,0 +1 @@
|
||||
ip_cache/*
|
||||
106
hw/syn/altera/NOTEBOOK
Normal file
106
hw/syn/altera/NOTEBOOK
Normal file
@@ -0,0 +1,106 @@
|
||||
## Altera synthesis Notebook
|
||||
|
||||
## To configure quartus and opae. Run this after logging in.
|
||||
source /export/fpga/bin/setup-fpga-env fpga-pac-a10
|
||||
|
||||
# Configure a Quartus build area
|
||||
afu_synth_setup -s sources.txt build_fpga
|
||||
|
||||
# Run Quartus in the vLab batch queue
|
||||
cd build_fpga && qsub-synth
|
||||
|
||||
# check last 10 lines in build log for possible errors
|
||||
tail -n 10 ./build_arria10_fpga_1c/build.log
|
||||
|
||||
# Check if the job is submitted to the queue and running. Status should be R
|
||||
qstat | grep <user>
|
||||
|
||||
# Constantly monitoring the job submitted to the queue. Stop this using Ctrl+C
|
||||
watch ‘qstat | grep <user>’
|
||||
|
||||
#
|
||||
## Executing on FPGA
|
||||
#
|
||||
|
||||
# From the build_fpga directory acquire a fpga node
|
||||
qsub-fpga
|
||||
|
||||
# Go to the directory whree qsub-synth was run above
|
||||
cd $PBS_O_WORKDIR
|
||||
|
||||
# Load the image onto an FPGA
|
||||
fpgaconf <build>/synth/vortex_afu.gbs
|
||||
|
||||
# If this says Multiple ports. Then use --bus with fpgaconf. #bus info can be found by fpgainfo port
|
||||
fpgaconf --bus 0xaf <build>/synth/vortex_afu.gbs
|
||||
|
||||
# get portid
|
||||
fpgainfo port
|
||||
|
||||
# Running the Test case
|
||||
cd /driver/tests/basic
|
||||
make run-fpga
|
||||
|
||||
#
|
||||
## ASE build instructions
|
||||
#
|
||||
source /export/fpga/bin/setup-fpga-env fpga-pac-a10
|
||||
|
||||
# Acquire a sever node for running ASE simulations
|
||||
qsub-sim
|
||||
|
||||
# build ASE runtime
|
||||
TARGET=asesim make -C runtime/opae
|
||||
|
||||
# build ASE hw image
|
||||
PREFIX=build_base CONFIGS="-DEXT_F_DISABLE -DL1_DISABLE -DSM_DISABLE -DNUM_WARPS=2 -DNUM_THREADS=2" TARGET=asesim make
|
||||
PREFIX=build_gfx CONFIGS="-DEXT_GFX_ENABLE -DTCACHE_DISABLE -DRCACHE_DISABLE -DOCACHE_DISABLE -DEXT_F_DISABLE -DL1_DISABLE -DSM_DISABLE -DNUM_WARPS=2 -DNUM_THREADS=2" TARGET=asesim make
|
||||
|
||||
# ASE test runs
|
||||
./run_ase.sh build_base_arria10_asesim_1c/synth ../../../../tests/regression/basic/basic -n1 -t0
|
||||
./run_ase.sh build_base_arria10_asesim_1c/synth ../../../../tests/regression/basic/basic -n1 -t1
|
||||
./run_ase.sh build_base_arria10_asesim_1c/synth ../../../../tests/regression/basic/basic -n16
|
||||
./run_ase.sh build_base_arria10_asesim_1c/synth ../../../../tests/regression/demo/demo -n16
|
||||
./run_ase.sh build_base_arria10_asesim_1c/synth ../../../../tests/regression/dogfood/dogfood -n16
|
||||
./run_ase.sh build_base_arria10_asesim_1c/synth ../../../../tests/opencl/vecadd/vecadd
|
||||
./run_ase.sh build_base_arria10_asesim_1c/synth ../../../../tests/opencl/sgemm/sgemm -n4
|
||||
./run_ase.sh build_gfx_arria10_asesim_1c/synth ../../../../tests/regression/tex/tex
|
||||
./run_ase.sh build_gfx_arria10_asesim_1c/synth ../../../../tests/regression/rop/rop -w8 -h8
|
||||
./run_ase.sh build_gfx_arria10_asesim_1c/synth ../../../../tests/regression/raster/raster -w8 -h8
|
||||
./run_ase.sh build_gfx_arria10_asesim_1c/synth ../../../../tests/regression/draw3d/draw3d -w8 -h8
|
||||
|
||||
# modify "vsim_run.tcl" to dump VCD trace
|
||||
vcd file trace.vcd
|
||||
vcd add -r /*/Vortex/hw/rtl/*
|
||||
run -all
|
||||
|
||||
# compress FPGA output files
|
||||
tar -zcvf output_files_1c.tar.gz `find ./build_fpga_1c -type f \( -iname \*.rpt -o -iname \*.txt -o -iname \*summary -o -iname \*.log \)`
|
||||
|
||||
# compress log trace
|
||||
tar -zcvf run.log.tar.gz run.log
|
||||
tar -cvjf trace.vcd.tar.bz2 trace.vcd run.log
|
||||
tar -cvjf trace.vcd.tar.bz2 build_arria10_ase_1c/synth/work/run.log build_arria10_ase_1c/work/trace.vcd
|
||||
|
||||
# decompress log trace
|
||||
tar -zxvf vortex.vcd.tar.gz
|
||||
tar -xvf vortex.vcd.tar.bz2
|
||||
|
||||
# building FPGA images
|
||||
make all
|
||||
PREFIX=build_gfx NUM_CORES=2 CONFIGS="-DEXT_GFX_ENABLE" make
|
||||
|
||||
# building gfx test on systems with custom boost directory
|
||||
LDFLAGS += -L/homes/tinebp/tools/boost/lib
|
||||
|
||||
# running benchmarks on FPGA
|
||||
fpgaconf --bus 0xaf <build>/synth/vortex_afu.gbs
|
||||
TARGET=fpga ./ci/blackbox.sh --driver=opae --app=sgemm
|
||||
TARGET=fpga ./ci/blackbox.sh --driver=opae --app=draw3d --args="-w512 -h512 -tvase.cgltrace"
|
||||
|
||||
# quick off synthesis
|
||||
make core
|
||||
|
||||
# generate reports
|
||||
./report_timing.sh <project_dir> <project_name>
|
||||
./report_area.sh <project_dir> <project_name>
|
||||
17
hw/syn/altera/analyze_timing.sh
Executable file
17
hw/syn/altera/analyze_timing.sh
Executable file
@@ -0,0 +1,17 @@
|
||||
#!/bin/bash
|
||||
|
||||
# Timing Analysis
|
||||
# first argument is the project name
|
||||
|
||||
SCRIPT_DIR="$(dirname "${BASH_SOURCE[0]}")"
|
||||
SCRIPT_DIR="$(realpath "${SCRIPT_DIR}")"
|
||||
|
||||
PROJECT_DIR=$1
|
||||
PROJECT=$2
|
||||
MODE=${3-fit}
|
||||
|
||||
echo "Running quartus_sh -t $SCRIPT_DIR/report_area.tcl $PROJECT $MODE in $PROJECT_DIR ..."
|
||||
|
||||
pushd $PROJECT_DIR
|
||||
quartus_sta -t $SCRIPT_DIR/analyze_timing.tcl $PROJECT $MODE
|
||||
popd
|
||||
145
hw/syn/altera/analyze_timing.tcl
Normal file
145
hw/syn/altera/analyze_timing.tcl
Normal file
@@ -0,0 +1,145 @@
|
||||
# Copyright © 2019-2023
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
set ProjectName [lindex $argv 0]
|
||||
set SynMode [lindex $argv 1]
|
||||
if { $SynMode == "map" } {
|
||||
set FileSuffix "map"
|
||||
} else {
|
||||
set FileSuffix "fit"
|
||||
}
|
||||
|
||||
proc do_timing_checks { ProjectName FileSuffix } {
|
||||
# Validate timing DRC rules
|
||||
# REF: http://quartushelp.altera.com/14.0/mergedProjects/tafs/tafs/tcl_pkg_sta_ver_1.0_cmd_check_timing.htm
|
||||
check_timing -include {no_clock multiple_clock loops latches } -file $ProjectName.$FileSuffix.timing.check_errors.html
|
||||
# NOTE: metastability requires QSF setting of Synchronizer Identification = Auto
|
||||
# can also embed in Verilog: (* altera_attribute = "-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS" *)
|
||||
report_metastability -nchains 100 -file $ProjectName.$FileSuffix.timing.check_metastability.html
|
||||
}
|
||||
|
||||
proc do_timing_detailed_slackpaths { ProjectName FileSuffix SynMode } {
|
||||
# Detailed info for top 100 setup/hold paths
|
||||
if { $SynMode == "fit" } {
|
||||
set npaths_detailed 200
|
||||
set npaths_pairs 10000
|
||||
set npaths_maxslack 0.2
|
||||
# Create html reports showing details of each of the top 100 paths (creates html index + subdir with css/images/etc)
|
||||
set ExtraRTArgs "-show_routing"
|
||||
report_timing -setup -nworst $npaths_detailed -detail full_path $ExtraRTArgs -file $ProjectName.$FileSuffix.timing.setup.html
|
||||
report_timing -hold -nworst $npaths_detailed -detail full_path $ExtraRTArgs -file $ProjectName.$FileSuffix.timing.hold.html
|
||||
report_timing -recovery -nworst $npaths_detailed -detail full_path $ExtraRTArgs -file $ProjectName.$FileSuffix.timing.recovery.html
|
||||
report_timing -removal -nworst $npaths_detailed -detail full_path $ExtraRTArgs -file $ProjectName.$FileSuffix.timing.removal.html
|
||||
|
||||
# Create txt with (slack,src,dst) for cross-seed comparisons
|
||||
report_timing -setup -nworst $npaths_pairs -less_than_slack $npaths_maxslack -detail summary -pairs_only -file $ProjectName.$FileSuffix.timing_paths.setup.txt
|
||||
report_timing -hold -nworst $npaths_pairs -less_than_slack $npaths_maxslack -detail summary -pairs_only -file $ProjectName.$FileSuffix.timing_paths.hold.txt
|
||||
report_timing -recovery -nworst $npaths_pairs -less_than_slack $npaths_maxslack -detail summary -pairs_only -file $ProjectName.$FileSuffix.timing_paths.recovery.txt
|
||||
report_timing -removal -nworst $npaths_pairs -less_than_slack $npaths_maxslack -detail summary -pairs_only -file $ProjectName.$FileSuffix.timing_paths.removal.txt
|
||||
|
||||
# Histogram of setup/hold slacks across all clocks
|
||||
set allclocks [get_clocks]
|
||||
foreach_in_collection curclk $allclocks {
|
||||
set clkname [ get_clock_info -name $curclk ]
|
||||
create_slack_histogram -clock_name $clkname -setup -file $ProjectName.$FileSuffix.timing_histogram.$clkname.setup.html
|
||||
#create_slack_histogram -clock_name $clkname -hold -file $ProjectName.$FileSuffix.timing_histogram.$clkname.hold.html
|
||||
}
|
||||
# Just emit simple setup paths if analyzing MAP netlist
|
||||
} else {
|
||||
set ExtraRTArgs ""
|
||||
report_timing -setup -nworst 100 -detail full_path $ExtraRTArgs -file $ProjectName.$FileSuffix.timing.setup.html
|
||||
}
|
||||
}
|
||||
|
||||
proc do_timing_summary { ProjectName FileSuffix } {
|
||||
# Save summary into to single txt file
|
||||
create_timing_summary -setup -file $ProjectName.$FileSuffix.timing.summary.txt
|
||||
create_timing_summary -hold -append -file $ProjectName.$FileSuffix.timing.summary.txt
|
||||
report_clocks -summary -append -file $ProjectName.$FileSuffix.timing.summary.txt
|
||||
report_clock_fmax_summary -append -file $ProjectName.$FileSuffix.timing.summary.txt
|
||||
}
|
||||
|
||||
proc do_timing_detailed_bottleneck_paths { ProjectName FileSuffix } {
|
||||
# Create bottleneck timing analysis with different metrics to analyze setup paths
|
||||
#proc custom_metric_fanins {arg} {
|
||||
# upvar $arg metric
|
||||
# set rating $metric(num_fanins)
|
||||
# return $rating
|
||||
#}
|
||||
#report_bottleneck -cmetric custom_metric_fanins -file timing.bottlneck.num_fanins.html $tpaths
|
||||
set tpaths [ get_timing_paths -nworst 1000 -setup ]
|
||||
set tns_paths [ report_bottleneck -metric tns $tpaths -stdout ]
|
||||
set np_paths [ report_bottleneck -metric num_paths $tpaths -stdout ]
|
||||
set nfp_paths [ report_bottleneck -metric num_fpaths $tpaths -stdout ]
|
||||
set nfo_paths [ report_bottleneck -metric num_fanouts $tpaths -stdout ]
|
||||
set nfi_paths [ report_bottleneck -metric num_fanins $tpaths -stdout ]
|
||||
|
||||
set fo [ open "$ProjectName.$FileSuffix.timing.setup.bottlenecks.txt" "w" ]
|
||||
puts $fo "Bottlenecks by TNS"
|
||||
puts $fo $tns_paths
|
||||
|
||||
puts $fo "Bottlenecks by NumPaths"
|
||||
puts $fo $np_paths
|
||||
|
||||
puts $fo "Bottlenecks by NumFailingPaths"
|
||||
puts $fo $nfp_paths
|
||||
|
||||
puts $fo "Bottlenecks by NumFanOuts"
|
||||
puts $fo $nfo_paths
|
||||
|
||||
puts $fo "Bottlenecks by NumFanIns"
|
||||
puts $fo $nfi_paths
|
||||
}
|
||||
|
||||
# Iterate over all known operating conditions
|
||||
# 3_H2_slow_850mv_100c / 3_H2_slow_850mv_100c / 3_H2_slow_850mv_0c / MIN_fast_850mv_100c / MIN_fast_850mv_0c
|
||||
#foreach_in_collection oc [get_available_operating_conditions] {
|
||||
# set_operating_conditions $oc
|
||||
# post_message "Setting Operating Conditions $oc"
|
||||
# update_timing_netlist
|
||||
# report_timing -setup -npaths 100 -file $ProjectName.timing.setup.html
|
||||
# report_timing -hold -npaths 100 -file $ProjectName.timing.hold.html
|
||||
#}
|
||||
|
||||
project_open $ProjectName
|
||||
|
||||
# => allows comparison of raw logic vs impact of routing delays
|
||||
if { $SynMode == "map" } {
|
||||
create_timing_netlist -post_map
|
||||
read_sdc
|
||||
update_timing_netlist
|
||||
|
||||
do_timing_detailed_slackpaths $ProjectName $FileSuffix $SynMode
|
||||
do_timing_summary $ProjectName $FileSuffix
|
||||
|
||||
delete_timing_netlist
|
||||
|
||||
# normal post-par analysis (includes routing congestion/physical placement constraints)
|
||||
} else {
|
||||
create_timing_netlist
|
||||
read_sdc
|
||||
update_timing_netlist
|
||||
|
||||
# Iterate over a single worst-case operating condition (grade/speed pre-selected based on netlist)
|
||||
set_operating_conditions -voltage 900 -temperature 100
|
||||
update_timing_netlist
|
||||
|
||||
do_timing_checks $ProjectName $FileSuffix
|
||||
do_timing_detailed_slackpaths $ProjectName $FileSuffix $SynMode
|
||||
do_timing_detailed_bottleneck_paths $ProjectName $FileSuffix
|
||||
do_timing_summary $ProjectName $FileSuffix
|
||||
|
||||
delete_timing_netlist
|
||||
}
|
||||
|
||||
project_close
|
||||
50
hw/syn/altera/ip_gen.sh
Executable file
50
hw/syn/altera/ip_gen.sh
Executable file
@@ -0,0 +1,50 @@
|
||||
#!/bin/bash
|
||||
|
||||
# Copyright © 2019-2023
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
|
||||
BUILD_DIR=$1
|
||||
|
||||
EXP_BITS=8
|
||||
MAN_BITS=23
|
||||
FBITS="f$(($EXP_BITS + $MAN_BITS + 1))"
|
||||
|
||||
CMD_POLY_EVAL_PATH=$QUARTUS_HOME/dspba/backend/linux64
|
||||
|
||||
OPTIONS="-target $DEVICE_FAMILY -noChanValid -enable -enableHardFP 1 -faithfulRounding -speedgrade 2 -frequency 200 -lang verilog -printMachineReadable"
|
||||
|
||||
export LD_LIBRARY_PATH=$CMD_POLY_EVAL_PATH:$LD_LIBRARY_PATH
|
||||
|
||||
CMD="$CMD_POLY_EVAL_PATH/cmdPolyEval $OPTIONS"
|
||||
|
||||
mkdir -p $BUILD_DIR
|
||||
pushd $BUILD_DIR
|
||||
|
||||
echo Generating IP cores for $FBITS
|
||||
{
|
||||
#$CMD -name acl_fadd FPAdd $EXP_BITS $MAN_BITS
|
||||
#$CMD -name acl_fsub FPSub $EXP_BITS $MAN_BITS
|
||||
#$CMD -name acl_fmul FPMul $EXP_BITS $MAN_BITS
|
||||
$CMD -name acl_fmadd FPMultAdd $EXP_BITS $MAN_BITS
|
||||
$CMD -name acl_fdiv FPDiv $EXP_BITS $MAN_BITS 0
|
||||
$CMD -name acl_fsqrt FPSqrt $EXP_BITS $MAN_BITS
|
||||
#$CMD -name acl_ftoi FPToFXP $EXP_BITS $MAN_BITS 32 0 1
|
||||
#$CMD -name acl_ftou FPToFXP $EXP_BITS $MAN_BITS 32 0 0
|
||||
#$CMD -name acl_itof FXPToFP 32 0 1 $EXP_BITS $MAN_BITS
|
||||
#$CMD -name acl_utof FXPToFP 32 0 0 $EXP_BITS $MAN_BITS
|
||||
} > ip_gen.log 2>&1
|
||||
|
||||
cp $QUARTUS_HOME/dspba/backend/Libraries/sv/base/dspba_library_ver.sv dspba_delay_ver.sv
|
||||
|
||||
popd
|
||||
1
hw/syn/altera/opae/.gitignore
vendored
Normal file
1
hw/syn/altera/opae/.gitignore
vendored
Normal file
@@ -0,0 +1 @@
|
||||
build*/*
|
||||
152
hw/syn/altera/opae/Makefile
Normal file
152
hw/syn/altera/opae/Makefile
Normal file
@@ -0,0 +1,152 @@
|
||||
DEVICE_FAMILY ?= arria10
|
||||
XLEN ?= 32
|
||||
PREFIX ?= build$(XLEN)
|
||||
TARGET ?= fpga
|
||||
NUM_CORES ?= 1
|
||||
|
||||
SCRIPT_DIR = ../../../scripts
|
||||
RTL_DIR = ../../../rtl
|
||||
DPI_DIR = ../../../dpi
|
||||
AFU_DIR = $(RTL_DIR)/afu/opae
|
||||
THIRD_PARTY_DIR = ../../../../third_party
|
||||
IP_CACHE_DIR = ../ip_cache/$(DEVICE_FAMILY)
|
||||
|
||||
BUILD_DIR = $(PREFIX)_$(DEVICE_FAMILY)_$(TARGET)_$(NUM_CORES)c
|
||||
|
||||
ifeq ($(shell which qsub-synth),)
|
||||
RUN_SYNTH=$(OPAE_PLATFORM_ROOT)/bin/run.sh > build.log 2>&1 &
|
||||
else
|
||||
RUN_SYNTH=qsub-synth
|
||||
endif
|
||||
|
||||
# control RTL debug tracing states
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_PIPELINE
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_ICACHE
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_DCACHE
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_MEM
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_BANK
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_MSHR
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_TAG
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_DATA
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_AFU
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_TEX
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_RASTER
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_ROP
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_GBAR
|
||||
|
||||
# Control logic analyzer monitors
|
||||
DBG_SCOPE_FLAGS += -DDBG_SCOPE_AFU
|
||||
DBG_SCOPE_FLAGS += -DDBG_SCOPE_ISSUE
|
||||
DBG_SCOPE_FLAGS += -DDBG_SCOPE_FETCH
|
||||
DBG_SCOPE_FLAGS += -DDBG_SCOPE_LSU
|
||||
DBG_SCOPE_FLAGS += -DDBG_SCOPE_RASTER
|
||||
DBG_SCOPE_FLAGS += -DDBG_SCOPE_MSCHED
|
||||
|
||||
ifeq ($(DEVICE_FAMILY), stratix10)
|
||||
CONFIGS += -DALTERA_S10
|
||||
endif
|
||||
ifeq ($(DEVICE_FAMILY), arria10)
|
||||
CONFIGS += -DALTERA_A10
|
||||
endif
|
||||
|
||||
# cluster configuration
|
||||
CONFIGS_1c := -DNUM_CLUSTERS=1 -DNUM_CORES=1
|
||||
CONFIGS_2c := -DNUM_CLUSTERS=1 -DNUM_CORES=2
|
||||
CONFIGS_4c := -DNUM_CLUSTERS=1 -DNUM_CORES=4
|
||||
CONFIGS_8c := -DNUM_CLUSTERS=1 -DNUM_CORES=8
|
||||
CONFIGS_16c := -DNUM_CLUSTERS=1 -DNUM_CORES=16 -DL2_ENABLE
|
||||
CONFIGS_32c := -DNUM_CLUSTERS=2 -DNUM_CORES=16 -DL2_ENABLE
|
||||
CONFIGS_64c := -DNUM_CLUSTERS=4 -DNUM_CORES=16 -DL2_ENABLE
|
||||
CONFIGS += $(CONFIGS_$(NUM_CORES)c)
|
||||
|
||||
# include paths
|
||||
FPU_INCLUDE = -I$(RTL_DIR)/fpu
|
||||
ifneq (,$(findstring FPU_FPNEW,$(CONFIGS)))
|
||||
FPU_INCLUDE += -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -J$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/fpnew/src
|
||||
endif
|
||||
RTL_INCLUDE = -I$(RTL_DIR) -I$(DPI_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache -I$(AFU_DIR) -I$(IP_CACHE_DIR)
|
||||
RTL_INCLUDE += $(FPU_INCLUDE)
|
||||
|
||||
# compilation flags
|
||||
CFLAGS += -DSYNTHESIS -DQUARTUS
|
||||
CFLAGS += -DXLEN_$(XLEN)
|
||||
CFLAGS += $(CONFIGS)
|
||||
CFLAGS += $(RTL_INCLUDE)
|
||||
|
||||
ifneq ($(TARGET), fpga)
|
||||
CFLAGS += -DSIMULATION
|
||||
endif
|
||||
|
||||
# Debugigng
|
||||
ifdef DEBUG
|
||||
ifeq ($(TARGET), fpga)
|
||||
CFLAGS += -DNDEBUG -DSCOPE $(DBG_SCOPE_FLAGS)
|
||||
SCOPE_JSON += $(BUILD_DIR)/scope.json
|
||||
else
|
||||
CFLAGS += $(DBG_TRACE_FLAGS)
|
||||
endif
|
||||
else
|
||||
CFLAGS += -DNDEBUG
|
||||
endif
|
||||
|
||||
# Enable scope analyzer
|
||||
ifdef SCOPE
|
||||
CFLAGS += -DSCOPE
|
||||
endif
|
||||
|
||||
# Enable perf counters
|
||||
ifdef PERF
|
||||
CFLAGS += -DPERF_ENABLE
|
||||
endif
|
||||
|
||||
# ast dump flags
|
||||
XML_CFLAGS = $(filter-out -DSYNTHESIS -DQUARTUS, $(CFLAGS)) -I$(AFU_DIR)/ccip -I$(DPI_DIR) -DNOPAE
|
||||
|
||||
all: swconfig ip-gen setup build
|
||||
|
||||
ip-gen: $(IP_CACHE_DIR)/ip-gen.log
|
||||
$(IP_CACHE_DIR)/ip-gen.log:
|
||||
../ip_gen.sh $(IP_CACHE_DIR)
|
||||
|
||||
swconfig: vortex_afu.h
|
||||
vortex_afu.h: vortex_afu.json
|
||||
afu_json_mgr json-info --afu-json=$^ --c-hdr=$@
|
||||
|
||||
$(BUILD_DIR)/setup.cfg:
|
||||
mkdir -p $(BUILD_DIR); cp setup.cfg $(BUILD_DIR)/setup.cfg
|
||||
|
||||
$(BUILD_DIR)/vortex_afu.qsf:
|
||||
mkdir -p $(BUILD_DIR); cp vortex_afu.qsf $(BUILD_DIR)/vortex_afu.qsf
|
||||
|
||||
$(BUILD_DIR)/vortex_afu.json:
|
||||
mkdir -p $(BUILD_DIR); cp vortex_afu.json $(BUILD_DIR)/vortex_afu.json
|
||||
|
||||
gen-sources: $(BUILD_DIR)/sources.txt
|
||||
$(BUILD_DIR)/sources.txt:
|
||||
mkdir -p $(BUILD_DIR); $(SCRIPT_DIR)/gen_sources.sh $(CFLAGS) -C$(BUILD_DIR)/src -O$(BUILD_DIR)/sources.txt
|
||||
|
||||
setup: $(BUILD_DIR)/synth
|
||||
$(BUILD_DIR)/synth: $(BUILD_DIR)/sources.txt $(BUILD_DIR)/setup.cfg $(BUILD_DIR)/vortex_afu.qsf $(BUILD_DIR)/vortex_afu.json
|
||||
ifeq ($(TARGET), asesim)
|
||||
afu_sim_setup -s $(BUILD_DIR)/setup.cfg $(BUILD_DIR)/synth
|
||||
else
|
||||
afu_synth_setup -s $(BUILD_DIR)/setup.cfg $(BUILD_DIR)/synth
|
||||
endif
|
||||
|
||||
build: ip-gen setup $(SCOPE_JSON)
|
||||
ifeq ($(TARGET), asesim)
|
||||
make -C $(BUILD_DIR)/synth > $(BUILD_DIR)/synth/build.log 2>&1 &
|
||||
else
|
||||
cd $(BUILD_DIR)/synth && $(RUN_SYNTH)
|
||||
endif
|
||||
|
||||
gen-ast: $(BUILD_DIR)/vortex.xml
|
||||
$(BUILD_DIR)/vortex.xml: setup
|
||||
verilator --xml-only -O0 $(XML_CFLAGS) vortex_afu.sv --xml-output $(BUILD_DIR)/vortex.xml
|
||||
|
||||
scope-json: $(BUILD_DIR)/scope.json
|
||||
$(BUILD_DIR)/scope.json: $(BUILD_DIR)/vortex.xml
|
||||
$(SCRIPT_DIR)/scope.py $(BUILD_DIR)/vortex.xml -o $(BUILD_DIR)/scope.json
|
||||
|
||||
clean:
|
||||
rm -rf vortex_afu.h $(BUILD_DIR)
|
||||
19
hw/syn/altera/opae/fpga_prog.sh
Executable file
19
hw/syn/altera/opae/fpga_prog.sh
Executable file
@@ -0,0 +1,19 @@
|
||||
#!/bin/bash
|
||||
|
||||
# Copyright © 2019-2023
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
# FPGA programming
|
||||
# first argument is the bitstream
|
||||
|
||||
fpgaconf --bus 0xaf $1
|
||||
@@ -1,5 +1,18 @@
|
||||
#!/bin/bash
|
||||
|
||||
# Copyright © 2019-2023
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
SCRIPT_DIR="$( cd "$( dirname "${BASH_SOURCE[0]}" )" >/dev/null 2>&1 && pwd )"
|
||||
|
||||
BUILD_DIR=$1
|
||||
@@ -7,7 +20,7 @@ BUILD_DIR=$1
|
||||
PROGRAM=$(basename "$2")
|
||||
PROGRAM_DIR=`dirname $2`
|
||||
|
||||
VORTEX_DRV_PATH=$SCRIPT_DIR/../../../driver
|
||||
VORTEX_RT_PATH=$SCRIPT_DIR/../../../../runtime
|
||||
|
||||
# Export ASE_WORKDIR variable
|
||||
export ASE_WORKDIR=$SCRIPT_DIR/$BUILD_DIR/work
|
||||
@@ -35,5 +48,5 @@ done
|
||||
# run application
|
||||
pushd $PROGRAM_DIR
|
||||
echo " [DBG] running ./$PROGRAM $*"
|
||||
ASE_LOG=0 LD_LIBRARY_PATH=$POCL_RT_PATH/lib:$VORTEX_DRV_PATH/asesim:$LD_LIBRARY_PATH ./$PROGRAM $*
|
||||
popd
|
||||
ASE_LOG=0 LD_LIBRARY_PATH=$POCL_RT_PATH/lib:$VORTEX_RT_PATH/opae:$LD_LIBRARY_PATH ./$PROGRAM $*
|
||||
popd
|
||||
4
hw/syn/altera/opae/setup.cfg
Normal file
4
hw/syn/altera/opae/setup.cfg
Normal file
@@ -0,0 +1,4 @@
|
||||
vortex_afu.json
|
||||
QI:vortex_afu.qsf
|
||||
|
||||
C:sources.txt
|
||||
@@ -2,21 +2,24 @@
|
||||
"version": 1,
|
||||
"afu-image": {
|
||||
"power": 0,
|
||||
"clock-frequency-high": "auto",
|
||||
"clock-frequency-low": "auto",
|
||||
"clock-frequency-high": "auto-200",
|
||||
"clock-frequency-low": "auto-100",
|
||||
|
||||
"cmd-mem-read": 1,
|
||||
"cmd-mem-write": 2,
|
||||
"cmd-run": 3,
|
||||
"cmd-dcr-write": 4,
|
||||
"cmd-max-value": 4,
|
||||
|
||||
"mmio-cmd-type": 10,
|
||||
"mmio-io-addr": 12,
|
||||
"mmio-mem-addr": 14,
|
||||
"mmio-data-size": 16,
|
||||
"mmio-cmd-arg0": 12,
|
||||
"mmio-cmd-arg1": 14,
|
||||
"mmio-cmd-arg2": 16,
|
||||
"mmio-status": 18,
|
||||
"mmio-scope-read": 20,
|
||||
"mmio-scope-write": 22,
|
||||
"mmio-dev-caps": 24,
|
||||
"mmio-isa-caps": 26,
|
||||
|
||||
"afu-top-interface":
|
||||
{
|
||||
@@ -4,24 +4,25 @@
|
||||
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
|
||||
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009
|
||||
set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS ON
|
||||
set_global_assignment -name VERILOG_MACRO QUARTUS
|
||||
set_global_assignment -name VERILOG_MACRO SYNTHESIS
|
||||
set_global_assignment -name VERILOG_MACRO NDEBUG
|
||||
set_global_assignment -name MESSAGE_DISABLE 16818
|
||||
set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
|
||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
|
||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
|
||||
|
||||
set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
|
||||
set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE"
|
||||
|
||||
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
|
||||
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 2.0
|
||||
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
|
||||
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
|
||||
|
||||
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
|
||||
set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
|
||||
set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
|
||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
|
||||
|
||||
#set_global_assignment -name USE_HIGH_SPEED_ADDER ON
|
||||
#set_global_assignment -name MUX_RESTRUCTURE ON
|
||||
@@ -30,6 +31,6 @@ set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
|
||||
#set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
|
||||
#set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
|
||||
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
|
||||
set_global_assignment -name SEED 1
|
||||
#set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
#set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
|
||||
#set_global_assignment -name SEED 1
|
||||
6
hw/syn/altera/power_play.sh
Normal file
6
hw/syn/altera/power_play.sh
Normal file
@@ -0,0 +1,6 @@
|
||||
#!/bin/bash
|
||||
|
||||
# Generate Power Report
|
||||
# first argument is the project name
|
||||
|
||||
quartus_pow --input_vcd=trace.vcd --vcd_filter_glitches=on --default_input_io_toggle_rate=10000transitions/s $1
|
||||
41
hw/syn/altera/quartus/.gitignore
vendored
Normal file
41
hw/syn/altera/quartus/.gitignore
vendored
Normal file
@@ -0,0 +1,41 @@
|
||||
/unittest/*
|
||||
!/unittest/Makefile
|
||||
|
||||
/smem/*
|
||||
!/smem/Makefile
|
||||
|
||||
/cache/*
|
||||
!/cache/Makefile
|
||||
|
||||
/vortex/*
|
||||
!/vortex/Makefile
|
||||
|
||||
/pipeline/*
|
||||
!/pipeline/Makefile
|
||||
|
||||
/core/*
|
||||
!/core/Makefile
|
||||
|
||||
/top/*
|
||||
!/top/Makefile
|
||||
|
||||
/top-gfx/*
|
||||
!/top-gfx/Makefile
|
||||
|
||||
/test/*
|
||||
!/test/Makefile
|
||||
|
||||
/fpu/*
|
||||
!/fpu/Makefile
|
||||
|
||||
/tex/*
|
||||
!/tex/Makefile
|
||||
|
||||
/rop/*
|
||||
!/rop/Makefile
|
||||
|
||||
/raster/*
|
||||
!/raster/Makefile
|
||||
|
||||
/vortex-gfx/*
|
||||
!/vortex-gfx/Makefile
|
||||
61
hw/syn/altera/quartus/Makefile
Normal file
61
hw/syn/altera/quartus/Makefile
Normal file
@@ -0,0 +1,61 @@
|
||||
PREFIX ?= build
|
||||
|
||||
BUILD_DIR=$(PREFIX)_$(DEVICE_FAMILY)
|
||||
|
||||
IP_CACHE_DIR=../ip_cache/$(DEVICE_FAMILY)
|
||||
|
||||
.PHONY: dogfood unittest pipeline smem cache fpu core vortex top test
|
||||
|
||||
ip-gen: $(IP_CACHE_DIR)/ip_gen.log
|
||||
$(IP_CACHE_DIR)/ip_gen.log:
|
||||
../ip_gen.sh $(IP_CACHE_DIR)
|
||||
|
||||
dogfood:
|
||||
mkdir -p dogfood/$(BUILD_DIR)
|
||||
cp dogfood/Makefile dogfood/$(BUILD_DIR)
|
||||
$(MAKE) -C dogfood/$(BUILD_DIR) clean && $(MAKE) -C dogfood/$(BUILD_DIR) > dogfood/$(BUILD_DIR)/build.log 2>&1 &
|
||||
|
||||
unittest:
|
||||
mkdir -p unittest/$(BUILD_DIR)
|
||||
cp unittest/Makefile unittest/$(BUILD_DIR)
|
||||
$(MAKE) -C unittest/$(BUILD_DIR) clean && $(MAKE) -C unittest/$(BUILD_DIR) > unittest/$(BUILD_DIR)/build.log 2>&1 &
|
||||
|
||||
pipeline:
|
||||
mkdir -p pipeline/$(BUILD_DIR)
|
||||
cp pipeline/Makefile pipeline/$(BUILD_DIR)
|
||||
$(MAKE) -C pipeline/$(BUILD_DIR) clean && $(MAKE) -C pipeline/$(BUILD_DIR) > pipeline/$(BUILD_DIR)/build.log 2>&1 &
|
||||
|
||||
smem:
|
||||
mkdir -p smem/$(BUILD_DIR)
|
||||
cp smem/Makefile smem/$(BUILD_DIR)
|
||||
$(MAKE) -C smem/$(BUILD_DIR) clean && $(MAKE) -C smem/$(BUILD_DIR) > smem/$(BUILD_DIR)/build.log 2>&1 &
|
||||
|
||||
cache:
|
||||
mkdir -p cache/$(BUILD_DIR)
|
||||
cp cache/Makefile cache/$(BUILD_DIR)
|
||||
$(MAKE) -C cache/$(BUILD_DIR) clean && $(MAKE) -C cache/$(BUILD_DIR) > cache/$(BUILD_DIR)/build.log 2>&1 &
|
||||
|
||||
fpu: ip-gen
|
||||
mkdir -p fpu/$(BUILD_DIR)
|
||||
cp fpu/Makefile fpu/$(BUILD_DIR)
|
||||
$(MAKE) -C fpu/$(BUILD_DIR) clean && $(MAKE) -C fpu/$(BUILD_DIR) > fpu/$(BUILD_DIR)/build.log 2>&1 &
|
||||
|
||||
core:
|
||||
mkdir -p core/$(BUILD_DIR)
|
||||
cp core/Makefile core/$(BUILD_DIR)
|
||||
$(MAKE) -C core/$(BUILD_DIR) clean && $(MAKE) -C core/$(BUILD_DIR) > core/$(BUILD_DIR)/build.log 2>&1 &
|
||||
|
||||
vortex: ip-gen
|
||||
mkdir -p vortex/$(BUILD_DIR)
|
||||
cp vortex/Makefile vortex/$(BUILD_DIR)
|
||||
$(MAKE) -C vortex/$(BUILD_DIR) clean && $(MAKE) -C vortex/$(BUILD_DIR) > vortex/$(BUILD_DIR)/build.log 2>&1 &
|
||||
|
||||
top: ip-gen
|
||||
mkdir -p top/$(BUILD_DIR)
|
||||
cp top/Makefile top/$(BUILD_DIR)
|
||||
$(MAKE) -C top/$(BUILD_DIR) clean && $(MAKE) -C top/$(BUILD_DIR) > top/$(BUILD_DIR)/build.log 2>&1 &
|
||||
|
||||
test: ip-gen
|
||||
mkdir -p test/$(BUILD_DIR)
|
||||
cp test/Makefile test/$(BUILD_DIR)
|
||||
$(MAKE) -C test/$(BUILD_DIR) clean && $(MAKE) -C test/$(BUILD_DIR) > test/$(BUILD_DIR)/build.log 2>&1 &
|
||||
7
hw/syn/altera/quartus/cache/Makefile
vendored
Executable file
7
hw/syn/altera/quartus/cache/Makefile
vendored
Executable file
@@ -0,0 +1,7 @@
|
||||
PROJECT = VX_cache_cluster_top
|
||||
TOP_LEVEL_ENTITY = $(PROJECT)
|
||||
SRC_FILE = VX_cache_cluster.sv
|
||||
|
||||
include ../../common.mk
|
||||
|
||||
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache
|
||||
99
hw/syn/altera/quartus/common.mk
Normal file
99
hw/syn/altera/quartus/common.mk
Normal file
@@ -0,0 +1,99 @@
|
||||
RTL_DIR = ../../../../../rtl
|
||||
AFU_DIR = $(RTL_DIR)/afu/opae
|
||||
THIRD_PARTY_DIR = ../../../../../../third_party
|
||||
IP_CACHE_DIR = ../../../ip_cache/$(DEVICE_FAMILY)
|
||||
SCRIPT_DIR = ../../../../../scripts
|
||||
THIRD_PARTY_DIR = ../../../../../../third_party
|
||||
|
||||
ifeq ($(DEVICE_FAMILY), stratix10)
|
||||
FAMILY = "Stratix 10"
|
||||
DEVICE = 1SX280HN2F43E2VG
|
||||
endif
|
||||
ifeq ($(DEVICE_FAMILY), arria10)
|
||||
FAMILY = "Arria 10"
|
||||
DEVICE = 10AX115N3F40E2SG
|
||||
endif
|
||||
|
||||
CONFIGS += -DNDEBUG
|
||||
CONFIGS += -DQUARTUS
|
||||
CONFIGS += -DSYNTHESIS
|
||||
CONFIGS += -DNOGLOBALS
|
||||
|
||||
PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
|
||||
|
||||
# Executable Configuration
|
||||
SYN_ARGS = --parallel --read_settings_files=on
|
||||
FIT_ARGS = --parallel --part=$(DEVICE) --read_settings_files=on
|
||||
ASM_ARGS =
|
||||
STA_ARGS = --parallel --do_report_timing
|
||||
POW_ARGS = --no_input_file --default_input_io_toggle_rate=60% --default_toggle_rate=20% --use_vectorless_estimation=off
|
||||
|
||||
# Build targets
|
||||
all: gen-sources $(PROJECT).sta.rpt $(PROJECT).pow.rpt
|
||||
|
||||
gen-sources: src
|
||||
src:
|
||||
mkdir -p src
|
||||
$(SCRIPT_DIR)/gen_sources.sh $(CONFIGS) $(RTL_INCLUDE) -P -Csrc
|
||||
|
||||
syn: $(PROJECT).syn.rpt
|
||||
|
||||
fit: $(PROJECT).fit.rpt
|
||||
|
||||
asm: $(PROJECT).asm.rpt
|
||||
|
||||
sta: $(PROJECT).sta.rpt
|
||||
|
||||
pow: $(PROJECT).pow.rpt
|
||||
|
||||
smart: smart.log
|
||||
|
||||
# Target implementations
|
||||
STAMP = echo done >
|
||||
|
||||
$(PROJECT).syn.rpt: smart.log syn.chg
|
||||
quartus_syn $(SYN_ARGS) $(PROJECT)
|
||||
$(STAMP) fit.chg
|
||||
|
||||
$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt
|
||||
quartus_fit $(FIT_ARGS) $(PROJECT)
|
||||
$(STAMP) asm.chg
|
||||
$(STAMP) sta.chg
|
||||
|
||||
$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt
|
||||
quartus_asm $(ASM_ARGS) $(PROJECT)
|
||||
$(STAMP) pow.chg
|
||||
|
||||
$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt
|
||||
quartus_sta $(STA_ARGS) $(PROJECT)
|
||||
|
||||
$(PROJECT).pow.rpt: smart.log pow.chg $(PROJECT).asm.rpt
|
||||
quartus_pow $(POW_ARGS) $(PROJECT)
|
||||
|
||||
smart.log: $(PROJECT_FILES)
|
||||
quartus_sh --determine_smart_action $(PROJECT) > smart.log
|
||||
|
||||
# Project initialization
|
||||
$(PROJECT_FILES): gen-sources
|
||||
quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "src"
|
||||
|
||||
syn.chg:
|
||||
$(STAMP) syn.chg
|
||||
|
||||
fit.chg:
|
||||
$(STAMP) fit.chg
|
||||
|
||||
sta.chg:
|
||||
$(STAMP) sta.chg
|
||||
|
||||
asm.chg:
|
||||
$(STAMP) asm.chg
|
||||
|
||||
pow.chg:
|
||||
$(STAMP) pow.chg
|
||||
|
||||
program: $(PROJECT).sof
|
||||
quartus_pgm --no_banner --mode=jtag -o "$(PROJECT).sof"
|
||||
|
||||
clean:
|
||||
rm -rf src bin *.rpt *.chg *.qsf *.qpf *.qws *.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox
|
||||
14
hw/syn/altera/quartus/core/Makefile
Normal file
14
hw/syn/altera/quartus/core/Makefile
Normal file
@@ -0,0 +1,14 @@
|
||||
PROJECT = VX_core_top
|
||||
TOP_LEVEL_ENTITY = $(PROJECT)
|
||||
SRC_FILE = VX_core.sv
|
||||
|
||||
include ../../common.mk
|
||||
|
||||
#CONFIGS += -DNUM_WARPS=32
|
||||
#CONFIGS += -DNUM_THREADS=32
|
||||
|
||||
FPU_INCLUDE = -I$(RTL_DIR)/fpu
|
||||
ifneq (,$(findstring FPU_FPNEW,$(CONFIGS)))
|
||||
FPU_INCLUDE += -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -J$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/fpnew/src
|
||||
endif
|
||||
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache -I$(IP_CACHE_DIR) $(FPU_INCLUDE)
|
||||
11
hw/syn/altera/quartus/fpu/Makefile
Normal file
11
hw/syn/altera/quartus/fpu/Makefile
Normal file
@@ -0,0 +1,11 @@
|
||||
PROJECT = VX_fpu_dsp
|
||||
TOP_LEVEL_ENTITY = $(PROJECT)
|
||||
SRC_FILE = $(PROJECT).sv
|
||||
|
||||
include ../../common.mk
|
||||
|
||||
FPU_INCLUDE = -I$(RTL_DIR)/fpu
|
||||
ifneq (,$(findstring FPU_FPNEW,$(CONFIGS)))
|
||||
FPU_INCLUDE += -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -J$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/fpnew/src
|
||||
endif
|
||||
RTL_INCLUDE = $(FPU_INCLUDE) -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(IP_CACHE_DIR)
|
||||
1
hw/syn/altera/quartus/project.sdc
Normal file
1
hw/syn/altera/quartus/project.sdc
Normal file
@@ -0,0 +1 @@
|
||||
create_clock -name {clk} -period "200 MHz" -waveform { 0.000 1.0 } [get_ports {clk}]
|
||||
@@ -1,3 +1,16 @@
|
||||
# Copyright © 2019-2023
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
load_package flow
|
||||
package require cmdline
|
||||
|
||||
@@ -35,21 +48,11 @@ set_global_assignment -name PROJECT_OUTPUT_DIRECTORY bin
|
||||
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
|
||||
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009
|
||||
set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS ON
|
||||
set_global_assignment -name VERILOG_MACRO QUARTUS
|
||||
set_global_assignment -name VERILOG_MACRO SYNTHESIS
|
||||
set_global_assignment -name VERILOG_MACRO NDEBUG
|
||||
set_global_assignment -name MESSAGE_DISABLE 16818
|
||||
set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
|
||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
|
||||
|
||||
set_global_assignment -name OPTIMIZATION_TECHNIQUE AREA
|
||||
set_global_assignment -name SEED 1
|
||||
|
||||
# Power estimation
|
||||
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
|
||||
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
||||
|
||||
switch $opts(family) {
|
||||
"Arria 10" {
|
||||
set_global_assignment -name VERILOG_MACRO ALTERA_A10
|
||||
@@ -82,11 +85,16 @@ foreach arg $q_args_orig {
|
||||
|
||||
proc make_all_pins_virtual {} {
|
||||
execute_module -tool map
|
||||
set excludes { clk }
|
||||
set name_ids [get_names -filter * -node_type pin]
|
||||
foreach_in_collection name_id $name_ids {
|
||||
set pin_name [get_name_info -info full_path $name_id]
|
||||
post_message "Making VIRTUAL_PIN assignment to $pin_name"
|
||||
set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON
|
||||
if { [lsearch -exact -nocase $excludes $pin_name] >= 0 } {
|
||||
post_message "Skipping VIRTUAL_PIN assignment to $pin_name"
|
||||
} else {
|
||||
post_message "Making VIRTUAL_PIN assignment to $pin_name"
|
||||
set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON
|
||||
}
|
||||
}
|
||||
export_assignments
|
||||
}
|
||||
7
hw/syn/altera/quartus/smem/Makefile
Executable file
7
hw/syn/altera/quartus/smem/Makefile
Executable file
@@ -0,0 +1,7 @@
|
||||
PROJECT = VX_shared_mem
|
||||
TOP_LEVEL_ENTITY = $(PROJECT)
|
||||
SRC_FILE = $(PROJECT).sv
|
||||
|
||||
include ../../common.mk
|
||||
|
||||
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/mem
|
||||
11
hw/syn/altera/quartus/test/Makefile
Normal file
11
hw/syn/altera/quartus/test/Makefile
Normal file
@@ -0,0 +1,11 @@
|
||||
PROJECT = Vortex
|
||||
TOP_LEVEL_ENTITY = $(PROJECT)
|
||||
SRC_FILE = $(PROJECT).sv
|
||||
|
||||
include ../../common.mk
|
||||
|
||||
FPU_INCLUDE = -I$(RTL_DIR)/fpu
|
||||
ifneq (,$(findstring FPU_FPNEW,$(CONFIGS)))
|
||||
FPU_INCLUDE += -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -J$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/fpnew/src
|
||||
endif
|
||||
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache -I$(IP_CACHE_DIR) $(FPU_INCLUDE)
|
||||
@@ -1,3 +1,16 @@
|
||||
# Copyright © 2019-2023
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
package require cmdline
|
||||
|
||||
set options {
|
||||
18
hw/syn/altera/quartus/top/Makefile
Normal file
18
hw/syn/altera/quartus/top/Makefile
Normal file
@@ -0,0 +1,18 @@
|
||||
PROJECT = vortex_afu
|
||||
TOP_LEVEL_ENTITY = $(PROJECT)
|
||||
SRC_FILE = $(PROJECT).sv
|
||||
|
||||
include ../../common.mk
|
||||
|
||||
CONFIGS += -DNOPAE
|
||||
|
||||
#CONFIGS += -DNUM_CORES=2
|
||||
#CONFIGS += -DNUM_WARPS=32
|
||||
#CONFIGS += -DNUM_THREADS=32
|
||||
#CONFIGS += -DL2_ENABLE
|
||||
|
||||
FPU_INCLUDE = -I$(RTL_DIR)/fpu
|
||||
ifneq (,$(findstring FPU_FPNEW,$(CONFIGS)))
|
||||
FPU_INCLUDE += -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -J$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/fpnew/src
|
||||
endif
|
||||
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache -I$(AFU_DIR) -I$(AFU_DIR)/ccip -I$(IP_CACHE_DIR) $(FPU_INCLUDE)
|
||||
11
hw/syn/altera/quartus/unittest/Makefile
Normal file
11
hw/syn/altera/quartus/unittest/Makefile
Normal file
@@ -0,0 +1,11 @@
|
||||
PROJECT = Unittest
|
||||
TOP_LEVEL_ENTITY = $(PROJECT)
|
||||
SRC_FILE = $(PROJECT).sv
|
||||
|
||||
include ../../common.mk
|
||||
|
||||
FPU_INCLUDE = -I$(RTL_DIR)/fpu
|
||||
ifneq (,$(findstring FPU_FPNEW,$(CONFIGS)))
|
||||
FPU_INCLUDE += -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -J$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/fpnew/src
|
||||
endif
|
||||
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache -I$(IP_CACHE_DIR) $(FPU_INCLUDE)
|
||||
16
hw/syn/altera/quartus/vortex/Makefile
Normal file
16
hw/syn/altera/quartus/vortex/Makefile
Normal file
@@ -0,0 +1,16 @@
|
||||
PROJECT = Vortex
|
||||
TOP_LEVEL_ENTITY = $(PROJECT)
|
||||
SRC_FILE = $(PROJECT).sv
|
||||
|
||||
include ../../common.mk
|
||||
|
||||
#CONFIGS += -DNUM_CORES=2
|
||||
#CONFIGS += -DNUM_WARPS=32
|
||||
#CONFIGS += -DNUM_THREADS=32
|
||||
#CONFIGS += -DL2_ENABLE
|
||||
|
||||
FPU_INCLUDE = -I$(RTL_DIR)/fpu
|
||||
ifneq (,$(findstring FPU_FPNEW,$(CONFIGS)))
|
||||
FPU_INCLUDE += -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -J$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/fpnew/src
|
||||
endif
|
||||
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache -I$(IP_CACHE_DIR) $(FPU_INCLUDE)
|
||||
17
hw/syn/altera/report_area.sh
Executable file
17
hw/syn/altera/report_area.sh
Executable file
@@ -0,0 +1,17 @@
|
||||
#!/bin/bash
|
||||
|
||||
# Dump Area Report
|
||||
# first argument is the project name
|
||||
|
||||
SCRIPT_DIR="$(dirname "${BASH_SOURCE[0]}")"
|
||||
SCRIPT_DIR="$(realpath "${SCRIPT_DIR}")"
|
||||
|
||||
PROJECT_DIR=$1
|
||||
PROJECT=$2
|
||||
MODE=${3-fit}
|
||||
|
||||
echo "Running quartus_sh -t $SCRIPT_DIR/report_area.tcl $PROJECT $MODE in $PROJECT_DIR ..."
|
||||
|
||||
pushd $PROJECT_DIR
|
||||
quartus_sh -t $SCRIPT_DIR/report_area.tcl $PROJECT $MODE
|
||||
popd
|
||||
105
hw/syn/altera/report_area.tcl
Normal file
105
hw/syn/altera/report_area.tcl
Normal file
@@ -0,0 +1,105 @@
|
||||
# Copyright © 2019-2023
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
load_package report
|
||||
|
||||
set ProjectName [lindex $argv 0]
|
||||
set SynMode [lindex $argv 1]
|
||||
|
||||
proc panel_to_csv { panel_name csv_file } {
|
||||
set fh [open $csv_file w]
|
||||
# Its possible for some panels to not exist based on design (ex. if no RAMs )
|
||||
set num_rows [get_number_of_rows -name $panel_name]
|
||||
catch {
|
||||
for { set i 0 } { $i < $num_rows } { incr i } {
|
||||
set row_data_raw [get_report_panel_row -name $panel_name -row $i]
|
||||
set row_data [regsub -all , $row_data_raw ""]
|
||||
puts $fh [join $row_data ","]
|
||||
}
|
||||
}
|
||||
close $fh
|
||||
}
|
||||
|
||||
# Dump names of all known panels
|
||||
proc do_dump_panelnames { } {
|
||||
set fh [open "panels.txt" w]
|
||||
set panel_names [get_report_panel_names]
|
||||
foreach panel_name $panel_names {
|
||||
puts $fh "$panel_name"
|
||||
}
|
||||
close $fh
|
||||
}
|
||||
|
||||
proc do_map_analysis { ProjectName } {
|
||||
# Save synthesis results
|
||||
set RSyn1 "Synthesis||Synthesis Source Files Read"
|
||||
set RSyn2 "Synthesis||Partition \"root_partition\"||Synthesis Resource Usage Summary for Partition \"root_partition\""
|
||||
set RSyn3 "Synthesis||Partition \"root_partition\"||Partition \"root_partition\" Resource Utilization by Entity"
|
||||
set RSyn4 "Synthesis||Partition \"root_partition\"||Synthesis RAM Summary for Partition \"root_partition\""
|
||||
set RSyn5 "Synthesis||Partition \"root_partition\"||Partition \"root_partition\" Optimization Results||Register Statistics||Registers Protected by Synthesis"
|
||||
set RSyn6 "Synthesis||Partition \"root_partition\"||Post-Synthesis Netlist Statistics for Partition \"root_partition\""
|
||||
panel_to_csv $RSyn1 "$ProjectName.syn.area.source_files.csv"
|
||||
panel_to_csv $RSyn2 "$ProjectName.syn.area.resource_summmary.csv"
|
||||
panel_to_csv $RSyn3 "$ProjectName.syn.area.resource_breakdown.csv"
|
||||
panel_to_csv $RSyn4 "$ProjectName.syn.area.ram_summary.csv"
|
||||
panel_to_csv $RSyn5 "$ProjectName.syn.area.regs_removed.csv"
|
||||
panel_to_csv $RSyn6 "$ProjectName.syn.area.stats.csv"
|
||||
}
|
||||
|
||||
proc do_fit_analysis { ProjectName } {
|
||||
# Save par results
|
||||
set RPar1 "Fitter||Place Stage||Fitter Resource Usage Summary"
|
||||
set RPar2 "Fitter||Place Stage||Fitter Resource Utilization by Entity"
|
||||
set RPar3 "Fitter||Place Stage||Fitter Partition Statistics"
|
||||
set RPar4 "Fitter||Place Stage||Fitter RAM Summary"
|
||||
set RPar5 "Fitter||Plan Stage||Global & Other Fast Signals Summary"
|
||||
set RPar6 "Fitter||Place Stage||Non-Global High Fan-Out Signals"
|
||||
set RPar7 "Fitter||Route Stage||Routing Usage Summary"
|
||||
panel_to_csv $RPar1 "$ProjectName.fit.area.resource_summary.csv"
|
||||
panel_to_csv $RPar2 "$ProjectName.fit.area.resource_breakdown.csv"
|
||||
#panel_to_csv $RPar3 "$ProjectName.fit.area.stats.csv"
|
||||
panel_to_csv $RPar4 "$ProjectName.fit.area.ram_summary.csv"
|
||||
panel_to_csv $RPar5 "$ProjectName.fit.area.routing_global.csv"
|
||||
panel_to_csv $RPar6 "$ProjectName.fit.area.routing_high_fanout.csv"
|
||||
panel_to_csv $RPar7 "$ProjectName.fit.area.routing_summary.csv"
|
||||
}
|
||||
|
||||
proc do_fit_analysis_timingsummary { ProjectName } {
|
||||
# Save timing results
|
||||
set RT1 "TimeQuest Timing Analyzer||Slow 900mV 100C Model||Slow 900mV 100C Model Fmax Summary"
|
||||
set RT2 "TimeQuest Timing Analyzer||Slow 900mV 100C Model||Slow 900mV 100C Model Setup Summary"
|
||||
set RT3 "TimeQuest Timing Analyzer||Slow 900mV 100C Model||Slow 900mV 100C Model Hold Summary"
|
||||
set RT4 "TimeQuest Timing Analyzer||Multicorner Timing Analysis Summary"
|
||||
panel_to_csv $RT1 "$ProjectName.fit.timing.summary.fmax.csv"
|
||||
panel_to_csv $RT2 "$ProjectName.fit.timing.summary.setup.csv"
|
||||
panel_to_csv $RT3 "$ProjectName.fit.timing.summary.hold.csv"
|
||||
panel_to_csv $RT4 "$ProjectName.fit.timing.summary.multicorner.csv"
|
||||
}
|
||||
|
||||
project_open $ProjectName
|
||||
load_report
|
||||
|
||||
# print available panels
|
||||
#do_dump_panelnames
|
||||
|
||||
# => allows comparison of raw logic vs impact of routing delays
|
||||
if { $SynMode == "map" } {
|
||||
do_map_analysis $ProjectName
|
||||
# normal post-par analysis (includes routing congestion/physical placement constraints)
|
||||
} else {
|
||||
do_fit_analysis $ProjectName
|
||||
do_fit_analysis_timingsummary $ProjectName
|
||||
}
|
||||
|
||||
unload_report
|
||||
project_close
|
||||
@@ -1,3 +1,16 @@
|
||||
// Copyright © 2019-2023
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
|
||||
extern "C" {
|
||||
void load_file (char * filename);
|
||||
|
||||
@@ -1,3 +1,16 @@
|
||||
// Copyright © 2019-2023
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
`include "VX_define.vh"
|
||||
|
||||
//`define NUM_BANKS 8
|
||||
|
||||
1
hw/syn/opae/.gitignore
vendored
1
hw/syn/opae/.gitignore
vendored
@@ -1 +0,0 @@
|
||||
build_*/
|
||||
@@ -1,203 +0,0 @@
|
||||
DEVICE_FAMILY ?= arria10
|
||||
BUILD_DIR ?= build_$(DEVICE_FAMILY)
|
||||
RTL_DIR=../../rtl
|
||||
|
||||
ifeq ($(shell which qsub-synth),)
|
||||
RUN_SYNTH=$(OPAE_PLATFORM_ROOT)/bin/run.sh > build.log 2>&1 &
|
||||
else
|
||||
RUN_SYNTH=qsub-synth
|
||||
endif
|
||||
|
||||
# control RTL debug tracing states
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_PIPELINE
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_ICACHE
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_DCACHE
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_MEM
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_BANK
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_MSHR
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_TAG
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_DATA
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_AFU
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_SCOPE
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_TEX
|
||||
|
||||
DBG_FLAGS += $(DBG_TRACE_FLAGS)
|
||||
|
||||
CONFIG1 := -DNUM_CLUSTERS=1 -DNUM_CORES=1 -DL2_ENABLE=0 -DL3_ENABLE=0 $(CONFIGS)
|
||||
CONFIG2 := -DNUM_CLUSTERS=1 -DNUM_CORES=2 -DL2_ENABLE=0 -DL3_ENABLE=0 $(CONFIGS)
|
||||
CONFIG4 := -DNUM_CLUSTERS=1 -DNUM_CORES=4 -DL2_ENABLE=1 -DL3_ENABLE=0 -DICACHE_SIZE=8192 -DDCACHE_SIZE=8192 -DL2_CACHE_SIZE=131072 $(CONFIGS)
|
||||
CONFIG8 := -DNUM_CLUSTERS=1 -DNUM_CORES=8 -DL2_ENABLE=1 -DL3_ENABLE=0 -DICACHE_SIZE=8192 -DDCACHE_SIZE=8192 -DL2_CACHE_SIZE=131072 $(CONFIGS)
|
||||
CONFIG16 := -DNUM_CLUSTERS=4 -DNUM_CORES=4 -DL2_ENABLE=0 -DL3_ENABLE=1 -DICACHE_SIZE=8192 -DDCACHE_SIZE=8192 -DL3_CACHE_SIZE=262144 $(CONFIGS)
|
||||
CONFIG32 := -DNUM_CLUSTERS=4 -DNUM_CORES=8 -DL2_ENABLE=0 -DL3_ENABLE=1 -DICACHE_SIZE=8192 -DDCACHE_SIZE=8192 -DL3_CACHE_SIZE=262144 $(CONFIGS)
|
||||
CONFIG64 := -DNUM_CLUSTERS=8 -DNUM_CORES=8 -DL2_ENABLE=0 -DL3_ENABLE=1 -DICACHE_SIZE=8192 -DDCACHE_SIZE=8192 -DL3_CACHE_SIZE=524288 $(CONFIGS)
|
||||
|
||||
FPU_INCLUDE = -I$(RTL_DIR)/fp_cores -I$(RTL_DIR)/fp_cores/altera/$(DEVICE_FAMILY)
|
||||
TEX_INCLUDE = -I$(RTL_DIR)/tex_unit
|
||||
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache -I$(RTL_DIR)/afu $(FPU_INCLUDE) $(TEX_INCLUDE)
|
||||
|
||||
CFLAGS += $(RTL_INCLUDE)
|
||||
|
||||
# Debugigng
|
||||
ifdef DEBUG
|
||||
CFLAGS += $(DBG_FLAGS)
|
||||
else
|
||||
CFLAGS += -DNDEBUG
|
||||
endif
|
||||
|
||||
# Enable scope analyzer
|
||||
ifdef SCOPE
|
||||
CFLAGS += -DSCOPE
|
||||
endif
|
||||
|
||||
# Enable perf counters
|
||||
ifdef PERF
|
||||
CFLAGS += -DPERF_ENABLE
|
||||
endif
|
||||
|
||||
all: vortex_afu.h ase-1c
|
||||
|
||||
# AFU info from JSON file, including AFU UUID
|
||||
vortex_afu.h: vortex_afu.json
|
||||
afu_json_mgr json-info --afu-json=$^ --c-hdr=$@
|
||||
|
||||
$(BUILD_DIR)_ase_1c/Makefile:
|
||||
afu_sim_setup -s setup.cfg $(BUILD_DIR)_ase_1c
|
||||
|
||||
$(BUILD_DIR)_ase_2c/Makefile:
|
||||
afu_sim_setup -s setup.cfg $(BUILD_DIR)_ase_2c
|
||||
|
||||
$(BUILD_DIR)_ase_4c/Makefile:
|
||||
afu_sim_setup -s setup.cfg $(BUILD_DIR)_ase_4c
|
||||
|
||||
$(BUILD_DIR)_fpga_1c/build/dcp.qpf:
|
||||
afu_synth_setup -s setup.cfg $(BUILD_DIR)_fpga_1c
|
||||
|
||||
$(BUILD_DIR)_fpga_2c/build/dcp.qpf:
|
||||
afu_synth_setup -s setup.cfg $(BUILD_DIR)_fpga_2c
|
||||
|
||||
$(BUILD_DIR)_fpga_4c/build/dcp.qpf:
|
||||
afu_synth_setup -s setup.cfg $(BUILD_DIR)_fpga_4c
|
||||
|
||||
$(BUILD_DIR)_fpga_8c/build/dcp.qpf:
|
||||
afu_synth_setup -s setup.cfg $(BUILD_DIR)_fpga_8c
|
||||
|
||||
$(BUILD_DIR)_fpga_16c/build/dcp.qpf:
|
||||
afu_synth_setup -s setup.cfg $(BUILD_DIR)_fpga_16c
|
||||
|
||||
$(BUILD_DIR)_fpga_32c/build/dcp.qpf:
|
||||
afu_synth_setup -s setup.cfg $(BUILD_DIR)_fpga_32c
|
||||
|
||||
$(BUILD_DIR)_fpga_64c/build/dcp.qpf:
|
||||
afu_synth_setup -s setup.cfg $(BUILD_DIR)_fpga_64c
|
||||
|
||||
gen-sources-1c:
|
||||
./gen_sources.sh $(CFLAGS) $(CONFIG1) > sources.txt
|
||||
|
||||
gen-sources-2c:
|
||||
./gen_sources.sh $(CFLAGS) $(CONFIG2) > sources.txt
|
||||
|
||||
gen-sources-4c:
|
||||
./gen_sources.sh $(CFLAGS) $(CONFIG4) > sources.txt
|
||||
|
||||
gen-sources-8c:
|
||||
./gen_sources.sh $(CFLAGS) $(CONFIG8) > sources.txt
|
||||
|
||||
gen-sources-16c:
|
||||
./gen_sources.sh $(CFLAGS) $(CONFIG16) > sources.txt
|
||||
|
||||
gen-sources-32c:
|
||||
./gen_sources.sh $(CFLAGS) $(CONFIG32) > sources.txt
|
||||
|
||||
gen-sources-64c:
|
||||
./gen_sources.sh $(CFLAGS) $(CONFIG64) > sources.txt
|
||||
|
||||
# setup
|
||||
|
||||
setup-ase-1c: $(BUILD_DIR)_ase_1c/Makefile
|
||||
|
||||
setup-ase-2c: $(BUILD_DIR)_ase_2c/Makefile
|
||||
|
||||
setup-ase-4c: $(BUILD_DIR)_ase_4c/Makefile
|
||||
|
||||
setup-fpga-1c: $(BUILD_DIR)_fpga_1c/build/dcp.qpf
|
||||
|
||||
setup-fpga-2c: $(BUILD_DIR)_fpga_2c/build/dcp.qpf
|
||||
|
||||
setup-fpga-4c: $(BUILD_DIR)_fpga_4c/build/dcp.qpf
|
||||
|
||||
setup-fpga-8c: $(BUILD_DIR)_fpga_8c/build/dcp.qpf
|
||||
|
||||
setup-fpga-16c: $(BUILD_DIR)_fpga_16c/build/dcp.qpf
|
||||
|
||||
setup-fpga-32c: $(BUILD_DIR)_fpga_32c/build/dcp.qpf
|
||||
|
||||
setup-fpga-64c: $(BUILD_DIR)_fpga_64c/build/dcp.qpf
|
||||
|
||||
# build
|
||||
|
||||
ase-1c: gen-sources-1c setup-ase-1c
|
||||
make -C $(BUILD_DIR)_ase_1c
|
||||
cp $(RTL_DIR)/fp_cores/altera/$(DEVICE_FAMILY)/*.hex $(BUILD_DIR)_ase_1c/work
|
||||
|
||||
ase-2c: gen-sources-2c setup-ase-2c
|
||||
make -C $(BUILD_DIR)_ase_2c
|
||||
cp $(RTL_DIR)/fp_cores/altera/$(DEVICE_FAMILY)/*.hex $(BUILD_DIR)_ase_2c/work
|
||||
|
||||
ase-4c: gen-sources-4c setup-ase-4c
|
||||
make -C $(BUILD_DIR)_ase_4c
|
||||
cp $(RTL_DIR)/fp_cores/altera/$(DEVICE_FAMILY)/*.hex $(BUILD_DIR)_ase_4c/work
|
||||
|
||||
fpga-1c: gen-sources-1c setup-fpga-1c
|
||||
cd $(BUILD_DIR)_fpga_1c && $(RUN_SYNTH)
|
||||
|
||||
fpga-2c: gen-sources-2c setup-fpga-2c
|
||||
cd $(BUILD_DIR)_fpga_2c && $(RUN_SYNTH)
|
||||
|
||||
fpga-4c: gen-sources-4c setup-fpga-4c
|
||||
cd $(BUILD_DIR)_fpga_4c && $(RUN_SYNTH)
|
||||
|
||||
fpga-8c: gen-sources-8c setup-fpga-8c
|
||||
cd $(BUILD_DIR)_fpga_8c && $(RUN_SYNTH)
|
||||
|
||||
fpga-16c: gen-sources-16c setup-fpga-16c
|
||||
cd $(BUILD_DIR)_fpga_16c && $(RUN_SYNTH)
|
||||
|
||||
fpga-32c: gen-sources-32c setup-fpga-32c
|
||||
cd $(BUILD_DIR)_fpga_32c && $(RUN_SYNTH)
|
||||
|
||||
fpga-64c: gen-sources-64c setup-fpga-64c
|
||||
cd $(BUILD_DIR)_fpga_64c && $(RUN_SYNTH)
|
||||
|
||||
# cleanup
|
||||
|
||||
clean-ase-1c:
|
||||
rm -rf $(BUILD_DIR)_ase_1c sources.txt
|
||||
|
||||
clean-ase-2c:
|
||||
rm -rf $(BUILD_DIR)_ase_2c sources.txt
|
||||
|
||||
clean-ase-4c:
|
||||
rm -rf $(BUILD_DIR)_ase_4c sources.txt
|
||||
|
||||
clean-fpga-1c:
|
||||
rm -rf $(BUILD_DIR)_fpga_1c sources.txt
|
||||
|
||||
clean-fpga-2c:
|
||||
rm -rf $(BUILD_DIR)_fpga_2c sources.txt
|
||||
|
||||
clean-fpga-4c:
|
||||
rm -rf $(BUILD_DIR)_fpga_4c sources.txt
|
||||
|
||||
clean-fpga-8c:
|
||||
rm -rf $(BUILD_DIR)_fpga_8c sources.txt
|
||||
|
||||
clean-fpga-16c:
|
||||
rm -rf $(BUILD_DIR)_fpga_16c sources.txt
|
||||
|
||||
clean-fpga-32c:
|
||||
rm -rf $(BUILD_DIR)_fpga_32c sources.txt
|
||||
|
||||
clean-fpga-64c:
|
||||
rm -rf $(BUILD_DIR)_fpga_64c sources.txt
|
||||
|
||||
clean: vortex_afu.h clean-ase-1c clean-ase-2c clean-ase-4c clean-fpga-1c clean-fpga-2c clean-fpga-4c clean-fpga-8c clean-fpga-16c clean-fpga-32c clean-fpga-64c
|
||||
@@ -1,92 +0,0 @@
|
||||
use the following step to build vortex and run it on fpga on intel cloud server using OPAE.
|
||||
This script is also present at ~/dev/runVortex
|
||||
|
||||
## To configure quartus and opae. Run this after logging in.
|
||||
source /export/fpga/bin/setup-fpga-env fpga-pac-a10
|
||||
#########################
|
||||
## Vortex Run commands ##
|
||||
#########################
|
||||
|
||||
#
|
||||
## Synthesis
|
||||
#
|
||||
|
||||
cd /driver/hw/opae
|
||||
|
||||
# Configure a Quartus build area
|
||||
afu_synth_setup -s sources.txt build_fpga
|
||||
|
||||
# Run Quartus in the vLab batch queue
|
||||
cd build_fpga && qsub-synth
|
||||
|
||||
# check last 10 lines in build log for possible errors
|
||||
tail -n 10 ./build_fpga_1c/build.log
|
||||
|
||||
# Check if the job is submitted to the queue and running. Status should be R
|
||||
qstat | grep <user>
|
||||
|
||||
# Constantly monitoring the job submitted to the queue. Stop this using Ctrl+C
|
||||
watch ‘qstat | grep <user>’
|
||||
|
||||
#
|
||||
## Executing on FPGA
|
||||
#
|
||||
|
||||
# From the build_fpga directory acquire a fpga node
|
||||
qsub-fpga
|
||||
|
||||
# Go to the directory whree qsub-synth was run above
|
||||
cd $PBS_O_WORKDIR
|
||||
|
||||
# Load the image onto an FPGA
|
||||
fpgaconf vortex_afu.gbs
|
||||
|
||||
# If this says Multiple ports. Then use --bus with fpgaconf. #bus info can be found by fpgainfo port
|
||||
fpgaconf --bus 0xaf vortex_afu.gbs
|
||||
|
||||
# get portid
|
||||
fpgainfo port
|
||||
|
||||
# Running the Test case
|
||||
cd /driver/tests/basic
|
||||
make run-fpga
|
||||
|
||||
#
|
||||
## ASE build instructions
|
||||
#
|
||||
source /export/fpga/bin/setup-fpga-env fpga-pac-a10
|
||||
|
||||
# Acquire a sever node for running ASE simulations
|
||||
qsub-sim
|
||||
|
||||
# build
|
||||
make ase
|
||||
|
||||
# tests
|
||||
./run_ase.sh build_arria10_ase_1c ../../../tests/regression/basic/basic -n1 -t0
|
||||
./run_ase.sh build_arria10_ase_1c ../../../tests/regression/basic/basic -n1 -t1
|
||||
./run_ase.sh build_arria10_ase_1c ../../../tests/regression/basic/basic -n16
|
||||
./run_ase.sh build_arria10_ase_1c ../../../tests/regression/demo/demo -n16
|
||||
./run_ase.sh build_arria10_ase_1c ../../../tests/regression/dogfood/dogfood -n16
|
||||
./run_ase.sh build_arria10_ase_1c ../../../tests/opencl/vecadd/vecadd
|
||||
./run_ase.sh build_arria10_ase_1c ../../../tests/opencl/sgemm/sgemm -n4
|
||||
|
||||
# modify "vsim_run.tcl" to dump VCD trace
|
||||
vcd file trace.vcd
|
||||
vcd add -r /*/Vortex/hw/rtl/*
|
||||
run -all
|
||||
|
||||
# compress FPGA output files
|
||||
tar -zcvf output_files_1c.tar.gz `find ./build_fpga_1c -type f \( -iname \*.rpt -o -iname \*.txt -o -iname \*summary -o -iname \*.log \)`
|
||||
|
||||
# compress log trace
|
||||
tar -zcvf run.log.tar.gz run.log
|
||||
tar -cvjf trace.vcd.tar.bz2 trace.vcd run.log
|
||||
tar -cvjf trace.vcd.tar.bz2 build_arria10_ase_1c/work/run.log build_arria10_ase_1c/work/trace.vcd
|
||||
|
||||
# decompress log trace
|
||||
tar -zxvf vortex.vcd.tar.gz
|
||||
tar -xvf vortex.vcd.tar.bz2
|
||||
|
||||
# quick off synthesis
|
||||
make core
|
||||
@@ -1,7 +0,0 @@
|
||||
#!/bin/bash
|
||||
|
||||
# FPGA programming
|
||||
# first argument is the bitstream
|
||||
|
||||
echo "fpgaconf --bus 0xaf $1"
|
||||
fpgaconf --bus 0xaf $1
|
||||
@@ -1,46 +0,0 @@
|
||||
#!/bin/bash
|
||||
|
||||
exclude_list="VX_fpu_fpnew.sv"
|
||||
macros=()
|
||||
includes=()
|
||||
|
||||
# parse command arguments
|
||||
while getopts D:I:h flag
|
||||
do
|
||||
case "${flag}" in
|
||||
D) macros+=( ${OPTARG} );;
|
||||
I) includes+=( ${OPTARG} );;
|
||||
h) echo "Usage: [-D macro] [-I include] [-h help]"
|
||||
exit 0
|
||||
;;
|
||||
\?)
|
||||
echo "Invalid option: -$OPTARG" 1>&2
|
||||
exit 1
|
||||
;;
|
||||
esac
|
||||
done
|
||||
|
||||
# dump macros
|
||||
for value in ${macros[@]}; do
|
||||
echo "+define+$value"
|
||||
done
|
||||
|
||||
# dump include directories
|
||||
for dir in ${includes[@]}; do
|
||||
echo "+incdir+$dir"
|
||||
done
|
||||
|
||||
# dump source files
|
||||
for dir in ${includes[@]}; do
|
||||
for file in $(find $dir -maxdepth 1 -name '*.v' -o -name '*.sv' -type f); do
|
||||
exclude=0
|
||||
for fe in $exclude_list; do
|
||||
if [[ $file =~ $fe ]]; then
|
||||
exclude=1
|
||||
fi
|
||||
done
|
||||
if [[ $exclude == 0 ]]; then
|
||||
echo $file
|
||||
fi
|
||||
done
|
||||
done
|
||||
@@ -1,7 +0,0 @@
|
||||
+define+SYNTHESIS
|
||||
+define+QUARTUS
|
||||
|
||||
vortex_afu.json
|
||||
QI:vortex_afu.qsf
|
||||
|
||||
C:sources.txt
|
||||
41
hw/syn/quartus/.gitignore
vendored
41
hw/syn/quartus/.gitignore
vendored
@@ -1,41 +0,0 @@
|
||||
/unittest/*
|
||||
!/unittest/Makefile
|
||||
|
||||
/smem/*
|
||||
!/smem/Makefile
|
||||
|
||||
/cache/*
|
||||
!/cache/Makefile
|
||||
|
||||
/fpu_core/*
|
||||
!/fpu_core/Makefile
|
||||
|
||||
/vortex/*
|
||||
!/vortex/Makefile
|
||||
|
||||
/pipeline/*
|
||||
!/pipeline/Makefile
|
||||
|
||||
/core/*
|
||||
!/core/Makefile
|
||||
|
||||
/top1/*
|
||||
!/top1/Makefile
|
||||
|
||||
/top2/*
|
||||
!/top2/Makefile
|
||||
|
||||
/top4/*
|
||||
!/top4/Makefile
|
||||
|
||||
/top8/*
|
||||
!/top8/Makefile
|
||||
|
||||
/top16/*
|
||||
!/top16/Makefile
|
||||
|
||||
/top32/*
|
||||
!/top32/Makefile
|
||||
|
||||
/top64/*
|
||||
!/top64/Makefile
|
||||
@@ -1,83 +0,0 @@
|
||||
BUILD_DIR ?= build
|
||||
|
||||
.PHONY: dogfood unittest pipeline smem cache fpu_core core vortex top1 top2 top4 top8 top16 top32 top64 texunit
|
||||
|
||||
dogfood:
|
||||
mkdir -p dogfood/$(BUILD_DIR)
|
||||
cp dogfood/Makefile dogfood/$(BUILD_DIR)
|
||||
$(MAKE) -C dogfood/$(BUILD_DIR) clean && $(MAKE) -C dogfood/$(BUILD_DIR) > dogfood/$(BUILD_DIR)/build.log 2>&1 &
|
||||
|
||||
unittest:
|
||||
mkdir -p unittest/$(BUILD_DIR)
|
||||
cp unittest/Makefile unittest/$(BUILD_DIR)
|
||||
$(MAKE) -C unittest/$(BUILD_DIR) clean && $(MAKE) -C unittest/$(BUILD_DIR) > unittest/$(BUILD_DIR)/build.log 2>&1 &
|
||||
|
||||
pipeline:
|
||||
mkdir -p pipeline/$(BUILD_DIR)
|
||||
cp pipeline/Makefile pipeline/$(BUILD_DIR)
|
||||
$(MAKE) -C pipeline/$(BUILD_DIR) clean && $(MAKE) -C pipeline/$(BUILD_DIR) > pipeline/$(BUILD_DIR)/build.log 2>&1 &
|
||||
|
||||
smem:
|
||||
mkdir -p smem/$(BUILD_DIR)
|
||||
cp smem/Makefile smem/$(BUILD_DIR)
|
||||
$(MAKE) -C smem/$(BUILD_DIR) clean && $(MAKE) -C smem/$(BUILD_DIR) > smem/$(BUILD_DIR)/build.log 2>&1 &
|
||||
|
||||
cache:
|
||||
mkdir -p cache/$(BUILD_DIR)
|
||||
cp cache/Makefile cache/$(BUILD_DIR)
|
||||
$(MAKE) -C cache/$(BUILD_DIR) clean && $(MAKE) -C cache/$(BUILD_DIR) > cache/$(BUILD_DIR)/build.log 2>&1 &
|
||||
|
||||
fpu_core:
|
||||
mkdir -p fpu_core/$(BUILD_DIR)
|
||||
cp fpu_core/Makefile fpu_core/$(BUILD_DIR)
|
||||
$(MAKE) -C fpu_core/$(BUILD_DIR) clean && $(MAKE) -C fpu_core/$(BUILD_DIR) > fpu_core/$(BUILD_DIR)/build.log 2>&1 &
|
||||
|
||||
core:
|
||||
mkdir -p core/$(BUILD_DIR)
|
||||
cp core/Makefile core/$(BUILD_DIR)
|
||||
$(MAKE) -C core/$(BUILD_DIR) clean && $(MAKE) -C core/$(BUILD_DIR) > core/$(BUILD_DIR)/build.log 2>&1 &
|
||||
|
||||
vortex:
|
||||
mkdir -p vortex/$(BUILD_DIR)
|
||||
cp vortex/Makefile vortex/$(BUILD_DIR)
|
||||
$(MAKE) -C vortex/$(BUILD_DIR) clean && $(MAKE) -C vortex/$(BUILD_DIR) > vortex/$(BUILD_DIR)/build.log 2>&1 &
|
||||
|
||||
top1:
|
||||
mkdir -p top1/$(BUILD_DIR)
|
||||
cp top1/Makefile top1/$(BUILD_DIR)
|
||||
$(MAKE) -C top1/$(BUILD_DIR) clean && $(MAKE) -C top1/$(BUILD_DIR) > top1/$(BUILD_DIR)/build.log 2>&1 &
|
||||
|
||||
top2:
|
||||
mkdir -p top2/$(BUILD_DIR)
|
||||
cp top2/Makefile top2/$(BUILD_DIR)
|
||||
$(MAKE) -C top2/$(BUILD_DIR) clean && $(MAKE) -C top2/$(BUILD_DIR) > top2/$(BUILD_DIR)/build.log 2>&1 &
|
||||
|
||||
top4:
|
||||
mkdir -p top4/$(BUILD_DIR)
|
||||
cp top4/Makefile top4/$(BUILD_DIR)
|
||||
$(MAKE) -C top4/$(BUILD_DIR) clean && $(MAKE) -C top4/$(BUILD_DIR) > top4/$(BUILD_DIR)/build.log 2>&1 &
|
||||
|
||||
top8:
|
||||
mkdir -p top8/$(BUILD_DIR)
|
||||
cp top8/Makefile top8/$(BUILD_DIR)
|
||||
$(MAKE) -C top8/$(BUILD_DIR) clean && $(MAKE) -C top8/$(BUILD_DIR) > top8/$(BUILD_DIR)/build.log 2>&1 &
|
||||
|
||||
top16:
|
||||
mkdir -p top16/$(BUILD_DIR)
|
||||
cp top16/Makefile top16/$(BUILD_DIR)
|
||||
$(MAKE) -C top16/$(BUILD_DIR) clean && $(MAKE) -C top16/$(BUILD_DIR) > top16/$(BUILD_DIR)/build.log 2>&1 &
|
||||
|
||||
top32:
|
||||
mkdir -p top32/$(BUILD_DIR)
|
||||
cp top32/Makefile top32/$(BUILD_DIR)
|
||||
$(MAKE) -C top32/$(BUILD_DIR) clean && $(MAKE) -C top32/$(BUILD_DIR) > top32/$(BUILD_DIR)/build.log 2>&1 &
|
||||
|
||||
top64:
|
||||
mkdir -p top64/$(BUILD_DIR)
|
||||
cp top64/Makefile top64/$(BUILD_DIR)
|
||||
$(MAKE) -C top64/$(BUILD_DIR) clean && $(MAKE) -C top64/$(BUILD_DIR) > top64/$(BUILD_DIR)/build.log 2>&1 &
|
||||
|
||||
texunit:
|
||||
mkdir -p texunit/$(BUILD_DIR)
|
||||
cp texunit/Makefile texunit/$(BUILD_DIR)
|
||||
$(MAKE) -C texunit/$(BUILD_DIR) clean && $(MAKE) -C texunit/$(BUILD_DIR) > texunit/$(BUILD_DIR)/build.log 2>&1 &
|
||||
72
hw/syn/quartus/cache/Makefile
vendored
72
hw/syn/quartus/cache/Makefile
vendored
@@ -1,72 +0,0 @@
|
||||
PROJECT = VX_cache
|
||||
TOP_LEVEL_ENTITY = VX_cache
|
||||
SRC_FILE = VX_cache.v
|
||||
RTL_DIR = ../../../../rtl
|
||||
|
||||
FAMILY = "Arria 10"
|
||||
DEVICE = 10AX115N3F40E2SG
|
||||
|
||||
RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache
|
||||
PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
|
||||
|
||||
# Executable Configuration
|
||||
SYN_ARGS = --parallel --read_settings_files=on
|
||||
FIT_ARGS = --parallel --part=$(DEVICE) --read_settings_files=on
|
||||
ASM_ARGS =
|
||||
STA_ARGS = --parallel --do_report_timing
|
||||
|
||||
# Build targets
|
||||
all: $(PROJECT).sta.rpt
|
||||
|
||||
syn: $(PROJECT).syn.rpt
|
||||
|
||||
fit: $(PROJECT).fit.rpt
|
||||
|
||||
asm: $(PROJECT).asm.rpt
|
||||
|
||||
sta: $(PROJECT).sta.rpt
|
||||
|
||||
smart: smart.log
|
||||
|
||||
# Target implementations
|
||||
STAMP = echo done >
|
||||
|
||||
$(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES)
|
||||
quartus_syn $(PROJECT) $(SYN_ARGS)
|
||||
$(STAMP) fit.chg
|
||||
|
||||
$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt
|
||||
quartus_fit $(PROJECT) $(FIT_ARGS)
|
||||
$(STAMP) asm.chg
|
||||
$(STAMP) sta.chg
|
||||
|
||||
$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt
|
||||
quartus_asm $(PROJECT) $(ASM_ARGS)
|
||||
|
||||
$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt
|
||||
quartus_sta $(PROJECT) $(STA_ARGS)
|
||||
|
||||
smart.log: $(PROJECT_FILES)
|
||||
quartus_sh --determine_smart_action $(PROJECT) > smart.log
|
||||
|
||||
# Project initialization
|
||||
$(PROJECT_FILES):
|
||||
quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc ../../project.sdc -inc "$(RTL_INCLUDE)"
|
||||
|
||||
syn.chg:
|
||||
$(STAMP) syn.chg
|
||||
|
||||
fit.chg:
|
||||
$(STAMP) fit.chg
|
||||
|
||||
sta.chg:
|
||||
$(STAMP) sta.chg
|
||||
|
||||
asm.chg:
|
||||
$(STAMP) asm.chg
|
||||
|
||||
program: $(PROJECT).sof
|
||||
quartus_pgm --no_banner --mode=jtag -o "$(PROJECT).sof"
|
||||
|
||||
clean:
|
||||
rm -rf bin *.rpt *.chg *.qsf *.qpf *.qws *.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox
|
||||
@@ -1,81 +0,0 @@
|
||||
PROJECT = Core
|
||||
TOP_LEVEL_ENTITY = VX_core
|
||||
SRC_FILE = VX_core.v
|
||||
RTL_DIR = ../../../../rtl
|
||||
THIRD_PARTY_DIR = ../../../../../third_party
|
||||
|
||||
FAMILY = "Arria 10"
|
||||
DEVICE = 10AX115N3F40E2SG
|
||||
FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10
|
||||
|
||||
#FAMILY = "Stratix 10"
|
||||
#DEVICE = 1SX280HN2F43E2VG
|
||||
#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10
|
||||
|
||||
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(THIRD_PARTY_DIR)/fpnew/src;$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src
|
||||
TEX_INCLUDE = $(RTL_DIR)/tex_unit
|
||||
RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;$(FPU_INCLUDE);$(TEX_INCLUDE)
|
||||
|
||||
PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
|
||||
|
||||
# Executable Configuration
|
||||
SYN_ARGS = --parallel --read_settings_files=on
|
||||
FIT_ARGS = --parallel --part=$(DEVICE) --read_settings_files=on
|
||||
ASM_ARGS =
|
||||
STA_ARGS = --parallel --do_report_timing
|
||||
|
||||
# Build targets
|
||||
all: $(PROJECT).sta.rpt
|
||||
|
||||
syn: $(PROJECT).syn.rpt
|
||||
|
||||
fit: $(PROJECT).fit.rpt
|
||||
|
||||
asm: $(PROJECT).asm.rpt
|
||||
|
||||
sta: $(PROJECT).sta.rpt
|
||||
|
||||
smart: smart.log
|
||||
|
||||
# Target implementations
|
||||
STAMP = echo done >
|
||||
|
||||
$(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES)
|
||||
quartus_syn $(PROJECT) $(SYN_ARGS)
|
||||
$(STAMP) fit.chg
|
||||
|
||||
$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt
|
||||
quartus_fit $(PROJECT) $(FIT_ARGS)
|
||||
$(STAMP) asm.chg
|
||||
$(STAMP) sta.chg
|
||||
|
||||
$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt
|
||||
quartus_asm $(PROJECT) $(ASM_ARGS)
|
||||
|
||||
$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt
|
||||
quartus_sta $(PROJECT) $(STA_ARGS)
|
||||
|
||||
smart.log: $(PROJECT_FILES)
|
||||
quartus_sh --determine_smart_action $(PROJECT) > smart.log
|
||||
|
||||
# Project initialization
|
||||
$(PROJECT_FILES):
|
||||
quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "$(RTL_INCLUDE)"
|
||||
|
||||
syn.chg:
|
||||
$(STAMP) syn.chg
|
||||
|
||||
fit.chg:
|
||||
$(STAMP) fit.chg
|
||||
|
||||
sta.chg:
|
||||
$(STAMP) sta.chg
|
||||
|
||||
asm.chg:
|
||||
$(STAMP) asm.chg
|
||||
|
||||
program: $(PROJECT).sof
|
||||
quartus_pgm --no_banner --mode=jtag -o "$(PROJECT).sof"
|
||||
|
||||
clean:
|
||||
rm -rf bin *.rpt *.chg *.qsf *.qpf *.qws *.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox
|
||||
@@ -1,87 +0,0 @@
|
||||
PROJECT = VX_fpu_fpga
|
||||
TOP_LEVEL_ENTITY = VX_fpu_fpga
|
||||
SRC_FILE = VX_fpu_fpga.v
|
||||
RTL_DIR = ../../../../rtl
|
||||
THIRD_PARTY_DIR = ../../../../../third_party
|
||||
|
||||
FAMILY = "Arria 10"
|
||||
DEVICE = 10AX115N3F40E2SG
|
||||
FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10
|
||||
|
||||
#FAMILY = "Stratix 10"
|
||||
#DEVICE = 1SX280HN2F43E2VG
|
||||
#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10
|
||||
|
||||
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(THIRD_PARTY_DIR)/fpnew/src;$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src
|
||||
RTL_INCLUDE = $(FPU_INCLUDE);$(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces
|
||||
PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
|
||||
|
||||
# Part, Family
|
||||
FAMILY = "Arria 10"
|
||||
DEVICE = 10AX115N3F40E2SG
|
||||
|
||||
# Executable Configuration
|
||||
SYN_ARGS = --parallel --read_settings_files=on
|
||||
FIT_ARGS = --parallel --part=$(DEVICE) --read_settings_files=on
|
||||
ASM_ARGS =
|
||||
STA_ARGS = --parallel --do_report_timing
|
||||
|
||||
# Build targets
|
||||
all: $(PROJECT).sta.rpt
|
||||
|
||||
syn: $(PROJECT).syn.rpt
|
||||
|
||||
fit: $(PROJECT).fit.rpt
|
||||
|
||||
asm: $(PROJECT).asm.rpt
|
||||
|
||||
sta: $(PROJECT).sta.rpt
|
||||
|
||||
smart: smart.log
|
||||
|
||||
# Target implementations
|
||||
STAMP = echo done >
|
||||
|
||||
$(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES)
|
||||
quartus_syn $(PROJECT) $(SYN_ARGS)
|
||||
$(STAMP) fit.chg
|
||||
|
||||
$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt
|
||||
quartus_fit $(PROJECT) $(FIT_ARGS)
|
||||
$(STAMP) asm.chg
|
||||
$(STAMP) sta.chg
|
||||
|
||||
$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt
|
||||
quartus_asm $(PROJECT) $(ASM_ARGS)
|
||||
|
||||
$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt
|
||||
quartus_sta $(PROJECT) $(STA_ARGS)
|
||||
|
||||
smart.log: $(PROJECT_FILES)
|
||||
quartus_sh --determine_smart_action $(PROJECT) > smart.log
|
||||
|
||||
# Project initialization
|
||||
$(PROJECT_FILES):
|
||||
quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "$(RTL_INCLUDE)"
|
||||
# -set "FPU_CVT2"
|
||||
|
||||
syn.chg:
|
||||
$(STAMP) syn.chg
|
||||
|
||||
fit.chg:
|
||||
$(STAMP) fit.chg
|
||||
|
||||
sta.chg:
|
||||
$(STAMP) sta.chg
|
||||
|
||||
asm.chg:
|
||||
$(STAMP) asm.chg
|
||||
|
||||
timing: $(PROJECT_FILES)
|
||||
quartus_sh -t ../../timing-html.tcl -project $(PROJECT)
|
||||
|
||||
program: $(PROJECT).sof
|
||||
quartus_pgm --no_banner --mode=jtag -o "$(PROJECT).sof"
|
||||
|
||||
clean:
|
||||
rm -rf bin *.rpt *.chg *.qsf *.qpf *.qws *.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox
|
||||
@@ -1,86 +0,0 @@
|
||||
PROJECT = VX_pipeline
|
||||
TOP_LEVEL_ENTITY = VX_pipeline
|
||||
SRC_FILE = VX_pipeline.v
|
||||
RTL_DIR = ../../../../rtl
|
||||
THIRD_PARTY_DIR = ../../../../../third_party
|
||||
|
||||
FAMILY = "Arria 10"
|
||||
DEVICE = 10AX115N3F40E2SG
|
||||
FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10
|
||||
|
||||
#FAMILY = "Stratix 10"
|
||||
#DEVICE = 1SX280HN2F43E2VG
|
||||
#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10
|
||||
|
||||
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(THIRD_PARTY_DIR)/fpnew/src;$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src
|
||||
TEX_INCLUDE = $(RTL_DIR)/tex_unit
|
||||
RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(FPU_INCLUDE);$(TEX_INCLUDE)
|
||||
|
||||
PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
|
||||
|
||||
PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
|
||||
|
||||
# Executable Configuration
|
||||
SYN_ARGS = --parallel --read_settings_files=on
|
||||
FIT_ARGS = --parallel --part=$(DEVICE) --read_settings_files=on
|
||||
ASM_ARGS =
|
||||
STA_ARGS = --parallel --do_report_timing
|
||||
|
||||
# Build targets
|
||||
all: $(PROJECT).sta.rpt
|
||||
|
||||
syn: $(PROJECT).syn.rpt
|
||||
|
||||
fit: $(PROJECT).fit.rpt
|
||||
|
||||
asm: $(PROJECT).asm.rpt
|
||||
|
||||
sta: $(PROJECT).sta.rpt
|
||||
|
||||
smart: smart.log
|
||||
|
||||
# Target implementations
|
||||
STAMP = echo done >
|
||||
|
||||
$(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES)
|
||||
quartus_syn $(PROJECT) $(SYN_ARGS)
|
||||
$(STAMP) fit.chg
|
||||
|
||||
$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt
|
||||
quartus_fit $(PROJECT) $(FIT_ARGS)
|
||||
$(STAMP) asm.chg
|
||||
$(STAMP) sta.chg
|
||||
|
||||
$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt
|
||||
quartus_asm $(PROJECT) $(ASM_ARGS)
|
||||
|
||||
$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt
|
||||
quartus_sta $(PROJECT) $(STA_ARGS)
|
||||
|
||||
smart.log: $(PROJECT_FILES)
|
||||
quartus_sh --determine_smart_action $(PROJECT) > smart.log
|
||||
|
||||
# Project initialization
|
||||
$(PROJECT_FILES):
|
||||
quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "$(RTL_INCLUDE)"
|
||||
|
||||
syn.chg:
|
||||
$(STAMP) syn.chg
|
||||
|
||||
fit.chg:
|
||||
$(STAMP) fit.chg
|
||||
|
||||
sta.chg:
|
||||
$(STAMP) sta.chg
|
||||
|
||||
asm.chg:
|
||||
$(STAMP) asm.chg
|
||||
|
||||
timing: $(PROJECT_FILES)
|
||||
quartus_sh -t ../../timing-html.tcl -project $(PROJECT)
|
||||
|
||||
program: $(PROJECT).sof
|
||||
quartus_pgm --no_banner --mode=jtag -o "$(PROJECT).sof"
|
||||
|
||||
clean:
|
||||
rm -rf bin *.rpt *.chg *.qsf *.qpf *.qws *.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox
|
||||
@@ -1,4 +0,0 @@
|
||||
create_clock -name {clk} -period "250 MHz" [get_ports {clk}]
|
||||
|
||||
derive_pll_clocks -create_base_clocks
|
||||
derive_clock_uncertainty
|
||||
@@ -1,72 +0,0 @@
|
||||
PROJECT = VX_shared_mem
|
||||
TOP_LEVEL_ENTITY = VX_shared_mem
|
||||
SRC_FILE = VX_shared_mem.v
|
||||
RTL_DIR = ../../../../rtl
|
||||
|
||||
FAMILY = "Arria 10"
|
||||
DEVICE = 10AX115N3F40E2SG
|
||||
|
||||
RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache
|
||||
PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
|
||||
|
||||
# Executable Configuration
|
||||
SYN_ARGS = --parallel --read_settings_files=on
|
||||
FIT_ARGS = --parallel --part=$(DEVICE) --read_settings_files=on
|
||||
ASM_ARGS =
|
||||
STA_ARGS = --parallel --do_report_timing
|
||||
|
||||
# Build targets
|
||||
all: $(PROJECT).sta.rpt
|
||||
|
||||
syn: $(PROJECT).syn.rpt
|
||||
|
||||
fit: $(PROJECT).fit.rpt
|
||||
|
||||
asm: $(PROJECT).asm.rpt
|
||||
|
||||
sta: $(PROJECT).sta.rpt
|
||||
|
||||
smart: smart.log
|
||||
|
||||
# Target implementations
|
||||
STAMP = echo done >
|
||||
|
||||
$(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES)
|
||||
quartus_syn $(PROJECT) $(SYN_ARGS)
|
||||
$(STAMP) fit.chg
|
||||
|
||||
$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt
|
||||
quartus_fit $(PROJECT) $(FIT_ARGS)
|
||||
$(STAMP) asm.chg
|
||||
$(STAMP) sta.chg
|
||||
|
||||
$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt
|
||||
quartus_asm $(PROJECT) $(ASM_ARGS)
|
||||
|
||||
$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt
|
||||
quartus_sta $(PROJECT) $(STA_ARGS)
|
||||
|
||||
smart.log: $(PROJECT_FILES)
|
||||
quartus_sh --determine_smart_action $(PROJECT) > smart.log
|
||||
|
||||
# Project initialization
|
||||
$(PROJECT_FILES):
|
||||
quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc ../../project.sdc -inc "$(RTL_INCLUDE)"
|
||||
|
||||
syn.chg:
|
||||
$(STAMP) syn.chg
|
||||
|
||||
fit.chg:
|
||||
$(STAMP) fit.chg
|
||||
|
||||
sta.chg:
|
||||
$(STAMP) sta.chg
|
||||
|
||||
asm.chg:
|
||||
$(STAMP) asm.chg
|
||||
|
||||
program: $(PROJECT).sof
|
||||
quartus_pgm --no_banner --mode=jtag -o "$(PROJECT).sof"
|
||||
|
||||
clean:
|
||||
rm -rf bin *.rpt *.chg *.qsf *.qpf *.qws *.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox
|
||||
@@ -1,81 +0,0 @@
|
||||
PROJECT = Core
|
||||
TOP_LEVEL_ENTITY = VX_core
|
||||
SRC_FILE = VX_core.v
|
||||
RTL_DIR = ../../../../rtl
|
||||
THIRD_PARTY_DIR = ../../../../../third_party
|
||||
|
||||
FAMILY = "Arria 10"
|
||||
DEVICE = 10AX115N3F40E2SG
|
||||
FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10
|
||||
|
||||
#FAMILY = "Stratix 10"
|
||||
#DEVICE = 1SX280HN2F43E2VG
|
||||
#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10
|
||||
|
||||
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(THIRD_PARTY_DIR)/fpnew/src;$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src
|
||||
TEX_INCLUDE = $(RTL_DIR)/tex_unit
|
||||
RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;$(FPU_INCLUDE);$(TEX_INCLUDE)
|
||||
|
||||
PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
|
||||
|
||||
# Executable Configuration
|
||||
SYN_ARGS = --parallel --read_settings_files=on
|
||||
FIT_ARGS = --parallel --part=$(DEVICE) --read_settings_files=on
|
||||
ASM_ARGS =
|
||||
STA_ARGS = --parallel --do_report_timing
|
||||
|
||||
# Build targets
|
||||
all: $(PROJECT).sta.rpt
|
||||
|
||||
syn: $(PROJECT).syn.rpt
|
||||
|
||||
fit: $(PROJECT).fit.rpt
|
||||
|
||||
asm: $(PROJECT).asm.rpt
|
||||
|
||||
sta: $(PROJECT).sta.rpt
|
||||
|
||||
smart: smart.log
|
||||
|
||||
# Target implementations
|
||||
STAMP = echo done >
|
||||
|
||||
$(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES)
|
||||
quartus_syn $(PROJECT) $(SYN_ARGS)
|
||||
$(STAMP) fit.chg
|
||||
|
||||
$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt
|
||||
quartus_fit $(PROJECT) $(FIT_ARGS)
|
||||
$(STAMP) asm.chg
|
||||
$(STAMP) sta.chg
|
||||
|
||||
$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt
|
||||
quartus_asm $(PROJECT) $(ASM_ARGS)
|
||||
|
||||
$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt
|
||||
quartus_sta $(PROJECT) $(STA_ARGS)
|
||||
|
||||
smart.log: $(PROJECT_FILES)
|
||||
quartus_sh --determine_smart_action $(PROJECT) > smart.log
|
||||
|
||||
# Project initialization
|
||||
$(PROJECT_FILES):
|
||||
quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "$(RTL_INCLUDE)" -set "EXT_TEX_ENABLE=1"
|
||||
|
||||
syn.chg:
|
||||
$(STAMP) syn.chg
|
||||
|
||||
fit.chg:
|
||||
$(STAMP) fit.chg
|
||||
|
||||
sta.chg:
|
||||
$(STAMP) sta.chg
|
||||
|
||||
asm.chg:
|
||||
$(STAMP) asm.chg
|
||||
|
||||
program: $(PROJECT).sof
|
||||
quartus_pgm --no_banner --mode=jtag -o "$(PROJECT).sof"
|
||||
|
||||
clean:
|
||||
rm -rf bin *.rpt *.chg *.qsf *.qpf *.qws *.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox
|
||||
@@ -1,81 +0,0 @@
|
||||
PROJECT = vortex_afu
|
||||
TOP_LEVEL_ENTITY = vortex_afu
|
||||
SRC_FILE = vortex_afu.sv
|
||||
RTL_DIR = ../../../../rtl
|
||||
THIRD_PARTY_DIR = ../../../../../third_party
|
||||
|
||||
FAMILY = "Arria 10"
|
||||
DEVICE = 10AX115N3F40E2SG
|
||||
FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10
|
||||
|
||||
#FAMILY = "Stratix 10"
|
||||
#DEVICE = 1SX280HN2F43E2VG
|
||||
#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10
|
||||
|
||||
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(THIRD_PARTY_DIR)/fpnew/src;$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src
|
||||
TEX_INCLUDE = $(RTL_DIR)/tex_unit
|
||||
RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;$(RTL_DIR)/afu;$(RTL_DIR)/afu/ccip;$(FPU_INCLUDE);$(TEX_INCLUDE)
|
||||
|
||||
PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
|
||||
|
||||
# Executable Configuration
|
||||
SYN_ARGS = --parallel --read_settings_files=on
|
||||
FIT_ARGS = --parallel --part=$(DEVICE) --read_settings_files=on
|
||||
ASM_ARGS =
|
||||
STA_ARGS = --parallel --do_report_timing
|
||||
|
||||
# Build targets
|
||||
all: $(PROJECT).sta.rpt
|
||||
|
||||
syn: $(PROJECT).syn.rpt
|
||||
|
||||
fit: $(PROJECT).fit.rpt
|
||||
|
||||
asm: $(PROJECT).asm.rpt
|
||||
|
||||
sta: $(PROJECT).sta.rpt
|
||||
|
||||
smart: smart.log
|
||||
|
||||
# Target implementations
|
||||
STAMP = echo done >
|
||||
|
||||
$(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES)
|
||||
quartus_syn $(PROJECT) $(SYN_ARGS)
|
||||
$(STAMP) fit.chg
|
||||
|
||||
$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt
|
||||
quartus_fit $(PROJECT) $(FIT_ARGS)
|
||||
$(STAMP) asm.chg
|
||||
$(STAMP) sta.chg
|
||||
|
||||
$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt
|
||||
quartus_asm $(PROJECT) $(ASM_ARGS)
|
||||
|
||||
$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt
|
||||
quartus_sta $(PROJECT) $(STA_ARGS)
|
||||
|
||||
smart.log: $(PROJECT_FILES)
|
||||
quartus_sh --determine_smart_action $(PROJECT) > smart.log
|
||||
|
||||
# Project initialization
|
||||
$(PROJECT_FILES):
|
||||
quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "$(RTL_INCLUDE)" -set "NOPAE" -set "NUM_CORES=1"
|
||||
|
||||
syn.chg:
|
||||
$(STAMP) syn.chg
|
||||
|
||||
fit.chg:
|
||||
$(STAMP) fit.chg
|
||||
|
||||
sta.chg:
|
||||
$(STAMP) sta.chg
|
||||
|
||||
asm.chg:
|
||||
$(STAMP) asm.chg
|
||||
|
||||
program: $(PROJECT).sof
|
||||
quartus_pgm --no_banner --mode=jtag -o "$(PROJECT).sof"
|
||||
|
||||
clean:
|
||||
rm -rf bin *.rpt *.chg *.qsf *.qpf *.qws *.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox
|
||||
@@ -1,81 +0,0 @@
|
||||
PROJECT = vortex_afu
|
||||
TOP_LEVEL_ENTITY = vortex_afu
|
||||
SRC_FILE = vortex_afu.sv
|
||||
RTL_DIR = ../../../../rtl
|
||||
THIRD_PARTY_DIR = ../../../../../third_party
|
||||
|
||||
FAMILY = "Arria 10"
|
||||
DEVICE = 10AX115N3F40E2SG
|
||||
FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10
|
||||
|
||||
#FAMILY = "Stratix 10"
|
||||
#DEVICE = 1SX280HN2F43E2VG
|
||||
#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10
|
||||
|
||||
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(THIRD_PARTY_DIR)/fpnew/src;$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src
|
||||
TEX_INCLUDE = $(RTL_DIR)/tex_unit
|
||||
RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;$(RTL_DIR)/afu;$(RTL_DIR)/afu/ccip;$(FPU_INCLUDE);$(TEX_INCLUDE)
|
||||
|
||||
PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
|
||||
|
||||
# Executable Configuration
|
||||
SYN_ARGS = --parallel --read_settings_files=on
|
||||
FIT_ARGS = --parallel --part=$(DEVICE) --read_settings_files=on
|
||||
ASM_ARGS =
|
||||
STA_ARGS = --parallel --do_report_timing
|
||||
|
||||
# Build targets
|
||||
all: $(PROJECT).sta.rpt
|
||||
|
||||
syn: $(PROJECT).syn.rpt
|
||||
|
||||
fit: $(PROJECT).fit.rpt
|
||||
|
||||
asm: $(PROJECT).asm.rpt
|
||||
|
||||
sta: $(PROJECT).sta.rpt
|
||||
|
||||
smart: smart.log
|
||||
|
||||
# Target implementations
|
||||
STAMP = echo done >
|
||||
|
||||
$(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES)
|
||||
quartus_syn $(PROJECT) $(SYN_ARGS)
|
||||
$(STAMP) fit.chg
|
||||
|
||||
$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt
|
||||
quartus_fit $(PROJECT) $(FIT_ARGS)
|
||||
$(STAMP) asm.chg
|
||||
$(STAMP) sta.chg
|
||||
|
||||
$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt
|
||||
quartus_asm $(PROJECT) $(ASM_ARGS)
|
||||
|
||||
$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt
|
||||
quartus_sta $(PROJECT) $(STA_ARGS)
|
||||
|
||||
smart.log: $(PROJECT_FILES)
|
||||
quartus_sh --determine_smart_action $(PROJECT) > smart.log
|
||||
|
||||
# Project initialization
|
||||
$(PROJECT_FILES):
|
||||
quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "$(RTL_INCLUDE)" -set "NOPAE" -set "NUM_CORES=4" -set "NUM_CLUSTERS=4" -set "L2_ENABLE=0" -set "L3_ENABLE=1" -set "ICACHE_SIZE=8192" -set "DCACHE_SIZE=8192" -set "L3_CACHE_SIZE=262144"
|
||||
|
||||
syn.chg:
|
||||
$(STAMP) syn.chg
|
||||
|
||||
fit.chg:
|
||||
$(STAMP) fit.chg
|
||||
|
||||
sta.chg:
|
||||
$(STAMP) sta.chg
|
||||
|
||||
asm.chg:
|
||||
$(STAMP) asm.chg
|
||||
|
||||
program: $(PROJECT).sof
|
||||
quartus_pgm --no_banner --mode=jtag -o "$(PROJECT).sof"
|
||||
|
||||
clean:
|
||||
rm -rf bin *.rpt *.chg *.qsf *.qpf *.qws *.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox
|
||||
@@ -1,81 +0,0 @@
|
||||
PROJECT = vortex_afu
|
||||
TOP_LEVEL_ENTITY = vortex_afu
|
||||
SRC_FILE = vortex_afu.sv
|
||||
RTL_DIR = ../../../../rtl
|
||||
THIRD_PARTY_DIR = ../../../../../third_party
|
||||
|
||||
FAMILY = "Arria 10"
|
||||
DEVICE = 10AX115N3F40E2SG
|
||||
FPU_CORE_PATH=$(RTL_DIR)/fp_cores/altera/arria10
|
||||
|
||||
#FAMILY = "Stratix 10"
|
||||
#DEVICE = 1SX280HN2F43E2VG
|
||||
#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10
|
||||
|
||||
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(THIRD_PARTY_DIR)/fpnew/src;$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src
|
||||
TEX_INCLUDE = $(RTL_DIR)/tex_unit
|
||||
RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;$(RTL_DIR)/afu;$(RTL_DIR)/afu/ccip;$(FPU_INCLUDE);$(TEX_INCLUDE)
|
||||
|
||||
PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
|
||||
|
||||
# Executable Configuration
|
||||
SYN_ARGS = --parallel --read_settings_files=on
|
||||
FIT_ARGS = --parallel --part=$(DEVICE) --read_settings_files=on
|
||||
ASM_ARGS =
|
||||
STA_ARGS = --parallel --do_report_timing
|
||||
|
||||
# Build targets
|
||||
all: $(PROJECT).sta.rpt
|
||||
|
||||
syn: $(PROJECT).syn.rpt
|
||||
|
||||
fit: $(PROJECT).fit.rpt
|
||||
|
||||
asm: $(PROJECT).asm.rpt
|
||||
|
||||
sta: $(PROJECT).sta.rpt
|
||||
|
||||
smart: smart.log
|
||||
|
||||
# Target implementations
|
||||
STAMP = echo done >
|
||||
|
||||
$(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES)
|
||||
quartus_syn $(PROJECT) $(SYN_ARGS)
|
||||
$(STAMP) fit.chg
|
||||
|
||||
$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt
|
||||
quartus_fit $(PROJECT) $(FIT_ARGS)
|
||||
$(STAMP) asm.chg
|
||||
$(STAMP) sta.chg
|
||||
|
||||
$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt
|
||||
quartus_asm $(PROJECT) $(ASM_ARGS)
|
||||
|
||||
$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt
|
||||
quartus_sta $(PROJECT) $(STA_ARGS)
|
||||
|
||||
smart.log: $(PROJECT_FILES)
|
||||
quartus_sh --determine_smart_action $(PROJECT) > smart.log
|
||||
|
||||
# Project initialization
|
||||
$(PROJECT_FILES):
|
||||
quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "$(RTL_INCLUDE)" -set "NOPAE" -set "NUM_CORES=2"
|
||||
|
||||
syn.chg:
|
||||
$(STAMP) syn.chg
|
||||
|
||||
fit.chg:
|
||||
$(STAMP) fit.chg
|
||||
|
||||
sta.chg:
|
||||
$(STAMP) sta.chg
|
||||
|
||||
asm.chg:
|
||||
$(STAMP) asm.chg
|
||||
|
||||
program: $(PROJECT).sof
|
||||
quartus_pgm --no_banner --mode=jtag -o "$(PROJECT).sof"
|
||||
|
||||
clean:
|
||||
rm -rf bin *.rpt *.chg *.qsf *.qpf *.qws *.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox
|
||||
@@ -1,81 +0,0 @@
|
||||
PROJECT = vortex_afu
|
||||
TOP_LEVEL_ENTITY = vortex_afu
|
||||
SRC_FILE = vortex_afu.sv
|
||||
RTL_DIR = ../../../../rtl
|
||||
THIRD_PARTY_DIR = ../../../../../third_party
|
||||
|
||||
FAMILY = "Arria 10"
|
||||
DEVICE = 10AX115N3F40E2SG
|
||||
FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10
|
||||
|
||||
#FAMILY = "Stratix 10"
|
||||
#DEVICE = 1SX280HN2F43E2VG
|
||||
#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10
|
||||
|
||||
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(THIRD_PARTY_DIR)/fpnew/src;$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src
|
||||
TEX_INCLUDE = $(RTL_DIR)/tex_unit
|
||||
RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;$(RTL_DIR)/afu;$(RTL_DIR)/afu/ccip;$(FPU_INCLUDE);$(TEX_INCLUDE)
|
||||
|
||||
PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
|
||||
|
||||
# Executable Configuration
|
||||
SYN_ARGS = --parallel --read_settings_files=on
|
||||
FIT_ARGS = --parallel --part=$(DEVICE) --read_settings_files=on
|
||||
ASM_ARGS =
|
||||
STA_ARGS = --parallel --do_report_timing
|
||||
|
||||
# Build targets
|
||||
all: $(PROJECT).sta.rpt
|
||||
|
||||
syn: $(PROJECT).syn.rpt
|
||||
|
||||
fit: $(PROJECT).fit.rpt
|
||||
|
||||
asm: $(PROJECT).asm.rpt
|
||||
|
||||
sta: $(PROJECT).sta.rpt
|
||||
|
||||
smart: smart.log
|
||||
|
||||
# Target implementations
|
||||
STAMP = echo done >
|
||||
|
||||
$(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES)
|
||||
quartus_syn $(PROJECT) $(SYN_ARGS)
|
||||
$(STAMP) fit.chg
|
||||
|
||||
$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt
|
||||
quartus_fit $(PROJECT) $(FIT_ARGS)
|
||||
$(STAMP) asm.chg
|
||||
$(STAMP) sta.chg
|
||||
|
||||
$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt
|
||||
quartus_asm $(PROJECT) $(ASM_ARGS)
|
||||
|
||||
$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt
|
||||
quartus_sta $(PROJECT) $(STA_ARGS)
|
||||
|
||||
smart.log: $(PROJECT_FILES)
|
||||
quartus_sh --determine_smart_action $(PROJECT) > smart.log
|
||||
|
||||
# Project initialization
|
||||
$(PROJECT_FILES):
|
||||
quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "$(RTL_INCLUDE)" -set "NOPAE" -set "NUM_CORES=8" -set "NUM_CLUSTERS=4" -set "L2_ENABLE=0" -set "L3_ENABLE=1" -set "ICACHE_SIZE=8192" -set "DCACHE_SIZE=8192" -set "L3_CACHE_SIZE=262144"
|
||||
|
||||
syn.chg:
|
||||
$(STAMP) syn.chg
|
||||
|
||||
fit.chg:
|
||||
$(STAMP) fit.chg
|
||||
|
||||
sta.chg:
|
||||
$(STAMP) sta.chg
|
||||
|
||||
asm.chg:
|
||||
$(STAMP) asm.chg
|
||||
|
||||
program: $(PROJECT).sof
|
||||
quartus_pgm --no_banner --mode=jtag -o "$(PROJECT).sof"
|
||||
|
||||
clean:
|
||||
rm -rf bin *.rpt *.chg *.qsf *.qpf *.qws *.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox
|
||||
@@ -1,80 +0,0 @@
|
||||
PROJECT = vortex_afu
|
||||
TOP_LEVEL_ENTITY = vortex_afu
|
||||
SRC_FILE = vortex_afu.sv
|
||||
RTL_DIR = ../../../../rtl
|
||||
THIRD_PARTY_DIR = ../../../../../third_party
|
||||
|
||||
FAMILY = "Arria 10"
|
||||
DEVICE = 10AX115N3F40E2SG
|
||||
FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10
|
||||
|
||||
#FAMILY = "Stratix 10"
|
||||
#DEVICE = 1SX280HN2F43E2VG
|
||||
#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10
|
||||
|
||||
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(THIRD_PARTY_DIR)/fpnew/src;$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src
|
||||
TEX_INCLUDE = $(RTL_DIR)/tex_unit
|
||||
RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;$(RTL_DIR)/afu;$(RTL_DIR)/afu/ccip;$(FPU_INCLUDE);$(TEX_INCLUDE)
|
||||
|
||||
PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
|
||||
|
||||
# Executable Configuration
|
||||
SYN_ARGS = --parallel --read_settings_files=on
|
||||
FIT_ARGS = --parallel --part=$(DEVICE) --read_settings_files=on
|
||||
ASM_ARGS =
|
||||
STA_ARGS = --parallel --do_report_timing
|
||||
|
||||
# Build targets
|
||||
all: $(PROJECT).sta.rpt
|
||||
|
||||
syn: $(PROJECT).syn.rpt
|
||||
|
||||
fit: $(PROJECT).fit.rpt
|
||||
|
||||
asm: $(PROJECT).asm.rpt
|
||||
|
||||
sta: $(PROJECT).sta.rpt
|
||||
|
||||
smart: smart.log
|
||||
|
||||
# Target implementations
|
||||
STAMP = echo done >
|
||||
|
||||
$(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES)
|
||||
quartus_syn $(PROJECT) $(SYN_ARGS)
|
||||
$(STAMP) fit.chg
|
||||
|
||||
$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt
|
||||
quartus_fit $(PROJECT) $(FIT_ARGS)
|
||||
$(STAMP) asm.chg
|
||||
$(STAMP) sta.chg
|
||||
|
||||
$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt
|
||||
quartus_asm $(PROJECT) $(ASM_ARGS)
|
||||
|
||||
$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt
|
||||
quartus_sta $(PROJECT) $(STA_ARGS)
|
||||
|
||||
smart.log: $(PROJECT_FILES)
|
||||
quartus_sh --determine_smart_action $(PROJECT) > smart.log
|
||||
|
||||
# Project initialization
|
||||
$(PROJECT_FILES):
|
||||
quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "$(RTL_INCLUDE)" -set "NOPAE" -set "NUM_CORES=4" -set "NUM_CLUSTERS=1" -set "L2_ENABLE=1" -set "L3_ENABLE=0" -set "ICACHE_SIZE=8192" -set "DCACHE_SIZE=8192" -set "L2_CACHE_SIZE=65536"
|
||||
syn.chg:
|
||||
$(STAMP) syn.chg
|
||||
|
||||
fit.chg:
|
||||
$(STAMP) fit.chg
|
||||
|
||||
sta.chg:
|
||||
$(STAMP) sta.chg
|
||||
|
||||
asm.chg:
|
||||
$(STAMP) asm.chg
|
||||
|
||||
program: $(PROJECT).sof
|
||||
quartus_pgm --no_banner --mode=jtag -o "$(PROJECT).sof"
|
||||
|
||||
clean:
|
||||
rm -rf bin *.rpt *.chg *.qsf *.qpf *.qws *.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox
|
||||
@@ -1,81 +0,0 @@
|
||||
PROJECT = vortex_afu
|
||||
TOP_LEVEL_ENTITY = vortex_afu
|
||||
SRC_FILE = vortex_afu.sv
|
||||
RTL_DIR = ../../../../rtl
|
||||
THIRD_PARTY_DIR = ../../../../../third_party
|
||||
|
||||
#FAMILY = "Arria 10"
|
||||
#DEVICE = 10AX115N3F40E2SG
|
||||
#FPU_CORE_PATH=$(RTL_DIR)/fp_cores/altera/arria10
|
||||
|
||||
FAMILY = "Stratix 10"
|
||||
DEVICE = 1SX280HN2F43E2VG
|
||||
FPU_CORE_PATH=$(RTL_DIR)/fp_cores/altera/stratix10
|
||||
|
||||
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(THIRD_PARTY_DIR)/fpnew/src;$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src
|
||||
TEX_INCLUDE = $(RTL_DIR)/tex_unit
|
||||
RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;$(RTL_DIR)/afu;$(RTL_DIR)/afu/ccip;$(FPU_INCLUDE);$(TEX_INCLUDE)
|
||||
|
||||
PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
|
||||
|
||||
# Executable Configuration
|
||||
SYN_ARGS = --parallel --read_settings_files=on
|
||||
FIT_ARGS = --parallel --part=$(DEVICE) --read_settings_files=on
|
||||
ASM_ARGS =
|
||||
STA_ARGS = --parallel --do_report_timing
|
||||
|
||||
# Build targets
|
||||
all: $(PROJECT).sta.rpt
|
||||
|
||||
syn: $(PROJECT).syn.rpt
|
||||
|
||||
fit: $(PROJECT).fit.rpt
|
||||
|
||||
asm: $(PROJECT).asm.rpt
|
||||
|
||||
sta: $(PROJECT).sta.rpt
|
||||
|
||||
smart: smart.log
|
||||
|
||||
# Target implementations
|
||||
STAMP = echo done >
|
||||
|
||||
$(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES)
|
||||
quartus_syn $(PROJECT) $(SYN_ARGS)
|
||||
$(STAMP) fit.chg
|
||||
|
||||
$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt
|
||||
quartus_fit $(PROJECT) $(FIT_ARGS)
|
||||
$(STAMP) asm.chg
|
||||
$(STAMP) sta.chg
|
||||
|
||||
$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt
|
||||
quartus_asm $(PROJECT) $(ASM_ARGS)
|
||||
|
||||
$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt
|
||||
quartus_sta $(PROJECT) $(STA_ARGS)
|
||||
|
||||
smart.log: $(PROJECT_FILES)
|
||||
quartus_sh --determine_smart_action $(PROJECT) > smart.log
|
||||
|
||||
# Project initialization
|
||||
$(PROJECT_FILES):
|
||||
quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "$(RTL_INCLUDE)" -set "NOPAE" -set "NUM_CORES=8" -set "NUM_CLUSTERS=8" -set "L2_ENABLE=0" -set "L3_ENABLE=1" -set "ICACHE_SIZE=8192" -set "DCACHE_SIZE=8192" -set "L3_CACHE_SIZE=524288"
|
||||
|
||||
syn.chg:
|
||||
$(STAMP) syn.chg
|
||||
|
||||
fit.chg:
|
||||
$(STAMP) fit.chg
|
||||
|
||||
sta.chg:
|
||||
$(STAMP) sta.chg
|
||||
|
||||
asm.chg:
|
||||
$(STAMP) asm.chg
|
||||
|
||||
program: $(PROJECT).sof
|
||||
quartus_pgm --no_banner --mode=jtag -o "$(PROJECT).sof"
|
||||
|
||||
clean:
|
||||
rm -rf bin *.rpt *.chg *.qsf *.qpf *.qws *.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox
|
||||
@@ -1,81 +0,0 @@
|
||||
PROJECT = vortex_afu
|
||||
TOP_LEVEL_ENTITY = vortex_afu
|
||||
SRC_FILE = vortex_afu.sv
|
||||
RTL_DIR = ../../../../rtl
|
||||
THIRD_PARTY_DIR = ../../../../../third_party
|
||||
|
||||
FAMILY = "Arria 10"
|
||||
DEVICE = 10AX115N3F40E2SG
|
||||
FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10
|
||||
|
||||
#FAMILY = "Stratix 10"
|
||||
#DEVICE = 1SX280HN2F43E2VG
|
||||
#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10
|
||||
|
||||
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(THIRD_PARTY_DIR)/fpnew/src;$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src
|
||||
TEX_INCLUDE = $(RTL_DIR)/tex_unit
|
||||
RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;$(RTL_DIR)/afu;$(RTL_DIR)/afu/ccip;$(FPU_INCLUDE);$(TEX_INCLUDE)
|
||||
|
||||
PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
|
||||
|
||||
# Executable Configuration
|
||||
SYN_ARGS = --parallel --read_settings_files=on
|
||||
FIT_ARGS = --parallel --part=$(DEVICE) --read_settings_files=on
|
||||
ASM_ARGS =
|
||||
STA_ARGS = --parallel --do_report_timing
|
||||
|
||||
# Build targets
|
||||
all: $(PROJECT).sta.rpt
|
||||
|
||||
syn: $(PROJECT).syn.rpt
|
||||
|
||||
fit: $(PROJECT).fit.rpt
|
||||
|
||||
asm: $(PROJECT).asm.rpt
|
||||
|
||||
sta: $(PROJECT).sta.rpt
|
||||
|
||||
smart: smart.log
|
||||
|
||||
# Target implementations
|
||||
STAMP = echo done >
|
||||
|
||||
$(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES)
|
||||
quartus_syn $(PROJECT) $(SYN_ARGS)
|
||||
$(STAMP) fit.chg
|
||||
|
||||
$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt
|
||||
quartus_fit $(PROJECT) $(FIT_ARGS)
|
||||
$(STAMP) asm.chg
|
||||
$(STAMP) sta.chg
|
||||
|
||||
$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt
|
||||
quartus_asm $(PROJECT) $(ASM_ARGS)
|
||||
|
||||
$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt
|
||||
quartus_sta $(PROJECT) $(STA_ARGS)
|
||||
|
||||
smart.log: $(PROJECT_FILES)
|
||||
quartus_sh --determine_smart_action $(PROJECT) > smart.log
|
||||
|
||||
# Project initialization
|
||||
$(PROJECT_FILES):
|
||||
quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "$(RTL_INCLUDE)" -set "NOPAE" -set "NUM_CORES=8" -set "NUM_CLUSTERS=1" -set "L2_ENABLE=1" -set "L3_ENABLE=0" -set "ICACHE_SIZE=8192" -set "DCACHE_SIZE=8192" -set "L2_CACHE_SIZE=131072"
|
||||
|
||||
syn.chg:
|
||||
$(STAMP) syn.chg
|
||||
|
||||
fit.chg:
|
||||
$(STAMP) fit.chg
|
||||
|
||||
sta.chg:
|
||||
$(STAMP) sta.chg
|
||||
|
||||
asm.chg:
|
||||
$(STAMP) asm.chg
|
||||
|
||||
program: $(PROJECT).sof
|
||||
quartus_pgm --no_banner --mode=jtag -o "$(PROJECT).sof"
|
||||
|
||||
clean:
|
||||
rm -rf bin *.rpt *.chg *.qsf *.qpf *.qws *.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox
|
||||
@@ -1,81 +0,0 @@
|
||||
PROJECT = Unittest
|
||||
TOP_LEVEL_ENTITY = VX_core_req_bank_sel
|
||||
SRC_FILE = VX_core_req_bank_sel.v
|
||||
RTL_DIR = ../../../../rtl
|
||||
THIRD_PARTY_DIR = ../../../../../third_party
|
||||
|
||||
FAMILY = "Arria 10"
|
||||
DEVICE = 10AX115N3F40E2SG
|
||||
FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10
|
||||
|
||||
#FAMILY = "Stratix 10"
|
||||
#DEVICE = 1SX280HN2F43E2VG
|
||||
#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10
|
||||
|
||||
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(THIRD_PARTY_DIR)/fpnew/src;$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src
|
||||
TEX_INCLUDE = $(RTL_DIR)/tex_unit
|
||||
RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;$(FPU_INCLUDE);$(TEX_INCLUDE)
|
||||
|
||||
PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
|
||||
|
||||
# Executable Configuration
|
||||
SYN_ARGS = --parallel --read_settings_files=on
|
||||
FIT_ARGS = --parallel --part=$(DEVICE) --read_settings_files=on
|
||||
ASM_ARGS =
|
||||
STA_ARGS = --parallel --do_report_timing
|
||||
|
||||
# Build targets
|
||||
all: $(PROJECT).sta.rpt
|
||||
|
||||
syn: $(PROJECT).syn.rpt
|
||||
|
||||
fit: $(PROJECT).fit.rpt
|
||||
|
||||
asm: $(PROJECT).asm.rpt
|
||||
|
||||
sta: $(PROJECT).sta.rpt
|
||||
|
||||
smart: smart.log
|
||||
|
||||
# Target implementations
|
||||
STAMP = echo done >
|
||||
|
||||
$(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES)
|
||||
quartus_syn $(PROJECT) $(SYN_ARGS)
|
||||
$(STAMP) fit.chg
|
||||
|
||||
$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt
|
||||
quartus_fit $(PROJECT) $(FIT_ARGS)
|
||||
$(STAMP) asm.chg
|
||||
$(STAMP) sta.chg
|
||||
|
||||
$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt
|
||||
quartus_asm $(PROJECT) $(ASM_ARGS)
|
||||
|
||||
$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt
|
||||
quartus_sta $(PROJECT) $(STA_ARGS)
|
||||
|
||||
smart.log: $(PROJECT_FILES)
|
||||
quartus_sh --determine_smart_action $(PROJECT) > smart.log
|
||||
|
||||
# Project initialization
|
||||
$(PROJECT_FILES):
|
||||
quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "$(RTL_INCLUDE)"
|
||||
|
||||
syn.chg:
|
||||
$(STAMP) syn.chg
|
||||
|
||||
fit.chg:
|
||||
$(STAMP) fit.chg
|
||||
|
||||
sta.chg:
|
||||
$(STAMP) sta.chg
|
||||
|
||||
asm.chg:
|
||||
$(STAMP) asm.chg
|
||||
|
||||
program: $(PROJECT).sof
|
||||
quartus_pgm --no_banner --mode=jtag -o "$(PROJECT).sof"
|
||||
|
||||
clean:
|
||||
rm -rf bin *.rpt *.chg *.qsf *.qpf *.qws *.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox
|
||||
@@ -1,81 +0,0 @@
|
||||
PROJECT = Vortex
|
||||
TOP_LEVEL_ENTITY = Vortex
|
||||
SRC_FILE = Vortex.sv
|
||||
RTL_DIR = ../../../../rtl
|
||||
THIRD_PARTY_DIR = ../../../../../third_party
|
||||
|
||||
FAMILY = "Arria 10"
|
||||
DEVICE = 10AX115N3F40E2SG
|
||||
FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10
|
||||
|
||||
#FAMILY = "Stratix 10"
|
||||
#DEVICE = 1SX280HN2F43E2VG
|
||||
#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10
|
||||
|
||||
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(THIRD_PARTY_DIR)/fpnew/src;$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src
|
||||
TEX_INCLUDE = $(RTL_DIR)/tex_unit
|
||||
RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;$(FPU_INCLUDE);$(TEX_INCLUDE)
|
||||
|
||||
PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
|
||||
|
||||
# Executable Configuration
|
||||
SYN_ARGS = --parallel --read_settings_files=on
|
||||
FIT_ARGS = --parallel --part=$(DEVICE) --read_settings_files=on
|
||||
ASM_ARGS =
|
||||
STA_ARGS = --parallel --do_report_timing
|
||||
|
||||
# Build targets
|
||||
all: $(PROJECT).sta.rpt
|
||||
|
||||
syn: $(PROJECT).syn.rpt
|
||||
|
||||
fit: $(PROJECT).fit.rpt
|
||||
|
||||
asm: $(PROJECT).asm.rpt
|
||||
|
||||
sta: $(PROJECT).sta.rpt
|
||||
|
||||
smart: smart.log
|
||||
|
||||
# Target implementations
|
||||
STAMP = echo done >
|
||||
|
||||
$(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES)
|
||||
quartus_syn $(PROJECT) $(SYN_ARGS)
|
||||
$(STAMP) fit.chg
|
||||
|
||||
$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt
|
||||
quartus_fit $(PROJECT) $(FIT_ARGS)
|
||||
$(STAMP) asm.chg
|
||||
$(STAMP) sta.chg
|
||||
|
||||
$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt
|
||||
quartus_asm $(PROJECT) $(ASM_ARGS)
|
||||
|
||||
$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt
|
||||
quartus_sta $(PROJECT) $(STA_ARGS)
|
||||
|
||||
smart.log: $(PROJECT_FILES)
|
||||
quartus_sh --determine_smart_action $(PROJECT) > smart.log
|
||||
|
||||
# Project initialization
|
||||
$(PROJECT_FILES):
|
||||
quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "$(RTL_INCLUDE)"
|
||||
|
||||
syn.chg:
|
||||
$(STAMP) syn.chg
|
||||
|
||||
fit.chg:
|
||||
$(STAMP) fit.chg
|
||||
|
||||
sta.chg:
|
||||
$(STAMP) sta.chg
|
||||
|
||||
asm.chg:
|
||||
$(STAMP) asm.chg
|
||||
|
||||
program: $(PROJECT).sof
|
||||
quartus_pgm --no_banner --mode=jtag -o "$(PROJECT).sof"
|
||||
|
||||
clean:
|
||||
rm -rf bin *.rpt *.chg *.qsf *.qpf *.qws *.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox
|
||||
@@ -1,3 +1,16 @@
|
||||
# Copyright © 2019-2023
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
set search_path [concat ../../models/memory/cln28hpm/rf2_128x128_wm1 ../../models/memory/cln28hpm/rf2_256x128_wm1 ../../models/memory/cln28hpm/rf2_256_19_wm0 ../../models/memory/cln28hpm/rf2_32x128_wm1 ../../rtl/ ../../rtl/interfaces ../../rtl/pipe_regs ../../rtl/shared_memory ../../rtl/cache]
|
||||
set link_library [concat NanGate_15nm_OCL.db]
|
||||
set symbol_library {}
|
||||
|
||||
@@ -1,3 +1,16 @@
|
||||
// Copyright © 2019-2023
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
|
||||
|
||||
#include "Vrf2_32x128_wm1_rtl.h"
|
||||
|
||||
@@ -1,3 +1,16 @@
|
||||
// Copyright © 2019-2023
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
|
||||
|
||||
@@ -1,3 +1,16 @@
|
||||
# Copyright © 2019-2023
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
set SOURCE_FILES [glob *.lib]
|
||||
foreach FILE ${SOURCE_FILES} {
|
||||
read_lib $FILE
|
||||
|
||||
@@ -1,3 +1,16 @@
|
||||
// Copyright © 2019-2023
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
|
||||
|
||||
@@ -1,4 +1,18 @@
|
||||
#!/bin/bash
|
||||
|
||||
# Copyright © 2019-2023
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
set top_level = Vortex
|
||||
|
||||
source /tools/synopsys/synthesis/j201409/cshrc.syn
|
||||
|
||||
@@ -1,3 +1,16 @@
|
||||
# Copyright © 2019-2023
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
set search_path [concat /nethome/dshim8/Desktop/GTCAD-3DPKG-v3/example/tech/cln28hpm/2d_db/ /nethome/dshim8/Desktop/GTCAD-3DPKG-v3/example/tech/cln28hpm/2d_hard_db/ ../../rtl/ ../../rtl/interfaces ../../rtl/pipe_regs ../../rtl/shared_memory ../../rtl/cache ../../models/memory/cln28hpm/2d_hardmacro_db]
|
||||
set link_library [concat * sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c.db rf2_32x128_wm1_ss_0p81v_0p81v_m40c.db rf2_256x128_wm1_ss_0p81v_0p81v_m40c.db rf2_256x19_wm0_ss_0p81v_0p81v_m40c.db rf2_128x128_wm1_ss_0p81v_0p81v_m40c.db dw_foundation.sldb]
|
||||
set symbol_library {}
|
||||
|
||||
73
hw/syn/xilinx/NOTEBOOK
Normal file
73
hw/syn/xilinx/NOTEBOOK
Normal file
@@ -0,0 +1,73 @@
|
||||
## Xilinx synthesis Notebook
|
||||
|
||||
# check installed FPGAs
|
||||
platforminfo -l
|
||||
|
||||
# check FPGA status
|
||||
xbutil validate --device 0000:09:00.1 --verbose
|
||||
|
||||
# generate FPU IPs
|
||||
vivado -mode batch -source scripts/gen_ip.tcl -tclargs ip/xilinx_u50_gen3x16_xdma_5_202210_1
|
||||
|
||||
# build FPGA
|
||||
PREFIX=build_base_1c NUM_CORES=1 TARGET=hw_emu PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 make > build_u50_hw_emu_base_1c.log 2>&1 &
|
||||
PREFIX=build_base_1c NUM_CORES=1 TARGET=hw PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 make > build_u50_hw_base_1c.log 2>&1 &
|
||||
|
||||
PREFIX=build_gfx_1c NUM_CORES=1 TARGET=hw_emu PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 CONFIGS="-DEXT_GFX_ENABLE" make > build_u50_hw_emu_gfx_1c.log 2>&1 &
|
||||
PREFIX=build_gfx_1c NUM_CORES=1 TARGET=hw PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 CONFIGS="-DEXT_GFX_ENABLE" make > build_u50_hw_gfx_1c.log 2>&1 &
|
||||
|
||||
PREFIX=build_gfx_dbg_1c DEBUG=3 NUM_CORES=1 TARGET=hw_emu PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 CONFIGS="-DEXT_GFX_ENABLE" make > build_u50_hw_emu_gfx_dbg_1c.log 2>&1 &
|
||||
PREFIX=build_gfx_dbg_1c DEBUG=3 NUM_CORES=1 TARGET=hw PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 CONFIGS="-DEXT_GFX_ENABLE" make > build_u50_hw_gfx_dbg_1c.log 2>&1 &
|
||||
|
||||
PREFIX=build_base_2c NUM_CORES=2 TARGET=hw_emu PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 make > build_u50_hw_emu_base_2c.log 2>&1 &
|
||||
PREFIX=build_base_2c NUM_CORES=2 TARGET=hw PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 make > build_u50_hw_base_2c.log 2>&1 &
|
||||
|
||||
PREFIX=build_gfx_2c NUM_CORES=2 TARGET=hw_emu PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 CONFIGS="-DEXT_GFX_ENABLE" make > build_u50_hw_emu_gfx_2c.log 2>&1 &
|
||||
PREFIX=build_gfx_2c NUM_CORES=2 TARGET=hw PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 CONFIGS="-DEXT_GFX_ENABLE" make > build_u50_hw_gfx_2c.log 2>&1 &
|
||||
|
||||
PREFIX=build_gfx_dbg_1c DEBUG=3 NUM_CORES=1 TARGET=hw_emu PLATFORM=xilinx_u280_gen3x16_xdma_1_202211_1 CONFIGS="-DEXT_GFX_ENABLE" make > build_u280_hw_emu_gfx_dbg_1c.log 2>&1 &
|
||||
PREFIX=build_gfx_dbg_1c DEBUG=3 NUM_CORES=1 TARGET=hw PLATFORM=xilinx_u280_gen3x16_xdma_1_202211_1 CONFIGS="-DEXT_GFX_ENABLE" make > build_u280_hw_gfx_dbg_1c.log 2>&1 &
|
||||
PREFIX=build_dbg_1c DEBUG=3 NUM_CORES=1 TARGET=hw_emu PLATFORM=xilinx_u280_gen3x16_xdma_1_202211_1 make > build_u280_hw_emu_dbg_1c.log 2>&1 &
|
||||
PREFIX=build_dbg_1c DEBUG=3 NUM_CORES=1 TARGET=hw PLATFORM=xilinx_u280_gen3x16_xdma_1_202211_1 make > build_u280_hw_dbg_1c.log 2>&1 &
|
||||
PREFIX=build_base_1c NUM_CORES=1 TARGET=hw_emu PLATFORM=xilinx_u280_gen3x16_xdma_1_202211_1 make > build_u280_hw_emu_base_1c.log 2>&1 &
|
||||
PREFIX=build_base_1c NUM_CORES=1 TARGET=hw PLATFORM=xilinx_u280_gen3x16_xdma_1_202211_1 make > build_u280_hw_base_1c.log 2>&1 &
|
||||
PREFIX=build_gfx_1c NUM_CORES=1 TARGET=hw_emu PLATFORM=xilinx_u280_gen3x16_xdma_1_202211_1 CONFIGS="-DEXT_GFX_ENABLE" make > build_u280_hw_emu_gfx_1c.log 2>&1 &
|
||||
PREFIX=build_gfx_1c NUM_CORES=1 TARGET=hw PLATFORM=xilinx_u280_gen3x16_xdma_1_202211_1 CONFIGS="-DEXT_GFX_ENABLE" make > build_u280_hw_gfx_1c.log 2>&1 &
|
||||
|
||||
PREFIX=build TARGET=hw_emu PLATFORM=xilinx_vck5000_gen3x16_xdma_1_202120_1 make > build_vck5k_hw_emu.log 2>&1 &
|
||||
PREFIX=build TARGET=hw_emu PLATFORM=xilinx_vck5000_gen3x16_xdma_1_202120_1 make > build_vck5k_hw.log 2>&1 &
|
||||
|
||||
# debug hw_emu using xsim
|
||||
xsim --gui xilinx_u50_gen3x16_xdma_5_202210_1-0-vortex_afu.wdb &
|
||||
|
||||
# debug hw using ILA
|
||||
platforminfo --json="hardwarePlatform.extensions.chipscope_debug" xilinx_u50_gen3x16_xdma_5_202210_1
|
||||
ls /dev/xfpga/xvc_pub*
|
||||
ls /dev/xvc_pub*
|
||||
debug_hw --xvc_pcie /dev/xfpga/xvc_pub.u2305.0 --hw_server
|
||||
debug_hw --xvc_pcie /dev/xvc_pub.u0 --hw_server
|
||||
debug_hw --vivado --host localhost --ltx_file ./build_xilinx_u50_gen3x16_xdma_5_202210_1_hw/_x/link/vivado/vpl/prj/prj.runs/impl_1/debug_nets.ltx &
|
||||
make chipscope TARGET=hw PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1
|
||||
|
||||
# analyze build report
|
||||
vitis_analyzer build_xilinx_u50_gen3x16_xdma_5_202210_1_hw_4c/bin/vortex_afu.xclbin.link_summary
|
||||
|
||||
# running test
|
||||
TARGET=hw PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 ./ci/blackbox.sh --driver=xrt --app=demo
|
||||
TARGET=hw_emu PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 ./ci/blackbox.sh --driver=xrt --app=demo
|
||||
TARGET=hw PLATFORM=xilinx_vck5000_gen3x16_xdma_1_202120_1 ./ci/blackbox.sh --driver=xrt --app=demo
|
||||
TARGET=hw_emu PLATFORM=xilinx_vck5000_gen3x16_xdma_1_202120_1 ./ci/blackbox.sh --driver=xrt --app=demo
|
||||
FPGA_BIN_DIR=<bin_dir> TARGET=hw_emu PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 ./ci/blackbox.sh --driver=xrt --app=demo
|
||||
FPGA_BIN_DIR=<bin_dir> TARGET=hw PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 ./ci/blackbox.sh --driver=xrt --app=demo
|
||||
FPGA_BIN_DIR=<bin_dir> TARGET=hw_emu PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 ./ci/blackbox.sh --driver=xrt --app=draw3d --args="-tbox.cgltrace -rbox_ref_128.png"
|
||||
FPGA_BIN_DIR=<bin_dir> TARGET=hw PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 ./ci/blackbox.sh --driver=xrt --app=draw3d --args="-tbox.cgltrace -rbox_ref_128.png"
|
||||
FPGA_BIN_DIR=<bin_dir> TARGET=hw_emu PLATFORM=xilinx_u280_gen3x16_xdma_1_202211_1 ./ci/blackbox.sh --driver=xrt --app=demo
|
||||
FPGA_BIN_DIR=<bin_dir> XRT_DEVICE_INDEX=1 TARGET=hw PLATFORM=xilinx_u280_gen3x16_xdma_1_202211_1 ./ci/blackbox.sh --driver=xrt --app=demo
|
||||
FPGA_BIN_DIR=<bin_dir> TARGET=hw_emu PLATFORM=xilinx_u280_gen3x16_xdma_1_202211_1 ./ci/blackbox.sh --driver=xrt --app=draw3d --args="-tbox.cgltrace -rbox_ref_128.png"
|
||||
FPGA_BIN_DIR=<bin_dir> XRT_DEVICE_INDEX=1 TARGET=hw PLATFORM=xilinx_u280_gen3x16_xdma_1_202211_1 ./ci/blackbox.sh --driver=xrt --app=draw3d --args="-tbox.cgltrace -rbox_ref_128.png"
|
||||
|
||||
# build report logs
|
||||
<build_dir>/bin/vortex_afu.xclbin.info
|
||||
<build_dir>/_x/reports/link/link/imp/impl_1_full_util_routed.rpt
|
||||
<build_dir>/_x/reports/link/imp/impl_1_hw_bb_locked_timing_summary_routed.rpt # search for keyword "VIOLATED"
|
||||
<build_dir>/_x/logs/link/syn/ulp_vortex_afu_1_0_synth_1_runme.log
|
||||
2
hw/syn/xilinx/test/.gitignore
vendored
Normal file
2
hw/syn/xilinx/test/.gitignore
vendored
Normal file
@@ -0,0 +1,2 @@
|
||||
/project_1/*
|
||||
/.Xil/*
|
||||
49
hw/syn/xilinx/test/Makefile
Normal file
49
hw/syn/xilinx/test/Makefile
Normal file
@@ -0,0 +1,49 @@
|
||||
VIVADO = $(XILINX_VIVADO)/bin/vivado
|
||||
|
||||
RTL_DIR = ../../../rtl
|
||||
AFU_DIR = $(RTL_DIR)/afu/xrt
|
||||
SCRIPT_DIR = ../../../scripts
|
||||
THIRD_PARTY_DIR = ../../../../third_party
|
||||
|
||||
# include paths
|
||||
FPU_INCLUDE = -I$(RTL_DIR)/fpu
|
||||
ifneq (,$(findstring FPU_FPNEW,$(CONFIGS)))
|
||||
FPU_INCLUDE += -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -I$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(THIRD_PARTY_DIR)/fpnew/src
|
||||
endif
|
||||
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache
|
||||
RTL_INCLUDE += $(FPU_INCLUDE)
|
||||
RTL_INCLUDE += -Iproject_1_files
|
||||
|
||||
# compilation flags
|
||||
CFLAGS += -DNDEBUG -DSYNTHESIS -DVIVADO
|
||||
CFLAGS += $(CONFIGS)
|
||||
CFLAGS += $(RTL_INCLUDE)
|
||||
CFLAGS += -DEXT_F_DISABLE
|
||||
#CFLAGS += -DNUM_CORES 4
|
||||
|
||||
# update memory layout for 2MB RAM
|
||||
CFLAGS += -DSTARTUP_ADDR=32\'h80000
|
||||
CFLAGS += -DIO_BASE_ADDR=32\'hFF000
|
||||
|
||||
COE_FILE := $(realpath project_1_files)/kernel.bin.coe
|
||||
ESCAPED_COE_FILE := $(shell echo "$(COE_FILE)" | sed -e 's/[\/&]/\\&/g')
|
||||
|
||||
all: build
|
||||
|
||||
gen-sources: project_1/sources.txt
|
||||
project_1/sources.txt:
|
||||
mkdir -p project_1
|
||||
$(SCRIPT_DIR)/gen_sources.sh $(CFLAGS) -P -Cproject_1/src -Oproject_1/sources.txt
|
||||
|
||||
project.tcl: project.tcl.in
|
||||
sed -e 's/%COE_FILE%/$(ESCAPED_COE_FILE)/g' < $< > $@
|
||||
|
||||
build: project_1/vortex.xpr
|
||||
project_1/vortex.xpr: project_1/sources.txt project.tcl
|
||||
$(VIVADO) -mode batch -source project.tcl -tclargs project_1/sources.txt project_1/src $(SCRIPT_DIR)
|
||||
|
||||
run: project_1/vortex.xpr
|
||||
$(VIVADO) project_1/vortex.xpr &
|
||||
|
||||
clean:
|
||||
rm -rf project_1 project.tcl
|
||||
51
hw/syn/xilinx/test/kernel/Makefile
Normal file
51
hw/syn/xilinx/test/kernel/Makefile
Normal file
@@ -0,0 +1,51 @@
|
||||
XLEN ?= 32
|
||||
|
||||
ifeq ($(XLEN),64)
|
||||
RISCV_TOOLCHAIN_PATH ?= /opt/riscv64-gnu-toolchain
|
||||
CFLAGS += -march=rv64imafd -mabi=lp64d
|
||||
else
|
||||
RISCV_TOOLCHAIN_PATH ?= /opt/riscv-gnu-toolchain
|
||||
CFLAGS += -march=rv32imaf -mabi=ilp32f
|
||||
endif
|
||||
|
||||
RISCV_PREFIX ?= riscv$(XLEN)-unknown-elf
|
||||
|
||||
VORTEX_RT_PATH ?= $(realpath ../../../../../kernel)
|
||||
BIN2COE_PATH ?= ../../../../../../bin2coe
|
||||
|
||||
CC = $(RISCV_TOOLCHAIN_PATH)/bin/$(RISCV_PREFIX)-gcc
|
||||
AR = $(RISCV_TOOLCHAIN_PATH)/bin/$(RISCV_PREFIX)-gcc-ar
|
||||
DP = $(RISCV_TOOLCHAIN_PATH)/bin/$(RISCV_PREFIX)-objdump
|
||||
CP = $(RISCV_TOOLCHAIN_PATH)/bin/$(RISCV_PREFIX)-objcopy
|
||||
|
||||
CFLAGS += -O3 -Wstack-usage=1024 -ffreestanding -nostartfiles -fdata-sections -ffunction-sections
|
||||
CFLAGS += -I$(VORTEX_RT_PATH)/include -I$(VORTEX_RT_PATH)/../hw
|
||||
|
||||
LDFLAGS += -lm -Wl,-Bstatic,-T,$(VORTEX_RT_PATH)/linker/vx_link$(XLEN).ld,--defsym=STARTUP_ADDR=0x80000000
|
||||
|
||||
PROJECT = kernel
|
||||
|
||||
SRCS = main.c start.S
|
||||
|
||||
all: $(PROJECT).elf $(PROJECT).hex $(PROJECT).bin $(PROJECT).dump $(PROJECT).bin.coe
|
||||
|
||||
$(PROJECT).dump: $(PROJECT).elf
|
||||
$(DP) -D $(PROJECT).elf > $(PROJECT).dump
|
||||
|
||||
$(PROJECT).hex: $(PROJECT).elf
|
||||
$(CP) -O ihex $(PROJECT).elf $(PROJECT).hex
|
||||
|
||||
$(PROJECT).bin: $(PROJECT).elf
|
||||
$(CP) -O binary $(PROJECT).elf $(PROJECT).bin
|
||||
|
||||
$(PROJECT).bin.coe: $(PROJECT).bin
|
||||
$(BIN2COE_PATH)/bin2coe $(PROJECT).bin --out=$(PROJECT).bin.coe --binary=$(PROJECT).bin --data=$(PROJECT).dat --binaddr=8192 --depth=16384 --wordsize=64
|
||||
|
||||
$(PROJECT).elf: $(SRCS)
|
||||
$(CC) $(CFLAGS) $(SRCS) $(LDFLAGS) -o $(PROJECT).elf
|
||||
|
||||
.depend: $(SRCS)
|
||||
$(CC) $(CFLAGS) -MM $^ > .depend;
|
||||
|
||||
clean:
|
||||
rm -rf *.bin *.elf *.hex *.dump *.coe .depend
|
||||
3
hw/syn/xilinx/test/kernel/kernel.dat
Normal file
3
hw/syn/xilinx/test/kernel/kernel.dat
Normal file
@@ -0,0 +1,3 @@
|
||||
@1
|
||||
000000C00000008000000002,
|
||||
00000003000000020000000100000000,
|
||||
38
hw/syn/xilinx/test/kernel/main.c
Normal file
38
hw/syn/xilinx/test/kernel/main.c
Normal file
@@ -0,0 +1,38 @@
|
||||
// Copyright © 2019-2023
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#include <stdint.h>
|
||||
#include <vx_intrinsics.h>
|
||||
|
||||
#define KERNEL_ARG_DEV_MEM_ADDR 0x40
|
||||
|
||||
typedef struct {
|
||||
uint32_t count;
|
||||
uint32_t src_addr;
|
||||
uint32_t dst_addr;
|
||||
} kernel_arg_t;
|
||||
|
||||
int main() {
|
||||
kernel_arg_t* arg = (kernel_arg_t*)KERNEL_ARG_DEV_MEM_ADDR;
|
||||
uint32_t count = arg->count;
|
||||
int32_t* src_ptr = (int32_t*)arg->src_addr;
|
||||
int32_t* dst_ptr = (int32_t*)arg->dst_addr;
|
||||
|
||||
uint32_t offset = vx_core_id() * count;
|
||||
|
||||
for (uint32_t i = 0; i < count; ++i) {
|
||||
dst_ptr[offset + i] = src_ptr[offset + i];
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
23
hw/syn/xilinx/test/kernel/start.S
Normal file
23
hw/syn/xilinx/test/kernel/start.S
Normal file
@@ -0,0 +1,23 @@
|
||||
// Copyright © 2019-2023
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
.section .init, "ax"
|
||||
.global _start
|
||||
.type _start, @function
|
||||
_start:
|
||||
# call main routine
|
||||
call main
|
||||
|
||||
# end execution
|
||||
.insn r 0x0b, 0, 0, x0, x0, x0
|
||||
.size _start, .-_start
|
||||
2228
hw/syn/xilinx/test/project.tcl.in
Normal file
2228
hw/syn/xilinx/test/project.tcl.in
Normal file
File diff suppressed because it is too large
Load Diff
208
hw/syn/xilinx/test/project_1_files/Vortex_top.v
Normal file
208
hw/syn/xilinx/test/project_1_files/Vortex_top.v
Normal file
@@ -0,0 +1,208 @@
|
||||
// Copyright © 2019-2023
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
`include "VX_define.vh"
|
||||
|
||||
module Vortex_top #(
|
||||
parameter C_M_AXI_GMEM_DATA_WIDTH = 512,
|
||||
parameter C_M_AXI_GMEM_ADDR_WIDTH = `XLEN,
|
||||
parameter C_M_AXI_GMEM_ID_WIDTH = 32,
|
||||
parameter C_M_AXI_MEM_NUM_BANKS = 1
|
||||
) (
|
||||
input wire clk,
|
||||
input wire reset,
|
||||
|
||||
// AXI4 memory interface
|
||||
output wire m_axi_mem_awvalid,
|
||||
input wire m_axi_mem_awready,
|
||||
output wire [C_M_AXI_GMEM_ADDR_WIDTH-1:0] m_axi_mem_awaddr,
|
||||
output wire [C_M_AXI_GMEM_ID_WIDTH - 1:0] m_axi_mem_awid,
|
||||
output wire [7:0] m_axi_mem_awlen,
|
||||
output wire [2:0] m_axi_mem_awsize,
|
||||
output wire [1:0] m_axi_mem_awburst,
|
||||
output wire [1:0] m_axi_mem_awlock,
|
||||
output wire [3:0] m_axi_mem_awcache,
|
||||
output wire [2:0] m_axi_mem_awprot,
|
||||
output wire [3:0] m_axi_mem_awqos,
|
||||
output wire m_axi_mem_wvalid,
|
||||
input wire m_axi_mem_wready,
|
||||
output wire [C_M_AXI_GMEM_DATA_WIDTH-1:0] m_axi_mem_wdata,
|
||||
output wire [C_M_AXI_GMEM_DATA_WIDTH/8-1:0] m_axi_mem_wstrb,
|
||||
output wire m_axi_mem_wlast,
|
||||
output wire m_axi_mem_arvalid,
|
||||
input wire m_axi_mem_arready,
|
||||
output wire [C_M_AXI_GMEM_ADDR_WIDTH-1:0] m_axi_mem_araddr,
|
||||
output wire [C_M_AXI_GMEM_ID_WIDTH-1:0] m_axi_mem_arid,
|
||||
output wire [7:0] m_axi_mem_arlen,
|
||||
output wire [2:0] m_axi_mem_arsize,
|
||||
output wire [1:0] m_axi_mem_arburst,
|
||||
output wire [1:0] m_axi_mem_arlock,
|
||||
output wire [3:0] m_axi_mem_arcache,
|
||||
output wire [2:0] m_axi_mem_arprot,
|
||||
output wire [3:0] m_axi_mem_arqos,
|
||||
input wire m_axi_mem_rvalid,
|
||||
output wire m_axi_mem_rready,
|
||||
input wire [C_M_AXI_GMEM_DATA_WIDTH - 1:0] m_axi_mem_rdata,
|
||||
input wire m_axi_mem_rlast,
|
||||
input wire [C_M_AXI_GMEM_ID_WIDTH - 1:0] m_axi_mem_rid,
|
||||
input wire [1:0] m_axi_mem_rresp,
|
||||
input wire m_axi_mem_bvalid,
|
||||
output wire m_axi_mem_bready,
|
||||
input wire [1:0] m_axi_mem_bresp,
|
||||
input wire [C_M_AXI_GMEM_ID_WIDTH - 1:0] m_axi_mem_bid,
|
||||
|
||||
input wire dcr_wr_valid,
|
||||
input wire [`VX_DCR_ADDR_WIDTH-1:0] dcr_wr_addr,
|
||||
input wire [`VX_DCR_DATA_WIDTH-1:0] dcr_wr_data,
|
||||
|
||||
output wire busy
|
||||
);
|
||||
|
||||
wire m_axi_mem_awvalid_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire m_axi_mem_awready_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire [C_M_AXI_GMEM_ADDR_WIDTH-1:0] m_axi_mem_awaddr_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire [C_M_AXI_GMEM_ID_WIDTH - 1:0] m_axi_mem_awid_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire [7:0] m_axi_mem_awlen_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire [2:0] m_axi_mem_awsize_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire [1:0] m_axi_mem_awburst_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire [1:0] m_axi_mem_awlock_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire [3:0] m_axi_mem_awcache_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire [2:0] m_axi_mem_awprot_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire [3:0] m_axi_mem_awqos_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire m_axi_mem_wvalid_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire m_axi_mem_wready_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire [C_M_AXI_GMEM_DATA_WIDTH-1:0] m_axi_mem_wdata_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire [C_M_AXI_GMEM_DATA_WIDTH/8-1:0] m_axi_mem_wstrb_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire m_axi_mem_wlast_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire m_axi_mem_arvalid_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire m_axi_mem_arready_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire [C_M_AXI_GMEM_ADDR_WIDTH-1:0] m_axi_mem_araddr_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire [C_M_AXI_GMEM_ID_WIDTH-1:0] m_axi_mem_arid_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire [7:0] m_axi_mem_arlen_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire [2:0] m_axi_mem_arsize_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire [1:0] m_axi_mem_arburst_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire [1:0] m_axi_mem_arlock_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire [3:0] m_axi_mem_arcache_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire [2:0] m_axi_mem_arprot_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire [3:0] m_axi_mem_arqos_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire m_axi_mem_rvalid_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire m_axi_mem_rready_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire [C_M_AXI_GMEM_DATA_WIDTH - 1:0] m_axi_mem_rdata_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire m_axi_mem_rlast_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire [C_M_AXI_GMEM_ID_WIDTH - 1:0] m_axi_mem_rid_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire [1:0] m_axi_mem_rresp_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire m_axi_mem_bvalid_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire m_axi_mem_bready_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire [1:0] m_axi_mem_bresp_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire [C_M_AXI_GMEM_ID_WIDTH - 1:0] m_axi_mem_bid_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
|
||||
assign m_axi_mem_awvalid = m_axi_mem_awvalid_a[0];
|
||||
assign m_axi_mem_awready_a[0] = m_axi_mem_awready;
|
||||
assign m_axi_mem_awaddr = m_axi_mem_awaddr_a[0];
|
||||
assign m_axi_mem_awid = m_axi_mem_awid_a[0];
|
||||
assign m_axi_mem_awlen = m_axi_mem_awlen_a[0];
|
||||
assign m_axi_mem_awsize = m_axi_mem_awsize_a[0];
|
||||
assign m_axi_mem_awburst = m_axi_mem_awburst_a[0];
|
||||
assign m_axi_mem_awlock = m_axi_mem_awlock_a[0];
|
||||
assign m_axi_mem_awcache = m_axi_mem_awcache_a[0];
|
||||
assign m_axi_mem_awprot = m_axi_mem_awprot_a[0];
|
||||
assign m_axi_mem_awqos = m_axi_mem_awqos_a[0];
|
||||
|
||||
assign m_axi_mem_wvalid = m_axi_mem_wvalid_a[0];
|
||||
assign m_axi_mem_wready_a[0] = m_axi_mem_wready;
|
||||
assign m_axi_mem_wdata = m_axi_mem_wdata_a[0];
|
||||
assign m_axi_mem_wstrb = m_axi_mem_wstrb_a[0];
|
||||
assign m_axi_mem_wlast = m_axi_mem_wlast_a[0];
|
||||
|
||||
assign m_axi_mem_arvalid = m_axi_mem_arvalid_a[0];
|
||||
assign m_axi_mem_arready_a[0] = m_axi_mem_arready;
|
||||
assign m_axi_mem_araddr = m_axi_mem_araddr_a[0];
|
||||
assign m_axi_mem_arid = m_axi_mem_arid_a[0];
|
||||
assign m_axi_mem_arlen = m_axi_mem_arlen_a[0];
|
||||
assign m_axi_mem_arsize = m_axi_mem_arsize_a[0];
|
||||
assign m_axi_mem_arburst = m_axi_mem_arburst_a[0];
|
||||
assign m_axi_mem_arlock = m_axi_mem_arlock_a[0];
|
||||
assign m_axi_mem_arcache = m_axi_mem_arcache_a[0];
|
||||
assign m_axi_mem_arprot = m_axi_mem_arprot_a[0];
|
||||
assign m_axi_mem_arqos = m_axi_mem_arqos_a[0];
|
||||
|
||||
assign m_axi_mem_rvalid_a[0] = m_axi_mem_rvalid;
|
||||
assign m_axi_mem_rready = m_axi_mem_rready_a[0];
|
||||
assign m_axi_mem_rdata_a[0] = m_axi_mem_rdata;
|
||||
assign m_axi_mem_rlast_a[0] = m_axi_mem_rlast;
|
||||
assign m_axi_mem_rid_a[0] = m_axi_mem_rid;
|
||||
assign m_axi_mem_rresp_a[0] = m_axi_mem_rresp;
|
||||
|
||||
assign m_axi_mem_bvalid_a[0] = m_axi_mem_bvalid;
|
||||
assign m_axi_mem_bready = m_axi_mem_bready_a[0];
|
||||
assign m_axi_mem_bresp_a[0] = m_axi_mem_bresp;
|
||||
assign m_axi_mem_bid_a[0] = m_axi_mem_bid;
|
||||
|
||||
Vortex_axi #(
|
||||
.AXI_DATA_WIDTH (C_M_AXI_GMEM_DATA_WIDTH),
|
||||
.AXI_ADDR_WIDTH (C_M_AXI_GMEM_ADDR_WIDTH),
|
||||
.AXI_TID_WIDTH (C_M_AXI_GMEM_ID_WIDTH)
|
||||
) inst (
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
|
||||
.m_axi_awvalid (m_axi_mem_awvalid_a),
|
||||
.m_axi_awready (m_axi_mem_awready_a),
|
||||
.m_axi_awaddr (m_axi_mem_awaddr_a),
|
||||
.m_axi_awid (m_axi_mem_awid_a),
|
||||
.m_axi_awlen (m_axi_mem_awlen_a),
|
||||
.m_axi_awsize (m_axi_mem_awsize_a),
|
||||
.m_axi_awburst (m_axi_mem_awburst_a),
|
||||
.m_axi_awlock (m_axi_mem_awlock_a),
|
||||
.m_axi_awcache (m_axi_mem_awcache_a),
|
||||
.m_axi_awprot (m_axi_mem_awprot_a),
|
||||
.m_axi_awqos (m_axi_mem_awqos_a),
|
||||
|
||||
.m_axi_wvalid (m_axi_mem_wvalid_a),
|
||||
.m_axi_wready (m_axi_mem_wready_a),
|
||||
.m_axi_wdata (m_axi_mem_wdata_a),
|
||||
.m_axi_wstrb (m_axi_mem_wstrb_a),
|
||||
.m_axi_wlast (m_axi_mem_wlast_a),
|
||||
|
||||
.m_axi_bvalid (m_axi_mem_bvalid_a),
|
||||
.m_axi_bready (m_axi_mem_bready_a),
|
||||
.m_axi_bid (m_axi_mem_bid_a),
|
||||
.m_axi_bresp (m_axi_mem_bresp_a),
|
||||
|
||||
.m_axi_arvalid (m_axi_mem_arvalid_a),
|
||||
.m_axi_arready (m_axi_mem_arready_a),
|
||||
.m_axi_araddr (m_axi_mem_araddr_a),
|
||||
.m_axi_arid (m_axi_mem_arid_a),
|
||||
.m_axi_arlen (m_axi_mem_arlen_a),
|
||||
.m_axi_arsize (m_axi_mem_arsize_a),
|
||||
.m_axi_arburst (m_axi_mem_arburst_a),
|
||||
.m_axi_arlock (m_axi_mem_arlock_a),
|
||||
.m_axi_arcache (m_axi_mem_arcache_a),
|
||||
.m_axi_arprot (m_axi_mem_arprot_a),
|
||||
.m_axi_arqos (m_axi_mem_arqos_a),
|
||||
|
||||
.m_axi_rvalid (m_axi_mem_rvalid_a),
|
||||
.m_axi_rready (m_axi_mem_rready_a),
|
||||
.m_axi_rdata (m_axi_mem_rdata_a),
|
||||
.m_axi_rid (m_axi_mem_rid_a),
|
||||
.m_axi_rresp (m_axi_mem_rresp_a),
|
||||
.m_axi_rlast (m_axi_mem_rlast_a),
|
||||
|
||||
.dcr_wr_valid (dcr_wr_valid),
|
||||
.dcr_wr_addr (dcr_wr_addr),
|
||||
.dcr_wr_data (dcr_wr_data),
|
||||
|
||||
.busy (busy)
|
||||
);
|
||||
|
||||
endmodule
|
||||
16386
hw/syn/xilinx/test/project_1_files/kernel.bin.coe
Normal file
16386
hw/syn/xilinx/test/project_1_files/kernel.bin.coe
Normal file
File diff suppressed because it is too large
Load Diff
119
hw/syn/xilinx/test/project_1_files/testbench.v
Normal file
119
hw/syn/xilinx/test/project_1_files/testbench.v
Normal file
@@ -0,0 +1,119 @@
|
||||
// Copyright © 2019-2023
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
`include "VX_define.vh"
|
||||
|
||||
`timescale 10ns / 1ns
|
||||
|
||||
`define CYCLE_TIME 4
|
||||
|
||||
module testbench;
|
||||
reg clk;
|
||||
reg resetn;
|
||||
reg [43:0] cycles;
|
||||
|
||||
reg vx_running;
|
||||
reg vx_reset_wait;
|
||||
reg vx_busy_wait;
|
||||
wire vx_busy;
|
||||
|
||||
reg dcr_wr_valid;
|
||||
reg [11:0] dcr_wr_addr;
|
||||
reg [31:0] dcr_wr_data;
|
||||
|
||||
design_1_wrapper UUD(
|
||||
.clk_100MHz (clk),
|
||||
.resetn (resetn),
|
||||
.vx_reset (~resetn || ~vx_running),
|
||||
.dcr_wr_valid (dcr_wr_valid),
|
||||
.dcr_wr_addr (dcr_wr_addr),
|
||||
.dcr_wr_data (dcr_wr_data),
|
||||
.vx_busy (vx_busy)
|
||||
);
|
||||
|
||||
always #(`CYCLE_TIME/2)
|
||||
clk = ~clk;
|
||||
|
||||
initial begin
|
||||
clk = 1'b0;
|
||||
resetn = 1'b0;
|
||||
#4 resetn = 1'b1;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (~resetn) begin
|
||||
cycles <= 0;
|
||||
end else begin
|
||||
cycles <= cycles + 1;
|
||||
end
|
||||
end
|
||||
|
||||
reg [7:0] vx_reset_ctr;
|
||||
always @(posedge clk) begin
|
||||
if (vx_reset_wait) begin
|
||||
vx_reset_ctr <= vx_reset_ctr + 1;
|
||||
end else begin
|
||||
vx_reset_ctr <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (~resetn) begin
|
||||
vx_running <= 0;
|
||||
vx_reset_wait <= 0;
|
||||
vx_busy_wait <= 0;
|
||||
dcr_wr_valid <= 0;
|
||||
dcr_wr_addr <= 0;
|
||||
dcr_wr_data <= 0;
|
||||
end else begin
|
||||
case (cycles)
|
||||
1: begin
|
||||
dcr_wr_valid <= 1;
|
||||
dcr_wr_addr <= `VX_DCR_BASE_STARTUP_ADDR0;
|
||||
dcr_wr_data <= `STARTUP_ADDR;
|
||||
end
|
||||
2: begin
|
||||
dcr_wr_valid <= 0;
|
||||
dcr_wr_addr <= 0;
|
||||
dcr_wr_data <= 0;
|
||||
end
|
||||
3: begin
|
||||
vx_reset_wait <= 1;
|
||||
end
|
||||
default:;
|
||||
endcase
|
||||
|
||||
if (vx_running) begin
|
||||
if (vx_busy_wait) begin
|
||||
if (vx_busy) begin
|
||||
vx_busy_wait <= 0;
|
||||
end
|
||||
end else begin
|
||||
if (~vx_busy) begin
|
||||
vx_running <= 0;
|
||||
$display("done!");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
end else begin
|
||||
if (vx_reset_wait && vx_reset_ctr == (`RESET_DELAY-1)) begin
|
||||
$display("start!");
|
||||
vx_reset_wait <= 0;
|
||||
vx_running <= 1;
|
||||
vx_busy_wait <= 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
1
hw/syn/xilinx/xrt/.gitignore
vendored
Normal file
1
hw/syn/xilinx/xrt/.gitignore
vendored
Normal file
@@ -0,0 +1 @@
|
||||
/build*/*
|
||||
200
hw/syn/xilinx/xrt/Makefile
Normal file
200
hw/syn/xilinx/xrt/Makefile
Normal file
@@ -0,0 +1,200 @@
|
||||
ifneq ($(findstring Makefile, $(MAKEFILE_LIST)), Makefile)
|
||||
help:
|
||||
$(ECHO) "Makefile Usage:"
|
||||
$(ECHO) " make all TARGET=<sw_emu/hw_emu/hw> PLATFORM=<FPGA platform>"
|
||||
$(ECHO) " Command to generate the design for specified Target and Device."
|
||||
$(ECHO) ""
|
||||
$(ECHO) " make clean"
|
||||
$(ECHO) " Command to remove the generated non-hardware files."
|
||||
$(ECHO) ""
|
||||
endif
|
||||
|
||||
TARGET ?= hw
|
||||
PLATFORM ?=
|
||||
XLEN ?= 32
|
||||
NUM_CORES ?= 1
|
||||
PREFIX ?= build$(XLEN)
|
||||
MAX_JOBS ?= 8
|
||||
|
||||
RTL_DIR = ../../../../rtl
|
||||
AFU_DIR = $(RTL_DIR)/afu/xrt
|
||||
DPI_DIR = ../../../../dpi
|
||||
SCRIPT_DIR = ../../../../scripts
|
||||
THIRD_PARTY_DIR = ../../../../../third_party
|
||||
|
||||
VIVADO = $(XILINX_VIVADO)/bin/vivado
|
||||
VPP = $(XILINX_VITIS)/bin/v++
|
||||
CP = cp -rf
|
||||
RMDIR = rm -rf
|
||||
ECHO = @echo
|
||||
|
||||
NCPUS := $(shell grep -c ^processor /proc/cpuinfo)
|
||||
JOBS ?= $(shell echo $$(( $(NCPUS) > $(MAX_JOBS) ? $(MAX_JOBS) : $(NCPUS) )))
|
||||
|
||||
PLATFORM_TO_XSA = $(strip $(patsubst %.xpfm, % , $(shell basename $(PLATFORM))))
|
||||
XSA := $(call PLATFORM_TO_XSA, $(PLATFORM))
|
||||
|
||||
DEV_ARCH := $(shell platforminfo -p $(PLATFORM) | grep 'FPGA Family' | sed 's/.*://' | sed '/ai_engine/d' | sed 's/^[[:space:]]*//')
|
||||
CPU_TYPE := $(shell platforminfo -p $(PLATFORM) | grep 'CPU Type' | sed 's/.*://' | sed '/ai_engine/d' | sed 's/^[[:space:]]*//')
|
||||
|
||||
BUILD_DIR = $(PREFIX)_$(XSA)_$(TARGET)
|
||||
BIN_DIR = $(BUILD_DIR)/bin
|
||||
|
||||
XO_CONTAINER = $(BIN_DIR)/vortex_afu.xo
|
||||
XCLBIN_CONTAINER = $(BIN_DIR)/vortex_afu.xclbin
|
||||
|
||||
# Control RTL debug tracing states
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_PIPELINE
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_ICACHE
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_DCACHE
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_MEM
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_BANK
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_MSHR
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_TAG
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_DATA
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_AFU
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_TEX
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_RASTER
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_ROP
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_GBAR
|
||||
|
||||
# Control logic analyzer monitors
|
||||
DBG_SCOPE_FLAGS += -DDBG_SCOPE_AFU
|
||||
DBG_SCOPE_FLAGS += -DDBG_SCOPE_ISSUE
|
||||
DBG_SCOPE_FLAGS += -DDBG_SCOPE_FETCH
|
||||
DBG_SCOPE_FLAGS += -DDBG_SCOPE_LSU
|
||||
DBG_SCOPE_FLAGS += -DDBG_SCOPE_RASTER
|
||||
DBG_SCOPE_FLAGS += -DDBG_SCOPE_MSCHED
|
||||
|
||||
# cluster configuration
|
||||
CONFIGS_1c := -DNUM_CLUSTERS=1 -DNUM_CORES=1
|
||||
CONFIGS_2c := -DNUM_CLUSTERS=1 -DNUM_CORES=2
|
||||
CONFIGS_4c := -DNUM_CLUSTERS=1 -DNUM_CORES=4
|
||||
CONFIGS_8c := -DNUM_CLUSTERS=1 -DNUM_CORES=8
|
||||
CONFIGS_16c := -DNUM_CLUSTERS=1 -DNUM_CORES=16 -DL2_ENABLE
|
||||
CONFIGS_32c := -DNUM_CLUSTERS=2 -DNUM_CORES=16 -DL2_ENABLE
|
||||
CONFIGS_64c := -DNUM_CLUSTERS=4 -DNUM_CORES=16 -DL2_ENABLE
|
||||
CONFIGS += $(CONFIGS_$(NUM_CORES)c)
|
||||
|
||||
# include paths
|
||||
FPU_INCLUDE = -I$(RTL_DIR)/fpu
|
||||
ifneq (,$(findstring FPU_FPNEW,$(CONFIGS)))
|
||||
FPU_INCLUDE += -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -I$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(THIRD_PARTY_DIR)/fpnew/src
|
||||
endif
|
||||
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache -I$(AFU_DIR)
|
||||
RTL_INCLUDE += $(FPU_INCLUDE)
|
||||
|
||||
# Kernel compiler global settings
|
||||
VPP_FLAGS += --link --target $(TARGET) --platform $(PLATFORM) --save-temps --no_ip_cache
|
||||
VPP_FLAGS += --vivado.synth.jobs $(JOBS) --vivado.impl.jobs $(JOBS)
|
||||
|
||||
ifeq ($(DEV_ARCH), zynquplus)
|
||||
# ztnq
|
||||
else ifeq ($(DEV_ARCH), versal)
|
||||
# versal
|
||||
else
|
||||
# alveo
|
||||
VPP_FLAGS += --connectivity.sp vortex_afu_1.m_axi_mem_0:HBM[0:15]
|
||||
endif
|
||||
|
||||
VPP_FLAGS += --report_level 2
|
||||
VPP_FLAGS += --config ../vitis.ini
|
||||
|
||||
# Enable perf counters
|
||||
ifdef PERF
|
||||
CFLAGS += -DPERF_ENABLE
|
||||
endif
|
||||
|
||||
# Generates profile summary report
|
||||
ifdef PROFILE
|
||||
VPP_FLAGS += --profile_kernel data:all:all:all
|
||||
VPP_FLAGS += --profile_kernel stall:all:all:all
|
||||
endif
|
||||
|
||||
ifeq ($(TARGET), hw_emu)
|
||||
CFLAGS += -DSIMULATION
|
||||
endif
|
||||
|
||||
# Debugigng
|
||||
ifdef DEBUG
|
||||
VPP_FLAGS += -g --debug.protocol all
|
||||
ifeq ($(TARGET), hw)
|
||||
CFLAGS += -DNDEBUG -DSCOPE $(DBG_SCOPE_FLAGS)
|
||||
SCOPE_JSON += $(BUILD_DIR)/scope.json
|
||||
#CFLAGS += -DNDEBUG -DCHIPSCOPE $(DBG_SCOPE_FLAGS)
|
||||
#VPP_FLAGS += --debug.chipscope vortex_afu_1
|
||||
else
|
||||
VPP_FLAGS += --vivado.prop fileset.sim_1.xsim.elaborate.debug_level=all
|
||||
CFLAGS += $(DBG_TRACE_FLAGS)
|
||||
endif
|
||||
else
|
||||
VPP_FLAGS += --optimize 3
|
||||
CFLAGS += -DNDEBUG
|
||||
endif
|
||||
|
||||
# compilation flags
|
||||
CFLAGS += -DSYNTHESIS -DVIVADO
|
||||
CFLAGS += -DXLEN_$(XLEN)
|
||||
CFLAGS += $(CONFIGS)
|
||||
CFLAGS += $(RTL_INCLUDE)
|
||||
|
||||
# ast dump flags
|
||||
XML_CFLAGS = $(filter-out -DSYNTHESIS -DVIVADO, $(CFLAGS)) -I$(DPI_DIR)
|
||||
|
||||
# RTL Kernel only supports Hardware and Hardware Emulation.
|
||||
ifneq ($(TARGET),$(findstring $(TARGET), hw hw_emu))
|
||||
$(warning WARNING:Application supports only hw hw_emu TARGET. Please use the target for running the application)
|
||||
endif
|
||||
|
||||
.PHONY: all clean gen-sources gen-ast emconfig check-devices
|
||||
|
||||
all: check-devices emconfig $(XCLBIN_CONTAINER) report
|
||||
|
||||
gen-sources: $(BUILD_DIR)/sources.txt
|
||||
$(BUILD_DIR)/sources.txt:
|
||||
mkdir -p $(BUILD_DIR); cd $(BUILD_DIR); $(SCRIPT_DIR)/gen_sources.sh -P $(CFLAGS) -Csrc -Osources.txt
|
||||
|
||||
gen-ast: $(BUILD_DIR)/vortex.xml
|
||||
$(BUILD_DIR)/vortex.xml:
|
||||
mkdir -p $(BUILD_DIR); cd $(BUILD_DIR); verilator --xml-only -O0 $(XML_CFLAGS) vortex_afu.v --xml-output vortex.xml
|
||||
|
||||
scope-json: $(BUILD_DIR)/scope.json
|
||||
$(BUILD_DIR)/scope.json: $(BUILD_DIR)/vortex.xml
|
||||
mkdir -p $(BUILD_DIR); cd $(BUILD_DIR); $(SCRIPT_DIR)/scope.py vortex.xml -o scope.json
|
||||
|
||||
gen-xo: $(XO_CONTAINER)
|
||||
$(XO_CONTAINER): $(BUILD_DIR)/sources.txt
|
||||
mkdir -p $(BUILD_DIR); cd $(BUILD_DIR); $(VIVADO) -mode batch -source ../scripts/gen_xo.tcl -tclargs ../$(XO_CONTAINER) vortex_afu sources.txt $(SCRIPT_DIR) ../$(BUILD_DIR)
|
||||
|
||||
gen-bin: $(XCLBIN_CONTAINER)
|
||||
$(XCLBIN_CONTAINER): $(XO_CONTAINER) $(SCOPE_JSON)
|
||||
mkdir -p $(BIN_DIR); cd $(BUILD_DIR); $(VPP) $(VPP_FLAGS) -o ../$(XCLBIN_CONTAINER) ../$(XO_CONTAINER)
|
||||
|
||||
emconfig: $(BIN_DIR)/emconfig.json
|
||||
$(BIN_DIR)/emconfig.json:
|
||||
mkdir -p $(BIN_DIR); cd $(BUILD_DIR); emconfigutil --platform $(PLATFORM) --od ../$(BIN_DIR)
|
||||
|
||||
report: $(XCLBIN_CONTAINER)
|
||||
ifeq ($(TARGET),$(findstring $(TARGET), hw))
|
||||
cp $(BUILD_DIR)/_x/logs/link/syn/ulp_vortex_afu_1_0_synth_1_runme.log $(BUILD_DIR)/bin/runme.log
|
||||
cp $(BUILD_DIR)/_x/reports/link/imp/impl_1_full_util_routed.rpt $(BUILD_DIR)/bin/synthesis.log
|
||||
cp $(BUILD_DIR)/_x/reports/link/imp/impl_1_hw_bb_locked_timing_summary_routed.rpt $(BUILD_DIR)/bin/timing.log
|
||||
endif
|
||||
|
||||
hwserver:
|
||||
debug_hw --xvc_pcie /dev/xfpga/xvc_pub.u2305.0 --hw_server &
|
||||
|
||||
chipscope:
|
||||
debug_hw --vivado --host localhost --ltx_file $(BUILD_DIR)/_x/link/vivado/vpl/prj/prj.runs/impl_1/debug_nets.ltx &
|
||||
|
||||
clean:
|
||||
$(RMDIR) $(BUILD_DIR)
|
||||
|
||||
# Check the devices avaiable
|
||||
check-devices:
|
||||
ifndef PLATFORM
|
||||
$(error PLATFORM not set. Please set the PLATFORM properly and rerun. Run "make help" for more details.)
|
||||
endif
|
||||
ifndef XILINX_VITIS
|
||||
$(error XILINX_VITIS variable is not set, please set correctly and rerun)
|
||||
endif
|
||||
25
hw/syn/xilinx/xrt/kill_build.sh
Executable file
25
hw/syn/xilinx/xrt/kill_build.sh
Executable file
@@ -0,0 +1,25 @@
|
||||
#!/bin/sh
|
||||
|
||||
# Copyright © 2019-2023
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
ps -A | grep xrcserver | awk '{print $1}' | xargs kill -9 $1
|
||||
ps -A | grep loader | awk '{print $1}' | xargs kill -9 $1
|
||||
ps -A | grep vpl | awk '{print $1}' | xargs kill -9 $1
|
||||
ps -A | grep v++ | awk '{print $1}' | xargs kill -9 $1
|
||||
ps -A | grep vivado | awk '{print $1}' | xargs kill -9 $1
|
||||
ps -A | grep runme.sh | awk '{print $1}' | xargs kill -9 $1
|
||||
ps -A | grep ISEWrap.sh | awk '{print $1}' | xargs kill -9 $1
|
||||
ps -A | grep vrs | awk '{print $1}' | xargs kill -9 $1
|
||||
ps -A | grep xcd | awk '{print $1}' | xargs kill -9 $1
|
||||
ps -A | grep make | awk '{print $1}' | xargs kill -9 $1
|
||||
19
hw/syn/xilinx/xrt/kill_hwserver.sh
Executable file
19
hw/syn/xilinx/xrt/kill_hwserver.sh
Executable file
@@ -0,0 +1,19 @@
|
||||
#!/bin/bash
|
||||
|
||||
# Copyright © 2019-2023
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
ps -A | grep debug_hw | awk '{print $1}' | xargs kill -9 $1
|
||||
ps -A | grep python3 | awk '{print $1}' | xargs kill -9 $1
|
||||
ps -A | grep xvc_pcie | awk '{print $1}' | xargs kill -9 $1
|
||||
ps -A | grep hw_server | awk '{print $1}' | xargs kill -9 $1
|
||||
19
hw/syn/xilinx/xrt/kill_sim.sh
Executable file
19
hw/syn/xilinx/xrt/kill_sim.sh
Executable file
@@ -0,0 +1,19 @@
|
||||
#!/bin/sh
|
||||
|
||||
# Copyright © 2019-2023
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
ps -A | grep launch_hw_emu.s | awk '{print $1}' | xargs kill -9 $1
|
||||
ps -A | grep simulate.sh | awk '{print $1}' | xargs kill -9 $1
|
||||
ps -A | grep xsim | awk '{print $1}' | xargs kill -9 $1
|
||||
ps -A | grep xsimk | awk '{print $1}' | xargs kill -9 $1
|
||||
40
hw/syn/xilinx/xrt/scripts/gen_ip.tcl
Normal file
40
hw/syn/xilinx/xrt/scripts/gen_ip.tcl
Normal file
@@ -0,0 +1,40 @@
|
||||
# Copyright © 2019-2023
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
if { $::argc != 1 } {
|
||||
puts "ERROR: Program \"$::argv0\" requires 1 arguments!\n"
|
||||
puts "Usage: $::argv0 <ip_dir>\n"
|
||||
exit
|
||||
}
|
||||
|
||||
set ip_dir [lindex $::argv 0]
|
||||
|
||||
# IP folder does not exist. Create IP folder
|
||||
file mkdir ${ip_dir}
|
||||
|
||||
# create_ip requires that a project is open in memory.
|
||||
# Create project but don't do anything with it
|
||||
create_project -in_memory
|
||||
|
||||
create_ip -name floating_point -vendor xilinx.com -library ip -version 7.1 -module_name xil_fdiv -dir ${ip_dir}
|
||||
set_property -dict [list CONFIG.Component_Name {xil_fdiv} CONFIG.Operation_Type {Divide} CONFIG.Flow_Control {NonBlocking} CONFIG.Has_ACLKEN {true} CONFIG.C_Has_UNDERFLOW {true} CONFIG.C_Has_OVERFLOW {true} CONFIG.C_Has_INVALID_OP {true} CONFIG.C_Has_DIVIDE_BY_ZERO {true} CONFIG.A_Precision_Type {Single} CONFIG.C_A_Exponent_Width {8} CONFIG.C_A_Fraction_Width {24} CONFIG.Result_Precision_Type {Single} CONFIG.C_Result_Exponent_Width {8} CONFIG.C_Result_Fraction_Width {24} CONFIG.C_Mult_Usage {No_Usage} CONFIG.Has_RESULT_TREADY {false} CONFIG.C_Latency {28} CONFIG.C_Rate {1}] [get_ips xil_fdiv]
|
||||
|
||||
create_ip -name floating_point -vendor xilinx.com -library ip -version 7.1 -module_name xil_fsqrt -dir ${ip_dir}
|
||||
set_property -dict [list CONFIG.Component_Name {xil_fsqrt} CONFIG.Operation_Type {Square_root} CONFIG.Flow_Control {NonBlocking} CONFIG.Has_ACLKEN {true} CONFIG.C_Has_INVALID_OP {true} CONFIG.A_Precision_Type {Single} CONFIG.C_A_Exponent_Width {8} CONFIG.C_A_Fraction_Width {24} CONFIG.Result_Precision_Type {Single} CONFIG.C_Result_Exponent_Width {8} CONFIG.C_Result_Fraction_Width {24} CONFIG.C_Mult_Usage {No_Usage} CONFIG.Has_RESULT_TREADY {false} CONFIG.C_Latency {28} CONFIG.C_Rate {1}] [get_ips xil_fsqrt]
|
||||
|
||||
create_ip -name floating_point -vendor xilinx.com -library ip -version 7.1 -module_name xil_fma -dir ${ip_dir}
|
||||
set_property -dict [list CONFIG.Component_Name {xil_fma} CONFIG.Operation_Type {FMA} CONFIG.Add_Sub_Value {Add} CONFIG.Flow_Control {NonBlocking} CONFIG.Has_ACLKEN {true} CONFIG.C_Has_UNDERFLOW {true} CONFIG.C_Has_OVERFLOW {true} CONFIG.C_Has_INVALID_OP {true} CONFIG.Has_A_TUSER {false} CONFIG.A_Precision_Type {Single} CONFIG.C_A_Exponent_Width {8} CONFIG.C_A_Fraction_Width {24} CONFIG.Result_Precision_Type {Single} CONFIG.C_Result_Exponent_Width {8} CONFIG.C_Result_Fraction_Width {24} CONFIG.C_Mult_Usage {Medium_Usage} CONFIG.Has_RESULT_TREADY {false} CONFIG.C_Latency {16} CONFIG.C_Rate {1} CONFIG.A_TUSER_Width {1}] [get_ips xil_fma]
|
||||
|
||||
generate_target all [get_ips]
|
||||
|
||||
close_project -delete
|
||||
40
hw/syn/xilinx/xrt/scripts/gen_xo.tcl
Normal file
40
hw/syn/xilinx/xrt/scripts/gen_xo.tcl
Normal file
@@ -0,0 +1,40 @@
|
||||
# Copyright © 2019-2023
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
if { $::argc != 5 } {
|
||||
puts "ERROR: Program \"$::argv0\" requires 4 arguments!\n"
|
||||
puts "Usage: $::argv0 <xoname> <krnl_name> <vcs_file> <tool_dir> <build_dir>\n"
|
||||
exit
|
||||
}
|
||||
|
||||
set xoname [lindex $::argv 0]
|
||||
set krnl_name [lindex $::argv 1]
|
||||
set vcs_file [lindex $::argv 2]
|
||||
set tool_dir [lindex $::argv 3]
|
||||
set build_dir [lindex $::argv 4]
|
||||
|
||||
set script_path [ file dirname [ file normalize [ info script ] ] ]
|
||||
|
||||
if {[file exists "${xoname}"]} {
|
||||
file delete -force "${xoname}"
|
||||
}
|
||||
|
||||
set argv [list ${build_dir}/ip]
|
||||
set argc 1
|
||||
source ${script_path}/gen_ip.tcl
|
||||
|
||||
set argv [list ${krnl_name} ${vcs_file} ${tool_dir} ${build_dir}]
|
||||
set argc 4
|
||||
source ${script_path}/package_kernel.tcl
|
||||
|
||||
package_xo -xo_path ${xoname} -kernel_name ${krnl_name} -ip_directory "${build_dir}/xo/packaged_kernel"
|
||||
268
hw/syn/xilinx/xrt/scripts/package_kernel.tcl
Normal file
268
hw/syn/xilinx/xrt/scripts/package_kernel.tcl
Normal file
@@ -0,0 +1,268 @@
|
||||
# Copyright © 2019-2023
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
if { $::argc != 4 } {
|
||||
puts "ERROR: Program \"$::argv0\" requires 4 arguments!\n"
|
||||
puts "Usage: $::argv0 <krnl_name> <vcs_file> <tool_dir> <build_dir>\n"
|
||||
exit
|
||||
}
|
||||
|
||||
set krnl_name [lindex $::argv 0]
|
||||
set vcs_file [lindex $::argv 1]
|
||||
set tool_dir [lindex $::argv 2]
|
||||
set build_dir [lindex $::argv 3]
|
||||
|
||||
set path_to_packaged "${build_dir}/xo/packaged_kernel"
|
||||
set path_to_tmp_project "${build_dir}/xo/project"
|
||||
|
||||
source "${tool_dir}/parse_vcs_list.tcl"
|
||||
set vlist [parse_vcs_list "${vcs_file}"]
|
||||
|
||||
set vsources_list [lindex $vlist 0]
|
||||
set vincludes_list [lindex $vlist 1]
|
||||
set vdefines_list [lindex $vlist 2]
|
||||
|
||||
#puts ${vsources_list}
|
||||
#puts ${vincludes_list}
|
||||
#puts ${vdefines_list}
|
||||
|
||||
# find if chipscope is enabled
|
||||
set chipscope 0
|
||||
foreach def $vdefines_list {
|
||||
set fields [split $def "="]
|
||||
set name [lindex $fields 0]
|
||||
if { $name == "CHIPSCOPE" } {
|
||||
set chipscope 1
|
||||
}
|
||||
}
|
||||
|
||||
create_project -force kernel_pack $path_to_tmp_project
|
||||
|
||||
add_files -norecurse ${vsources_list}
|
||||
|
||||
set obj [get_filesets sources_1]
|
||||
set files [list \
|
||||
[file normalize "${build_dir}/ip/xil_fdiv/xil_fdiv.xci"] \
|
||||
[file normalize "${build_dir}/ip/xil_fma/xil_fma.xci"] \
|
||||
[file normalize "${build_dir}/ip/xil_fsqrt/xil_fsqrt.xci"] \
|
||||
]
|
||||
add_files -verbose -norecurse -fileset $obj $files
|
||||
|
||||
set_property include_dirs ${vincludes_list} [current_fileset]
|
||||
#set_property verilog_define ${vdefines_list} [current_fileset]
|
||||
|
||||
set obj [get_filesets sources_1]
|
||||
set_property -verbose -name "top" -value ${krnl_name} -objects $obj
|
||||
|
||||
if { $chipscope == 1 } {
|
||||
# hw debugging
|
||||
create_ip -name axis_ila -vendor xilinx.com -library ip -version 1.1 -module_name ila_afu
|
||||
set_property -dict [list CONFIG.C_ADV_TRIGGER {true} \
|
||||
CONFIG.C_EN_STRG_QUAL {1} \
|
||||
CONFIG.C_DATA_DEPTH {4096} \
|
||||
CONFIG.C_NUM_OF_PROBES {2} \
|
||||
CONFIG.C_PROBE0_WIDTH {8} \
|
||||
CONFIG.C_PROBE1_WIDTH {24} \
|
||||
] [get_ips ila_afu]
|
||||
generate_target {instantiation_template} [get_files ila_afu.xci]
|
||||
set_property generate_synth_checkpoint false [get_files ila_afu.xci]
|
||||
|
||||
create_ip -name axis_ila -vendor xilinx.com -library ip -version 1.1 -module_name ila_fetch
|
||||
set_property -dict [list CONFIG.C_ADV_TRIGGER {true} \
|
||||
CONFIG.C_EN_STRG_QUAL {1} \
|
||||
CONFIG.C_DATA_DEPTH {4096} \
|
||||
CONFIG.C_NUM_OF_PROBES {3} \
|
||||
CONFIG.C_PROBE0_WIDTH {128} \
|
||||
CONFIG.C_PROBE1_WIDTH {128} \
|
||||
CONFIG.C_PROBE2_WIDTH {128} \
|
||||
] [get_ips ila_fetch]
|
||||
generate_target {instantiation_template} [get_files ila_fetch.xci]
|
||||
set_property generate_synth_checkpoint false [get_files ila_fetch.xci]
|
||||
|
||||
create_ip -name axis_ila -vendor xilinx.com -library ip -version 1.1 -module_name ila_issue
|
||||
set_property -dict [list CONFIG.C_ADV_TRIGGER {true} \
|
||||
CONFIG.C_EN_STRG_QUAL {1} \
|
||||
CONFIG.C_DATA_DEPTH {4096} \
|
||||
CONFIG.C_NUM_OF_PROBES {2} \
|
||||
CONFIG.C_PROBE0_WIDTH {256} \
|
||||
CONFIG.C_PROBE1_WIDTH {128} \
|
||||
] [get_ips ila_issue]
|
||||
generate_target {instantiation_template} [get_files ila_issue.xci]
|
||||
set_property generate_synth_checkpoint false [get_files ila_issue.xci]
|
||||
|
||||
create_ip -name axis_ila -vendor xilinx.com -library ip -version 1.1 -module_name ila_lsu
|
||||
set_property -dict [list CONFIG.C_ADV_TRIGGER {true} \
|
||||
CONFIG.C_EN_STRG_QUAL {1} \
|
||||
CONFIG.C_DATA_DEPTH {4096} \
|
||||
CONFIG.C_NUM_OF_PROBES {4} \
|
||||
CONFIG.C_PROBE0_WIDTH {256} \
|
||||
CONFIG.C_PROBE1_WIDTH {128} \
|
||||
CONFIG.C_PROBE2_WIDTH {288} \
|
||||
CONFIG.C_PROBE3_WIDTH {256} \
|
||||
] [get_ips ila_lsu]
|
||||
generate_target {instantiation_template} [get_files ila_lsu.xci]
|
||||
set_property generate_synth_checkpoint false [get_files ila_lsu.xci]
|
||||
|
||||
create_ip -name axis_ila -vendor xilinx.com -library ip -version 1.1 -module_name ila_msched
|
||||
set_property -dict [list CONFIG.C_ADV_TRIGGER {true} \
|
||||
CONFIG.C_EN_STRG_QUAL {1} \
|
||||
CONFIG.C_DATA_DEPTH {4096} \
|
||||
CONFIG.C_NUM_OF_PROBES {4} \
|
||||
CONFIG.C_PROBE0_WIDTH {128} \
|
||||
CONFIG.C_PROBE1_WIDTH {128} \
|
||||
CONFIG.C_PROBE2_WIDTH {128} \
|
||||
CONFIG.C_PROBE3_WIDTH {128} \
|
||||
] [get_ips ila_msched]
|
||||
generate_target {instantiation_template} [get_files ila_msched.xci]
|
||||
set_property generate_synth_checkpoint false [get_files ila_msched.xci]
|
||||
|
||||
create_ip -name axis_ila -vendor xilinx.com -library ip -version 1.1 -module_name ila_raster
|
||||
set_property -dict [list CONFIG.C_ADV_TRIGGER {true} \
|
||||
CONFIG.C_EN_STRG_QUAL {1} \
|
||||
CONFIG.C_DATA_DEPTH {4096} \
|
||||
CONFIG.C_NUM_OF_PROBES {2} \
|
||||
CONFIG.C_PROBE0_WIDTH {128} \
|
||||
CONFIG.C_PROBE1_WIDTH {128} \
|
||||
] [get_ips ila_raster]
|
||||
generate_target {instantiation_template} [get_files ila_raster.xci]
|
||||
set_property generate_synth_checkpoint false [get_files ila_raster.xci]
|
||||
}
|
||||
|
||||
update_compile_order -fileset sources_1
|
||||
update_compile_order -fileset sim_1
|
||||
ipx::package_project -root_dir $path_to_packaged -vendor xilinx.com -library RTLKernel -taxonomy /KernelIP -import_files -set_current false
|
||||
ipx::unload_core $path_to_packaged/component.xml
|
||||
ipx::edit_ip_in_project -upgrade true -name tmp_edit_project -directory $path_to_packaged $path_to_packaged/component.xml
|
||||
|
||||
set core [ipx::current_core]
|
||||
|
||||
set_property core_revision 2 $core
|
||||
foreach up [ipx::get_user_parameters] {
|
||||
ipx::remove_user_parameter [get_property NAME $up] $core
|
||||
}
|
||||
|
||||
ipx::associate_bus_interfaces -busif s_axi_ctrl -clock ap_clk $core
|
||||
|
||||
for {set i 0} {$i < 1} {incr i} {
|
||||
ipx::associate_bus_interfaces -busif m_axi_mem_$i -clock ap_clk $core
|
||||
}
|
||||
|
||||
set mem_map [::ipx::add_memory_map -quiet "s_axi_ctrl" $core]
|
||||
set addr_block [::ipx::add_address_block -quiet "reg0" $mem_map]
|
||||
|
||||
set reg [::ipx::add_register "CTRL" $addr_block]
|
||||
set_property description "Control signals" $reg
|
||||
set_property address_offset 0x000 $reg
|
||||
set_property size 32 $reg
|
||||
|
||||
set field [ipx::add_field AP_START $reg]
|
||||
set_property ACCESS {read-write} $field
|
||||
set_property BIT_OFFSET {0} $field
|
||||
set_property BIT_WIDTH {1} $field
|
||||
set_property DESCRIPTION {Control signal Register for 'ap_start'.} $field
|
||||
set_property MODIFIED_WRITE_VALUE {modify} $field
|
||||
|
||||
set field [ipx::add_field AP_DONE $reg]
|
||||
set_property ACCESS {read-only} $field
|
||||
set_property BIT_OFFSET {1} $field
|
||||
set_property BIT_WIDTH {1} $field
|
||||
set_property DESCRIPTION {Control signal Register for 'ap_done'.} $field
|
||||
set_property READ_ACTION {modify} $field
|
||||
|
||||
set field [ipx::add_field AP_IDLE $reg]
|
||||
set_property ACCESS {read-only} $field
|
||||
set_property BIT_OFFSET {2} $field
|
||||
set_property BIT_WIDTH {1} $field
|
||||
set_property DESCRIPTION {Control signal Register for 'ap_idle'.} $field
|
||||
set_property READ_ACTION {modify} $field
|
||||
|
||||
set field [ipx::add_field AP_READY $reg]
|
||||
set_property ACCESS {read-only} $field
|
||||
set_property BIT_OFFSET {3} $field
|
||||
set_property BIT_WIDTH {1} $field
|
||||
set_property DESCRIPTION {Control signal Register for 'ap_ready'.} $field
|
||||
set_property READ_ACTION {modify} $field
|
||||
|
||||
set field [ipx::add_field RESERVED_1 $reg]
|
||||
set_property ACCESS {read-only} $field
|
||||
set_property BIT_OFFSET {4} $field
|
||||
set_property BIT_WIDTH {3} $field
|
||||
set_property DESCRIPTION {Reserved. 0s on read.} $field
|
||||
set_property READ_ACTION {modify} $field
|
||||
|
||||
set field [ipx::add_field AUTO_RESTART $reg]
|
||||
set_property ACCESS {read-write} $field
|
||||
set_property BIT_OFFSET {7} $field
|
||||
set_property BIT_WIDTH {1} $field
|
||||
set_property DESCRIPTION {Control signal Register for 'auto_restart'.} $field
|
||||
set_property MODIFIED_WRITE_VALUE {modify} $field
|
||||
|
||||
set field [ipx::add_field RESERVED_2 $reg]
|
||||
set_property ACCESS {read-only} $field
|
||||
set_property BIT_OFFSET {8} $field
|
||||
set_property BIT_WIDTH {24} $field
|
||||
set_property DESCRIPTION {Reserved. 0s on read.} $field
|
||||
set_property READ_ACTION {modify} $field
|
||||
|
||||
set reg [::ipx::add_register "GIER" $addr_block]
|
||||
set_property description "Global Interrupt Enable Register" $reg
|
||||
set_property address_offset 0x004 $reg
|
||||
set_property size 32 $reg
|
||||
|
||||
set reg [::ipx::add_register "IP_IER" $addr_block]
|
||||
set_property description "IP Interrupt Enable Register" $reg
|
||||
set_property address_offset 0x008 $reg
|
||||
set_property size 32 $reg
|
||||
|
||||
set reg [::ipx::add_register "IP_ISR" $addr_block]
|
||||
set_property description "IP Interrupt Status Register" $reg
|
||||
set_property address_offset 0x00C $reg
|
||||
set_property size 32 $reg
|
||||
|
||||
set reg [::ipx::add_register -quiet "DEV" $addr_block]
|
||||
set_property address_offset 0x010 $reg
|
||||
set_property size [expr {8*8}] $reg
|
||||
|
||||
set reg [::ipx::add_register -quiet "ISA" $addr_block]
|
||||
set_property address_offset 0x01C $reg
|
||||
set_property size [expr {8*8}] $reg
|
||||
|
||||
set reg [::ipx::add_register -quiet "DCR" $addr_block]
|
||||
set_property address_offset 0x028 $reg
|
||||
set_property size [expr {8*8}] $reg
|
||||
|
||||
set reg [::ipx::add_register -quiet "SCP" $addr_block]
|
||||
set_property address_offset 0x034 $reg
|
||||
set_property size [expr {8*8}] $reg
|
||||
|
||||
for {set i 0} {$i < 1} {incr i} {
|
||||
set reg [::ipx::add_register -quiet "MEM_$i" $addr_block]
|
||||
set_property address_offset [expr {0x040 + $i * 12}] $reg
|
||||
set_property size [expr {8*8}] $reg
|
||||
set regparam [::ipx::add_register_parameter -quiet {ASSOCIATED_BUSIF} $reg]
|
||||
set_property value m_axi_mem_$i $regparam
|
||||
}
|
||||
|
||||
set_property slave_memory_map_ref "s_axi_ctrl" [::ipx::get_bus_interfaces -of $core "s_axi_ctrl"]
|
||||
|
||||
set_property xpm_libraries {XPM_CDC XPM_MEMORY XPM_FIFO} $core
|
||||
set_property sdx_kernel true $core
|
||||
set_property sdx_kernel_type rtl $core
|
||||
set_property supported_families { } $core
|
||||
set_property auto_family_support_level level_2 $core
|
||||
|
||||
ipx::create_xgui_files $core
|
||||
ipx::update_checksums $core
|
||||
ipx::check_integrity -kernel $core
|
||||
ipx::save_core $core
|
||||
close_project -delete
|
||||
25
hw/syn/xilinx/xrt/scripts/xsim.tcl
Normal file
25
hw/syn/xilinx/xrt/scripts/xsim.tcl
Normal file
@@ -0,0 +1,25 @@
|
||||
#
|
||||
# Copyright 2021 Xilinx, Inc.
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
#
|
||||
|
||||
#log_wave -r *
|
||||
#run all
|
||||
#exit
|
||||
|
||||
open_vcd xsim_dump.vcd
|
||||
log_vcd /*
|
||||
run all
|
||||
close_vcd
|
||||
exit
|
||||
9
hw/syn/xilinx/xrt/vitis.ini
Normal file
9
hw/syn/xilinx/xrt/vitis.ini
Normal file
@@ -0,0 +1,9 @@
|
||||
[connectivity]
|
||||
#nk=vortex_afu:1
|
||||
#sp=vortex_afu_1.m_axi_mem_0:HBM[0:15]
|
||||
|
||||
[vivado]
|
||||
#prop=fileset.sim_1.xsim.elaborate.debug_level=all
|
||||
|
||||
[advanced]
|
||||
#param=compiler.userPostDebugProfileOverlayTcl=../scripts/post_dbg_profile_overlay.tcl
|
||||
11
hw/syn/xilinx/xrt/xrt.ini
Normal file
11
hw/syn/xilinx/xrt/xrt.ini
Normal file
@@ -0,0 +1,11 @@
|
||||
[Runtime]
|
||||
runtime_log=console
|
||||
|
||||
[Emulation]
|
||||
#debug_mode=batch
|
||||
#user_pre_sim_script=xsim.tcl
|
||||
|
||||
[Debug]
|
||||
profile=true
|
||||
timeline_trace=true
|
||||
data_transfer_trace=fine
|
||||
1
hw/syn/yosys/.gitignore
vendored
Normal file
1
hw/syn/yosys/.gitignore
vendored
Normal file
@@ -0,0 +1 @@
|
||||
build_*/*
|
||||
@@ -1,20 +1,99 @@
|
||||
PROJECT = Vortex
|
||||
TOP_LEVEL_ENTITY = Vortex
|
||||
SRC_FILE = Vortex.sv
|
||||
RTL_DIR = ../../rtl
|
||||
TOP_LEVEL_ENTITY ?= Vortex
|
||||
PREFIX ?= build
|
||||
NUM_CORES ?= 1
|
||||
XLEN ?= 32
|
||||
|
||||
DEFINES = -DNDEBUG -DSYNTHESIS -DEXT_F_DISABLE -DNUM_CORES=1 -DNUM_THREADS=2 -DNUM_WARPS=2 -DMEM_BLOCK_SIZE=64
|
||||
SCRIPT_DIR = ../../../scripts
|
||||
RTL_DIR = ../../../rtl
|
||||
DPI_DIR = ../../../dpi
|
||||
THIRD_PARTY_DIR = ../../../../third_party
|
||||
|
||||
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache
|
||||
CP = cp -rf
|
||||
RMDIR = rm -rf
|
||||
ECHO = @echo
|
||||
|
||||
BUILD_DIR = $(PREFIX)_$(TOP_LEVEL_ENTITY)
|
||||
BIN_DIR = $(BUILD_DIR)/bin
|
||||
|
||||
# control RTL debug tracing states
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_PIPELINE
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_ICACHE
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_DCACHE
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_MEM
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_BANK
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_MSHR
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_TAG
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_DATA
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_AFU
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_TEX
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_RASTER
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_ROP
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_GBAR
|
||||
|
||||
# Control logic analyzer monitors
|
||||
DBG_SCOPE_FLAGS += -DDBG_SCOPE_AFU
|
||||
DBG_SCOPE_FLAGS += -DDBG_SCOPE_ISSUE
|
||||
DBG_SCOPE_FLAGS += -DDBG_SCOPE_FETCH
|
||||
DBG_SCOPE_FLAGS += -DDBG_SCOPE_LSU
|
||||
DBG_SCOPE_FLAGS += -DDBG_SCOPE_RASTER
|
||||
DBG_SCOPE_FLAGS += -DDBG_SCOPE_MSCHED
|
||||
|
||||
# cluster configuration
|
||||
CONFIGS_1c := -DNUM_CLUSTERS=1 -DNUM_CORES=1
|
||||
CONFIGS_2c := -DNUM_CLUSTERS=1 -DNUM_CORES=2
|
||||
CONFIGS_4c := -DNUM_CLUSTERS=1 -DNUM_CORES=4 -DL2_ENABLE
|
||||
CONFIGS_8c := -DNUM_CLUSTERS=1 -DNUM_CORES=8 -DL2_ENABLE
|
||||
CONFIGS_16c := -DNUM_CLUSTERS=1 -DNUM_CORES=16 -DL2_ENABLE
|
||||
CONFIGS_32c := -DNUM_CLUSTERS=2 -DNUM_CORES=16 -DL2_ENABLE
|
||||
CONFIGS_64c := -DNUM_CLUSTERS=4 -DNUM_CORES=16 -DL2_ENABLE
|
||||
CONFIGS += $(CONFIGS_$(NUM_CORES)c)
|
||||
|
||||
# include paths
|
||||
FPU_INCLUDE = -I$(RTL_DIR)/fpu
|
||||
ifneq (,$(findstring FPU_FPNEW,$(CONFIGS)))
|
||||
FPU_INCLUDE += -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -J$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/fpnew/src
|
||||
endif
|
||||
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache
|
||||
RTL_INCLUDE += $(FPU_INCLUDE)
|
||||
|
||||
# Debugigng
|
||||
ifdef DEBUG
|
||||
CFLAGS += -DNDEBUG -DSCOPE $(DBG_SCOPE_FLAGS)
|
||||
SCOPE_JSON += $(BUILD_DIR)/scope.json
|
||||
else
|
||||
CFLAGS += -DNDEBUG
|
||||
endif
|
||||
|
||||
# Enable scope analyzer
|
||||
ifdef SCOPE
|
||||
CFLAGS += -DSCOPE
|
||||
endif
|
||||
|
||||
# Enable perf counters
|
||||
ifdef PERF
|
||||
CFLAGS += -DPERF_ENABLE
|
||||
endif
|
||||
|
||||
CFLAGS += -DSYNTHESIS -DYOSYS
|
||||
CFLAGS += -DXLEN_$(XLEN)
|
||||
CFLAGS += $(CONFIGS)
|
||||
CFLAGS += $(RTL_INCLUDE)
|
||||
|
||||
# Build targets
|
||||
all: build
|
||||
all: clean build
|
||||
|
||||
output.v:
|
||||
./sv2v.sh $(DEFINES) $(RTL_INCLUDE) -ooutput.v
|
||||
gen-sources: $(BUILD_DIR)/sources.txt
|
||||
$(BUILD_DIR)/sources.txt:
|
||||
mkdir -p $(BUILD_DIR); cd $(BUILD_DIR); $(SCRIPT_DIR)/gen_sources.sh -P $(CFLAGS) -Csrc -Osources.txt
|
||||
|
||||
build: output.v
|
||||
./synth.sh -t$(TOP_LEVEL_ENTITY) -soutput.v
|
||||
$(BUILD_DIR)/project.v: gen-sources
|
||||
cd $(BUILD_DIR); $(SCRIPT_DIR)/sv2v.sh -t$(TOP_LEVEL_ENTITY) -Isrc -oproject.v
|
||||
|
||||
build: $(BUILD_DIR)/project.v
|
||||
cd $(BUILD_DIR); ../synth.sh -t$(TOP_LEVEL_ENTITY) -sproject.v
|
||||
|
||||
elaborate: $(BUILD_DIR)/project.v
|
||||
cd $(BUILD_DIR); ../synth.sh -t$(TOP_LEVEL_ENTITY) -sproject.v -P="elaborate"
|
||||
|
||||
clean:
|
||||
rm -rf output.v *.ys *.log
|
||||
$(RMDIR) $(BUILD_DIR)
|
||||
|
||||
@@ -1,57 +0,0 @@
|
||||
#!/bin/bash
|
||||
|
||||
# this script uses sv2v and yosys tools to run.
|
||||
# sv2v: https://github.com/zachjs/sv2v
|
||||
# yosys: http://www.clifford.at/yosys/
|
||||
|
||||
# exit when any command fails
|
||||
set -e
|
||||
|
||||
source=""
|
||||
includes=()
|
||||
macro_args=""
|
||||
output_file=out.v
|
||||
|
||||
usage() { echo "$0 usage:" && grep " .)\ #" $0; exit 0; }
|
||||
[ $# -eq 0 ] && usage
|
||||
while getopts "o:I:D:h" arg; do
|
||||
case $arg in
|
||||
s) # source
|
||||
source=${OPTARG}
|
||||
;;
|
||||
o) # output-file
|
||||
output_file=${OPTARG}
|
||||
;;
|
||||
I) # include directory
|
||||
includes+=(${OPTARG})
|
||||
;;
|
||||
D) # macro definition
|
||||
macro_args="$macro_args -D${OPTARG}"
|
||||
;;
|
||||
h | *)
|
||||
usage
|
||||
exit 0
|
||||
;;
|
||||
esac
|
||||
done
|
||||
|
||||
# process include paths
|
||||
inc_args=""
|
||||
for dir in "${includes[@]}"
|
||||
do
|
||||
inc_args="$inc_args -I$dir"
|
||||
done
|
||||
|
||||
# process source files
|
||||
file_args=$source
|
||||
for dir in "${includes[@]}"
|
||||
do
|
||||
for file in $(find $dir -maxdepth 1 -name '*.v' -o -name '*.sv' -type f)
|
||||
do
|
||||
echo "file: $file"
|
||||
file_args="$file_args $file"
|
||||
done
|
||||
done
|
||||
|
||||
# system-verilog to verilog conversion
|
||||
sv2v $macro_args $inc_args $file_args -v -w $output_file
|
||||
@@ -1,5 +1,18 @@
|
||||
#!/bin/bash
|
||||
|
||||
# Copyright © 2019-2023
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
# this script uses sv2v and yosys tools to run.
|
||||
# sv2v: https://github.com/zachjs/sv2v
|
||||
# yosys: http://www.clifford.at/yosys/
|
||||
@@ -12,10 +25,48 @@ top_level=""
|
||||
dir_list=()
|
||||
inc_args=""
|
||||
macro_args=""
|
||||
no_warnings=1
|
||||
process="elaborate,netlist,techmap,verilog"
|
||||
|
||||
declare -a excluded_warnings=("Resizing cell port")
|
||||
|
||||
is_excluded_warning() {
|
||||
local warning_text="$1"
|
||||
for exclusion in "${excluded_warnings[@]}"; do
|
||||
if [[ "$warning_text" == *"$exclusion"* ]]; then
|
||||
return $no_warnings
|
||||
fi
|
||||
done
|
||||
return 1
|
||||
}
|
||||
|
||||
checkErrors()
|
||||
{
|
||||
log_file="$1"
|
||||
if grep -q "Error: " "$log_file"; then
|
||||
echo "Error: found errors during synthesis!"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
count=0
|
||||
while IFS= read -r line; do
|
||||
if [[ "$line" == *"Warning:"* ]]; then
|
||||
warning_text="${line#Warning: }"
|
||||
if ! is_excluded_warning "$warning_text"; then
|
||||
count=$(expr $count + 1)
|
||||
fi
|
||||
fi
|
||||
done < $log_file
|
||||
|
||||
if [ "$count" -ne 0 ]; then
|
||||
echo "Error: found $count unexpected warnings during synthesis!"
|
||||
exit $count
|
||||
fi
|
||||
}
|
||||
|
||||
usage() { echo "$0 usage:" && grep " .)\ #" $0; exit 0; }
|
||||
[ $# -eq 0 ] && usage
|
||||
while getopts "s:t:I:D:h" arg; do
|
||||
while getopts "s:t:I:D:P:Wh" arg; do
|
||||
case $arg in
|
||||
s) # source
|
||||
source=${OPTARG}
|
||||
@@ -30,6 +81,12 @@ while getopts "s:t:I:D:h" arg; do
|
||||
D) # macro definition
|
||||
macro_args="$macro_args -D${OPTARG}"
|
||||
;;
|
||||
P) # process
|
||||
process=${OPTARG}
|
||||
;;
|
||||
W) # allow warnings
|
||||
no_warnings=0
|
||||
;;
|
||||
h | *)
|
||||
usage
|
||||
exit 0
|
||||
@@ -43,23 +100,34 @@ done
|
||||
do
|
||||
for file in $(find $dir -maxdepth 1 -name '*.v' -o -name '*.sv' -type f)
|
||||
do
|
||||
echo "read_verilog $macro_args $inc_args -sv $file"
|
||||
echo "read_verilog -defer -nolatches $macro_args $inc_args -sv $file"
|
||||
done
|
||||
done
|
||||
if [ -n "$source" ]; then
|
||||
echo "read_verilog $macro_args $inc_args -sv $source"
|
||||
echo "read_verilog -defer -nolatches $macro_args $inc_args -sv $source"
|
||||
fi
|
||||
|
||||
# generic synthesis
|
||||
echo "synth -top $top_level"
|
||||
# elaborate
|
||||
if echo "$process" | grep -q "elaborate"; then
|
||||
echo "hierarchy -top $top_level"
|
||||
fi
|
||||
|
||||
# convert to netlist
|
||||
if echo "$process" | grep -q "netlist"; then
|
||||
echo "proc; opt"
|
||||
fi
|
||||
|
||||
# mapping to mycells.lib
|
||||
echo "dfflibmap -liberty mycells.lib"
|
||||
echo "abc -liberty mycells.lib"
|
||||
echo "clean"
|
||||
# convert to gate logic
|
||||
if echo "$process" | grep -q "techmap"; then
|
||||
echo "techmap; opt"
|
||||
fi
|
||||
|
||||
# write synthesized design
|
||||
echo "write_verilog synth.v"
|
||||
if echo "$process" | grep -q "verilog"; then
|
||||
echo "write_verilog synth.v"
|
||||
fi
|
||||
} > synth.ys
|
||||
|
||||
yosys -l yosys.log synth.ys
|
||||
yosys -l yosys.log synth.ys
|
||||
|
||||
checkErrors yosys.log
|
||||
|
||||
Reference in New Issue
Block a user