Vortex 2.0 changes:
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
This commit is contained in:
73
hw/scripts/sv2v.sh
Executable file
73
hw/scripts/sv2v.sh
Executable file
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#!/bin/bash
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# Copyright © 2019-2023
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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# this script uses sv2v and yosys tools to run.
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# sv2v: https://github.com/zachjs/sv2v
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# yosys: http://www.clifford.at/yosys/
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# exit when any command fails
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set -e
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source=""
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includes=()
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macro_args=""
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output_file=out.v
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usage() { echo "$0 usage:" && grep " .)\ #" $0; exit 0; }
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[ $# -eq 0 ] && usage
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while getopts "t:s:o:I:D:h" arg; do
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case $arg in
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t) # source
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top=--top=${OPTARG}
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;;
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s) # source
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source=${OPTARG}
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;;
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o) # output-file
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output_file=${OPTARG}
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;;
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I) # include directory
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includes+=(${OPTARG})
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;;
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D) # macro definition
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macro_args="$macro_args -D${OPTARG}"
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;;
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h | *)
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usage
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exit 0
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;;
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esac
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done
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# process include paths
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inc_args=""
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for dir in "${includes[@]}"
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do
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inc_args="$inc_args -I$dir"
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done
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# process source files
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file_args=$source
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for dir in "${includes[@]}"
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do
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for file in $(find $dir -maxdepth 1 -name '*.v' -o -name '*.sv' -type f)
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do
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echo "file: $file"
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file_args="$file_args $file"
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done
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done
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# system-verilog to verilog conversion
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sv2v $top $macro_args $inc_args $file_args -v -w $output_file
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