Vortex 2.0 changes:
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
This commit is contained in:
Blaise Tine
330
hw/rtl/mem/VX_shared_mem.sv
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330
hw/rtl/mem/VX_shared_mem.sv
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// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_define.vh"
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module VX_shared_mem #(
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parameter `STRING INSTANCE_ID = "",
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// Size of cache in bytes
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parameter SIZE = (1024*16*8),
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// Number of Word requests per cycle
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parameter NUM_REQS = 4,
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// Number of banks
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parameter NUM_BANKS = 4,
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// Address width
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parameter ADDR_WIDTH = `CLOG2(SIZE),
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// Size of a word in bytes
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parameter WORD_SIZE = `XLEN/8,
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// Request debug identifier
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parameter UUID_WIDTH = 0,
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// Request tag size
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parameter TAG_WIDTH = 16
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) (
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input wire clk,
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input wire reset,
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// PERF
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`ifdef PERF_ENABLE
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VX_cache_perf_if.master cache_perf_if,
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`endif
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// Core request
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input wire [NUM_REQS-1:0] req_valid,
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input wire [NUM_REQS-1:0] req_rw,
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input wire [NUM_REQS-1:0][ADDR_WIDTH-1:0] req_addr,
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input wire [NUM_REQS-1:0][WORD_SIZE-1:0] req_byteen,
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input wire [NUM_REQS-1:0][WORD_SIZE*8-1:0] req_data,
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input wire [NUM_REQS-1:0][TAG_WIDTH-1:0] req_tag,
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output wire [NUM_REQS-1:0] req_ready,
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// Core response
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output wire [NUM_REQS-1:0] rsp_valid,
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output wire [NUM_REQS-1:0][WORD_SIZE*8-1:0] rsp_data,
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output wire [NUM_REQS-1:0][TAG_WIDTH-1:0] rsp_tag,
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input wire [NUM_REQS-1:0] rsp_ready
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);
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`UNUSED_SPARAM (INSTANCE_ID)
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`UNUSED_PARAM (UUID_WIDTH)
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localparam REQ_SEL_BITS = `CLOG2(NUM_REQS);
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localparam REQ_SEL_WIDTH = `UP(REQ_SEL_BITS);
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localparam WORD_WIDTH = WORD_SIZE * 8;
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localparam NUM_WORDS = SIZE / WORD_SIZE;
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localparam WORDS_PER_BANK = NUM_WORDS / NUM_BANKS;
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localparam BANK_ADDR_WIDTH = `CLOG2(WORDS_PER_BANK);
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localparam BANK_SEL_BITS = `CLOG2(NUM_BANKS);
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localparam BANK_SEL_WIDTH = `UP(BANK_SEL_BITS);
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localparam REQ_DATAW = 1 + BANK_ADDR_WIDTH + WORD_SIZE + WORD_WIDTH + TAG_WIDTH;
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localparam RSP_DATAW = WORD_WIDTH + TAG_WIDTH;
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`STATIC_ASSERT(ADDR_WIDTH == (BANK_ADDR_WIDTH + `CLOG2(NUM_BANKS)), ("invalid parameter"))
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// bank selection
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wire [NUM_REQS-1:0][BANK_SEL_WIDTH-1:0] req_bank_idx;
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if (NUM_BANKS > 1) begin
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for (genvar i = 0; i < NUM_REQS; ++i) begin
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assign req_bank_idx[i] = req_addr[i][0 +: BANK_SEL_BITS];
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end
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end else begin
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assign req_bank_idx = 0;
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end
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// bank addressing
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wire [NUM_REQS-1:0][BANK_ADDR_WIDTH-1:0] req_bank_addr;
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for (genvar i = 0; i < NUM_REQS; ++i) begin
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assign req_bank_addr[i] = req_addr[i][BANK_SEL_BITS +: BANK_ADDR_WIDTH];
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end
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// bank requests dispatch
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wire [NUM_BANKS-1:0] per_bank_req_valid;
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wire [NUM_BANKS-1:0] per_bank_req_rw;
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wire [NUM_BANKS-1:0][BANK_ADDR_WIDTH-1:0] per_bank_req_addr;
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wire [NUM_BANKS-1:0][WORD_SIZE-1:0] per_bank_req_byteen;
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wire [NUM_BANKS-1:0][WORD_WIDTH-1:0] per_bank_req_data;
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wire [NUM_BANKS-1:0][TAG_WIDTH-1:0] per_bank_req_tag;
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wire [NUM_BANKS-1:0][REQ_SEL_WIDTH-1:0] per_bank_req_idx;
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wire [NUM_BANKS-1:0] per_bank_req_ready;
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wire [NUM_REQS-1:0][REQ_DATAW-1:0] req_data_in;
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wire [NUM_BANKS-1:0][REQ_DATAW-1:0] req_data_out;
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for (genvar i = 0; i < NUM_REQS; ++i) begin
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assign req_data_in[i] = {
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req_rw[i],
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req_bank_addr[i],
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req_byteen[i],
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req_data[i],
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req_tag[i]};
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end
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VX_stream_xbar #(
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.NUM_INPUTS (NUM_REQS),
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.NUM_OUTPUTS (NUM_BANKS),
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.DATAW (REQ_DATAW),
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.PERF_CTR_BITS (`PERF_CTR_BITS),
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.OUT_REG (3) // output should be registered for the data_store addressing
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) req_xbar (
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.clk (clk),
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.reset (reset),
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`ifdef PERF_ENABLE
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.collisions (cache_perf_if.bank_stalls),
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`else
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`UNUSED_PIN (collisions),
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`endif
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.valid_in (req_valid),
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.data_in (req_data_in),
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.sel_in (req_bank_idx),
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.ready_in (req_ready),
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.valid_out (per_bank_req_valid),
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.data_out (req_data_out),
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.sel_out (per_bank_req_idx),
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.ready_out (per_bank_req_ready)
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);
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for (genvar i = 0; i < NUM_BANKS; ++i) begin
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assign {
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per_bank_req_rw[i],
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per_bank_req_addr[i],
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per_bank_req_byteen[i],
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per_bank_req_data[i],
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per_bank_req_tag[i]} = req_data_out[i];
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end
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// banks access
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wire [NUM_BANKS-1:0] per_bank_rsp_valid;
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wire [NUM_BANKS-1:0][WORD_WIDTH-1:0] per_bank_rsp_data;
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wire [NUM_BANKS-1:0][REQ_SEL_WIDTH-1:0] per_bank_rsp_idx;
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wire [NUM_BANKS-1:0][TAG_WIDTH-1:0] per_bank_rsp_tag;
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wire [NUM_BANKS-1:0] per_bank_rsp_ready;
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for (genvar i = 0; i < NUM_BANKS; ++i) begin
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VX_sp_ram #(
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.DATAW (WORD_WIDTH),
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.SIZE (WORDS_PER_BANK),
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.WRENW (WORD_SIZE)
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) data_store (
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.clk (clk),
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.read (1'b1),
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.write (per_bank_req_valid[i] && per_bank_req_ready[i] && per_bank_req_rw[i]),
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.wren (per_bank_req_byteen[i]),
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.addr (per_bank_req_addr[i]),
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.wdata (per_bank_req_data[i]),
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.rdata (per_bank_rsp_data[i])
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);
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// drop write response
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wire per_bank_req_valid_w, per_bank_req_ready_w;
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assign per_bank_req_valid_w = per_bank_req_valid[i] && ~per_bank_req_rw[i];
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assign per_bank_req_ready[i] = per_bank_req_ready_w || per_bank_req_rw[i];
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VX_elastic_buffer #(
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.DATAW (REQ_SEL_WIDTH + TAG_WIDTH),
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.SIZE (0)
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) bank_buf (
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.clk (clk),
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.reset (reset),
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.valid_in (per_bank_req_valid_w),
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.ready_in (per_bank_req_ready_w),
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.data_in ({per_bank_req_idx[i], per_bank_req_tag[i]}),
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.data_out ({per_bank_rsp_idx[i], per_bank_rsp_tag[i]}),
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.valid_out (per_bank_rsp_valid[i]),
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.ready_out (per_bank_rsp_ready[i])
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);
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end
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// bank responses gather
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wire [NUM_BANKS-1:0][RSP_DATAW-1:0] rsp_data_in;
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wire [NUM_REQS-1:0][RSP_DATAW-1:0] rsp_data_out;
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for (genvar i = 0; i < NUM_BANKS; ++i) begin
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assign rsp_data_in[i] = {per_bank_rsp_data[i], per_bank_rsp_tag[i]};
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end
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VX_stream_xbar #(
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.NUM_INPUTS (NUM_BANKS),
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.NUM_OUTPUTS (NUM_REQS),
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.DATAW (RSP_DATAW),
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.OUT_REG (2)
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) rsp_xbar (
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.clk (clk),
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.reset (reset),
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`UNUSED_PIN (collisions),
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.sel_in (per_bank_rsp_idx),
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.valid_in (per_bank_rsp_valid),
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.ready_in (per_bank_rsp_ready),
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.data_in (rsp_data_in),
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.data_out (rsp_data_out),
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.valid_out (rsp_valid),
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.ready_out (rsp_ready),
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`UNUSED_PIN (sel_out)
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);
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for (genvar i = 0; i < NUM_REQS; ++i) begin
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assign {rsp_data[i], rsp_tag[i]} = rsp_data_out[i];
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end
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`ifdef PERF_ENABLE
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// per cycle: reads, writes
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wire [`CLOG2(NUM_REQS+1)-1:0] perf_reads_per_cycle;
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wire [`CLOG2(NUM_REQS+1)-1:0] perf_writes_per_cycle;
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wire [`CLOG2(NUM_REQS+1)-1:0] perf_crsp_stall_per_cycle;
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wire [NUM_REQS-1:0] perf_reads_per_req = req_valid & req_ready & ~req_rw;
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wire [NUM_REQS-1:0] perf_writes_per_req = req_valid & req_ready & req_rw;
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wire [NUM_REQS-1:0] perf_crsp_stall_per_req = rsp_valid & ~rsp_ready;
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`POP_COUNT(perf_reads_per_cycle, perf_reads_per_req);
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`POP_COUNT(perf_writes_per_cycle, perf_writes_per_req);
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`POP_COUNT(perf_crsp_stall_per_cycle, perf_crsp_stall_per_req);
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reg [`PERF_CTR_BITS-1:0] perf_reads;
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reg [`PERF_CTR_BITS-1:0] perf_writes;
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reg [`PERF_CTR_BITS-1:0] perf_crsp_stalls;
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always @(posedge clk) begin
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if (reset) begin
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perf_reads <= '0;
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perf_writes <= '0;
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perf_crsp_stalls <= '0;
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end else begin
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perf_reads <= perf_reads + `PERF_CTR_BITS'(perf_reads_per_cycle);
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perf_writes <= perf_writes + `PERF_CTR_BITS'(perf_writes_per_cycle);
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perf_crsp_stalls <= perf_crsp_stalls + `PERF_CTR_BITS'(perf_crsp_stall_per_cycle);
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end
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end
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assign cache_perf_if.reads = perf_reads;
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assign cache_perf_if.writes = perf_writes;
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assign cache_perf_if.read_misses = '0;
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assign cache_perf_if.write_misses = '0;
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assign cache_perf_if.mshr_stalls = '0;
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assign cache_perf_if.mem_stalls = '0;
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assign cache_perf_if.crsp_stalls = perf_crsp_stalls;
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`endif
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`ifdef DBG_TRACE_CACHE_BANK
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wire [NUM_REQS-1:0][`UP(UUID_WIDTH)-1:0] req_uuid;
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wire [NUM_REQS-1:0][`UP(UUID_WIDTH)-1:0] rsp_uuid;
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for (genvar i = 0; i < NUM_REQS; ++i) begin
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if (UUID_WIDTH != 0) begin
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assign req_uuid[i] = req_tag[i][TAG_WIDTH-1 -: UUID_WIDTH];
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assign rsp_uuid[i] = rsp_tag[i][TAG_WIDTH-1 -: UUID_WIDTH];
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end else begin
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assign req_uuid[i] = 0;
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assign rsp_uuid[i] = 0;
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end
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end
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wire [NUM_BANKS-1:0][`UP(UUID_WIDTH)-1:0] per_bank_req_uuid;
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wire [NUM_BANKS-1:0][`UP(UUID_WIDTH)-1:0] per_bank_rsp_uuid;
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for (genvar i = 0; i < NUM_BANKS; ++i) begin
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if (UUID_WIDTH != 0) begin
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assign per_bank_req_uuid[i] = per_bank_req_tag[i][TAG_WIDTH-1 -: UUID_WIDTH];
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assign per_bank_rsp_uuid[i] = per_bank_rsp_tag[i][TAG_WIDTH-1 -: UUID_WIDTH];
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end else begin
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assign per_bank_req_uuid[i] = 0;
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assign per_bank_rsp_uuid[i] = 0;
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end
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end
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always @(posedge clk) begin
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for (integer i = 0; i < NUM_REQS; ++i) begin
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if (req_valid[i] && req_ready[i]) begin
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if (req_rw[i]) begin
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`TRACE(1, ("%d: %s wr-req: req_idx=%0d, addr=0x%0h, tag=0x%0h, byteen=%b, data=0x%0h (#%0d)\n",
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$time, INSTANCE_ID, i, req_addr[i], req_tag[i], req_byteen[i], req_data[i], req_uuid[i]));
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end else begin
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`TRACE(1, ("%d: %s rd-req: req_idx=%0d, addr=0x%0h, tag=0x%0h (#%0d)\n",
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$time, INSTANCE_ID, i, req_addr[i], req_tag[i], req_uuid[i]));
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end
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end
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if (rsp_valid[i] && rsp_ready[i]) begin
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`TRACE(1, ("%d: %s rd-rsp: req_idx=%0d, tag=0x%0h, data=0x%0h (#%0d)\n",
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$time, INSTANCE_ID, i, rsp_tag[i], rsp_data[i], rsp_uuid[i]));
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end
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end
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for (integer i = 0; i < NUM_BANKS; ++i) begin
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if (per_bank_req_valid[i] && per_bank_req_ready[i]) begin
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if (per_bank_req_rw[i]) begin
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`TRACE(2, ("%d: %s-bank%0d wr-req: addr=0x%0h, tag=0x%0h, byteen=%b, data=0x%0h (#%0d)\n",
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$time, INSTANCE_ID, i, per_bank_req_addr[i], per_bank_req_tag[i], per_bank_req_byteen[i], per_bank_req_data[i], per_bank_req_uuid[i]));
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end else begin
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`TRACE(2, ("%d: %s-bank%0d rd-req: addr=0x%0h, tag=0x%0h (#%0d)\n",
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$time, INSTANCE_ID, i, per_bank_req_addr[i], per_bank_req_tag[i], per_bank_req_uuid[i]));
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end
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end
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if (per_bank_rsp_valid[i] && per_bank_rsp_ready[i]) begin
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`TRACE(2, ("%d: %s-bank%0d rd-rsp: tag=0x%0h, data=0x%0h (#%0d)\n",
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$time, INSTANCE_ID, i, per_bank_rsp_tag[i], per_bank_rsp_data[i], per_bank_rsp_uuid[i]));
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end
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end
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end
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`endif
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endmodule
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