Vortex 2.0 changes:
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
This commit is contained in:
Blaise Tine
207
hw/rtl/libs/VX_stream_xbar.sv
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207
hw/rtl/libs/VX_stream_xbar.sv
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// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_define.vh"
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`TRACING_OFF
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module VX_stream_xbar #(
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parameter NUM_INPUTS = 4,
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parameter NUM_OUTPUTS = 4,
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parameter DATAW = 4,
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parameter IN_WIDTH = `LOG2UP(NUM_INPUTS),
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parameter OUT_WIDTH = `LOG2UP(NUM_OUTPUTS),
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parameter ARBITER = "P",
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parameter LOCK_ENABLE = 0,
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parameter OUT_REG = 0,
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parameter MAX_FANOUT = `MAX_FANOUT,
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parameter PERF_CTR_BITS = `CLOG2(NUM_INPUTS+1)
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) (
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input wire clk,
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input wire reset,
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output wire [PERF_CTR_BITS-1:0] collisions,
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input wire [NUM_INPUTS-1:0] valid_in,
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input wire [NUM_INPUTS-1:0][DATAW-1:0] data_in,
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input wire [NUM_INPUTS-1:0][OUT_WIDTH-1:0] sel_in,
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output wire [NUM_INPUTS-1:0] ready_in,
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output wire [NUM_OUTPUTS-1:0] valid_out,
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output wire [NUM_OUTPUTS-1:0][DATAW-1:0] data_out,
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output wire [NUM_OUTPUTS-1:0][IN_WIDTH-1:0] sel_out,
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input wire [NUM_OUTPUTS-1:0] ready_out
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);
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`UNUSED_VAR (clk)
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`UNUSED_VAR (reset)
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if (NUM_INPUTS != 1) begin
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if (NUM_OUTPUTS != 1) begin
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// (#inputs > 1) and (#outputs > 1)
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wire [NUM_OUTPUTS-1:0][NUM_INPUTS-1:0] per_output_ready_in;
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for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin
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wire [NUM_INPUTS-1:0] valid_in_q;
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for (genvar j = 0; j < NUM_INPUTS; ++j) begin
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assign valid_in_q[j] = valid_in[j] && (sel_in[j] == i);
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end
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`RESET_RELAY (slice_reset, reset);
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VX_stream_arb #(
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.NUM_INPUTS (NUM_INPUTS),
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.NUM_OUTPUTS (1),
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.DATAW (DATAW),
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.ARBITER (ARBITER),
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.LOCK_ENABLE (LOCK_ENABLE),
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.MAX_FANOUT (MAX_FANOUT),
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.OUT_REG (OUT_REG)
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) xbar_arb (
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.clk (clk),
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.reset (slice_reset),
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.valid_in (valid_in_q),
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.data_in (data_in),
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.ready_in (per_output_ready_in[i]),
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.valid_out (valid_out[i]),
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.data_out (data_out[i]),
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.sel_out (sel_out[i]),
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.ready_out (ready_out[i])
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);
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end
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for (genvar i = 0; i < NUM_INPUTS; ++i) begin
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assign ready_in[i] = per_output_ready_in[sel_in[i]][i];
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end
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end else begin
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// (#inputs >= 1) and (#outputs == 1)
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VX_stream_arb #(
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.NUM_INPUTS (NUM_INPUTS),
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.NUM_OUTPUTS (1),
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.DATAW (DATAW),
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.ARBITER (ARBITER),
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.LOCK_ENABLE (LOCK_ENABLE),
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.MAX_FANOUT (MAX_FANOUT),
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.OUT_REG (OUT_REG)
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) xbar_arb (
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.clk (clk),
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.reset (reset),
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.valid_in (valid_in),
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.data_in (data_in),
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.ready_in (ready_in),
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.valid_out (valid_out),
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.data_out (data_out),
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.sel_out (sel_out),
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.ready_out (ready_out)
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);
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`UNUSED_VAR (sel_in)
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end
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end else if (NUM_OUTPUTS != 1) begin
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// (#inputs == 1) and (#outputs > 1)
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logic [NUM_OUTPUTS-1:0] valid_out_r, ready_out_r;
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logic [NUM_OUTPUTS-1:0][DATAW-1:0] data_out_r;
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always @(*) begin
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valid_out_r = '0;
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valid_out_r[sel_in] = valid_in;
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end
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assign data_out_r = {NUM_OUTPUTS{data_in}};
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assign ready_in = ready_out_r[sel_in];
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for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin
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`RESET_RELAY (out_buf_reset, reset);
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VX_elastic_buffer #(
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.DATAW (DATAW),
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.SIZE (`OUT_REG_TO_EB_SIZE(OUT_REG)),
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.OUT_REG (`OUT_REG_TO_EB_REG(OUT_REG))
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) out_buf (
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.clk (clk),
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.reset (out_buf_reset),
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.valid_in (valid_out_r[i]),
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.ready_in (ready_out_r[i]),
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.data_in (data_out_r[i]),
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.data_out (data_out[i]),
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.valid_out (valid_out[i]),
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.ready_out (ready_out[i])
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);
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end
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assign sel_out = 0;
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end else begin
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// (#inputs == 1) and (#outputs == 1)
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VX_elastic_buffer #(
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.DATAW (DATAW),
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.SIZE (`OUT_REG_TO_EB_SIZE(OUT_REG)),
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.OUT_REG (`OUT_REG_TO_EB_REG(OUT_REG))
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) out_buf (
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.clk (clk),
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.reset (reset),
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.valid_in (valid_in),
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.ready_in (ready_in),
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.data_in (data_in),
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.data_out (data_out),
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.valid_out (valid_out),
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.ready_out (ready_out)
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);
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`UNUSED_VAR (sel_in)
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assign sel_out = 0;
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end
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// compute inputs collision
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// we have a collision when there exists a valid transfer with mutiple input candicates
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// we caount the unique duplicates each cycle.
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reg [PERF_CTR_BITS-1:0] collisions_r;
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reg [NUM_INPUTS-1:0] per_cycle_collision;
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always @(*) begin
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per_cycle_collision = 0;
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for (integer i = 0; i < NUM_INPUTS; ++i) begin
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for (integer j = 1; j < (NUM_INPUTS-i); ++j) begin
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if (valid_in[i] && valid_in[j+i] && sel_in[i] == sel_in[j+i]) begin
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per_cycle_collision[i] |= ready_in[i] | ready_in[j+i];
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end
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end
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end
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end
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wire [`CLOG2(NUM_INPUTS+1)-1:0] collision_count;
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`POP_COUNT(collision_count, per_cycle_collision);
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always @(posedge clk) begin
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if (reset) begin
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collisions_r <= '0;
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end else begin
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collisions_r <= collisions_r + PERF_CTR_BITS'(collision_count);
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end
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end
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assign collisions = collisions_r;
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endmodule
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`TRACING_ON
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