wu-arch/vortex
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Vortex 2.0 changes:

Browse Source 
+ Microarchitecture optimizations
+ 64-bit support
+ Xilinx FPGA support
+ LLVM-16 support
+ Refactoring and quality control fixes
This commit is contained in:
Blaise Tine
2023-10-19 20:51:22 -07:00
parent d69a64c32c
commit d47cccc157
1300 changed files with 247321 additions and 311189 deletions
Download Patch File Download Diff File Expand all files Collapse all files

108
hw/rtl/libs/VX_serial_div.sv
View File

@@ -1,32 +1,41 @@
// Copyright © 2019-2023
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
`include "VX_platform.vh"
`TRACING_OFF
module VX_serial_div #(
parameter WIDTHN = 1,
parameter WIDTHD = 1,
parameter WIDTHQ = 1,
parameter WIDTHR = 1,
parameter LANES = 1,
parameter TAGW = 1
parameter WIDTHN = 32,
parameter WIDTHD = 32,
parameter WIDTHQ = 32,
parameter WIDTHR = 32,
parameter LANES = 1
) (
input wire clk,
input wire reset,
input wire clk,
input wire reset,
input wire valid_in,
output wire ready_in,
input wire strobe,
output wire busy,
input wire is_signed,
input wire [LANES-1:0][WIDTHN-1:0] numer,
input wire [LANES-1:0][WIDTHD-1:0] denom,
input wire signed_mode,
input wire [TAGW-1:0] tag_in,
input wire [LANES-1:0][WIDTHD-1:0] denom,
output wire [LANES-1:0][WIDTHQ-1:0] quotient,
output wire [LANES-1:0][WIDTHR-1:0] remainder,
input wire ready_out,
output wire valid_out,
output wire [TAGW-1:0] tag_out
output wire [LANES-1:0][WIDTHR-1:0] remainder
);
localparam MIN_ND = (WIDTHN < WIDTHD) ? WIDTHN : WIDTHD;
localparam CNTRW = $clog2(WIDTHN+1);
localparam CNTRW = `CLOG2(WIDTHN);
reg [LANES-1:0][WIDTHN + MIN_ND:0] working;
reg [LANES-1:0][WIDTHD-1:0] denom_r;
@@ -38,18 +47,11 @@ module VX_serial_div #(
reg [LANES-1:0] inv_quot, inv_rem;
reg [CNTRW-1:0] cntr;
reg is_busy;
reg [TAGW-1:0] tag_r;
wire done = ~(| cntr);
wire push = valid_in && ready_in;
wire pop = valid_out && ready_out;
reg busy_r;
for (genvar i = 0; i < LANES; ++i) begin
wire negate_numer = signed_mode && numer[i][WIDTHN-1];
wire negate_denom = signed_mode && denom[i][WIDTHD-1];
wire negate_numer = is_signed && numer[i][WIDTHN-1];
wire negate_denom = is_signed && denom[i][WIDTHD-1];
assign numer_qual[i] = negate_numer ? -$signed(numer[i]) : numer[i];
assign denom_qual[i] = negate_denom ? -$signed(denom[i]) : denom[i];
assign sub_result[i] = working[i][WIDTHN + MIN_ND : WIDTHN] - denom_r[i];
@@ -57,46 +59,40 @@ module VX_serial_div #(
always @(posedge clk) begin
if (reset) begin
cntr <= 0;
is_busy <= 0;
busy_r <= 0;
end else begin
if (push) begin
cntr <= WIDTHN;
is_busy <= 1;
end else if (!done) begin
cntr <= cntr - CNTRW'(1);
if (strobe) begin
busy_r <= 1;
end
if (pop) begin
is_busy <= 0;
if (busy && cntr == 0) begin
busy_r <= 0;
end
end
if (push) begin
for (integer i = 0; i < LANES; ++i) begin
working[i] <= {{WIDTHD{1'b0}}, numer_qual[i], 1'b0};
denom_r[i] <= denom_qual[i];
inv_quot[i] <= (denom[i] != 0) && signed_mode && (numer[i][31] ^ denom[i][31]);
inv_rem[i] <= signed_mode && numer[i][31];
end
tag_r <= tag_in;
end else if (!done) begin
for (integer i = 0; i < LANES; ++i) begin
working[i] <= sub_result[i][WIDTHD] ? {working[i][WIDTHN+MIN_ND-1:0], 1'b0} :
{sub_result[i][WIDTHD-1:0], working[i][WIDTHN-1:0], 1'b1};
end
cntr <= cntr - CNTRW'(1);
if (strobe) begin
cntr <= CNTRW'(WIDTHN-1);
end
end
for (genvar i = 0; i < LANES; ++i) begin
always @(posedge clk) begin
if (strobe) begin
working[i] <= {{WIDTHD{1'b0}}, numer_qual[i], 1'b0};
denom_r[i] <= denom_qual[i];
inv_quot[i] <= (denom[i] != 0) && is_signed && (numer[i][31] ^ denom[i][31]);
inv_rem[i] <= is_signed && numer[i][31];
end else if (busy_r) begin
working[i] <= sub_result[i][WIDTHD] ? {working[i][WIDTHN+MIN_ND-1:0], 1'b0} :
{sub_result[i][WIDTHD-1:0], working[i][WIDTHN-1:0], 1'b1};
end
end
wire [WIDTHQ-1:0] q = working[i][WIDTHQ-1:0];
wire [WIDTHR-1:0] r = working[i][WIDTHN+WIDTHR:WIDTHN+1];
assign quotient[i] = inv_quot[i] ? -$signed(q) : q;
assign remainder[i] = inv_rem[i] ? -$signed(r) : r;
end
assign ready_in = !is_busy;
assign tag_out = tag_r;
assign valid_out = is_busy && done;
assign busy = busy_r;
endmodule
`TRACING_ON
`TRACING_ON