wu-arch/vortex
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Vortex 2.0 changes:

Browse Source 
+ Microarchitecture optimizations
+ 64-bit support
+ Xilinx FPGA support
+ LLVM-16 support
+ Refactoring and quality control fixes
This commit is contained in:
Blaise Tine
2023-10-19 20:51:22 -07:00
parent d69a64c32c
commit d47cccc157
1300 changed files with 247321 additions and 311189 deletions
Download Patch File Download Diff File Expand all files Collapse all files

43
hw/rtl/libs/VX_matrix_arbiter.sv
View File

@@ -1,26 +1,39 @@
// Copyright © 2019-2023
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
`include "VX_platform.vh"
`TRACING_OFF
module VX_matrix_arbiter #(
parameter NUM_REQS = 1,
parameter LOCK_ENABLE = 0,
parameter LOG_NUM_REQS = $clog2(NUM_REQS)
parameter LOG_NUM_REQS = `LOG2UP(NUM_REQS)
) (
input wire clk,
input wire reset,
input wire enable,
input wire unlock,
input wire [NUM_REQS-1:0] requests,
output wire [LOG_NUM_REQS-1:0] grant_index,
output wire [NUM_REQS-1:0] grant_onehot,
output wire grant_valid
);
);
if (NUM_REQS == 1) begin
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
`UNUSED_VAR (unlock)
assign grant_index = 0;
assign grant_index = '0;
assign grant_onehot = requests;
assign grant_valid = requests[0];
@@ -30,8 +43,8 @@ module VX_matrix_arbiter #(
wire [NUM_REQS-1:0] pri [NUM_REQS-1:0];
wire [NUM_REQS-1:0] grant_unqual;
for (genvar i = 0; i < NUM_REQS; i++) begin
for (genvar j = 0; j < NUM_REQS; j++) begin
for (genvar i = 0; i < NUM_REQS; ++i) begin
for (genvar j = 0; j < NUM_REQS; ++j) begin
if (j > i) begin
assign pri[j][i] = requests[i] && state[i][j];
end
@@ -45,11 +58,11 @@ module VX_matrix_arbiter #(
assign grant_unqual[i] = requests[i] && !(| pri[i]);
end
for (genvar i = 0; i < NUM_REQS; i++) begin
for (genvar j = i + 1; j < NUM_REQS; j++) begin
for (genvar i = 0; i < NUM_REQS; ++i) begin
for (genvar j = i + 1; j < NUM_REQS; ++j) begin
always @(posedge clk) begin
if (reset) begin
state[i][j] <= 0;
state[i][j] <= '0;
end else begin
state[i][j] <= (state[i][j] || grant_unqual[j]) && !grant_unqual[i];
end
@@ -58,18 +71,18 @@ module VX_matrix_arbiter #(
end
if (LOCK_ENABLE == 0) begin
`UNUSED_VAR (enable)
`UNUSED_VAR (unlock)
assign grant_onehot = grant_unqual;
end else begin
reg [NUM_REQS-1:0] grant_unqual_prev;
always @(posedge clk) begin
if (reset) begin
grant_unqual_prev <= 0;
end else if (enable) begin
grant_unqual_prev <= '0;
end else if (unlock) begin
grant_unqual_prev <= grant_unqual;
end
end
assign grant_onehot = enable ? grant_unqual : grant_unqual_prev;
assign grant_onehot = unlock ? grant_unqual : grant_unqual_prev;
end
VX_onehot_encoder #(
@@ -85,4 +98,4 @@ module VX_matrix_arbiter #(
end
endmodule
`TRACING_ON
`TRACING_ON