Vortex 2.0 changes:
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
This commit is contained in:
Blaise Tine
@@ -1,154 +1,225 @@
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`include "VX_define.vh"
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// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_platform.vh"
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`TRACING_OFF
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module VX_axi_adapter #(
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parameter VX_DATA_WIDTH = 512,
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parameter VX_ADDR_WIDTH = (32 - $clog2(VX_DATA_WIDTH/8)),
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parameter VX_TAG_WIDTH = 8,
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parameter AXI_DATA_WIDTH = VX_DATA_WIDTH,
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parameter AXI_ADDR_WIDTH = 32,
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parameter AXI_TID_WIDTH = VX_TAG_WIDTH,
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parameter VX_BYTEEN_WIDTH = (VX_DATA_WIDTH / 8),
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parameter AXI_STROBE_WIDTH = (AXI_DATA_WIDTH / 8)
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parameter DATA_WIDTH = 512,
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parameter ADDR_WIDTH = 32,
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parameter TAG_WIDTH = 8,
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parameter NUM_BANKS = 1,
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parameter AVS_ADDR_WIDTH = (ADDR_WIDTH - `CLOG2(DATA_WIDTH/8)),
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parameter OUT_REG_RSP = 0
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) (
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input wire clk,
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input wire reset,
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input wire clk,
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input wire reset,
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// Vortex request
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input wire mem_req_valid,
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input wire mem_req_rw,
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input wire [VX_BYTEEN_WIDTH-1:0] mem_req_byteen,
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input wire [VX_ADDR_WIDTH-1:0] mem_req_addr,
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input wire [VX_DATA_WIDTH-1:0] mem_req_data,
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input wire [VX_TAG_WIDTH-1:0] mem_req_tag,
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input wire mem_req_valid,
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input wire mem_req_rw,
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input wire [DATA_WIDTH/8-1:0] mem_req_byteen,
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input wire [AVS_ADDR_WIDTH-1:0] mem_req_addr,
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input wire [DATA_WIDTH-1:0] mem_req_data,
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input wire [TAG_WIDTH-1:0] mem_req_tag,
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output wire mem_req_ready,
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// Vortex response
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input wire mem_rsp_ready,
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output wire mem_rsp_valid,
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output wire [VX_DATA_WIDTH-1:0] mem_rsp_data,
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output wire [VX_TAG_WIDTH-1:0] mem_rsp_tag,
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output wire mem_req_ready,
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// Vortex response
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output wire mem_rsp_valid,
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output wire [DATA_WIDTH-1:0] mem_rsp_data,
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output wire [TAG_WIDTH-1:0] mem_rsp_tag,
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input wire mem_rsp_ready,
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// AXI write request address channel
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output wire [AXI_TID_WIDTH-1:0] m_axi_awid,
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output wire [AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
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output wire [7:0] m_axi_awlen,
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output wire [2:0] m_axi_awsize,
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output wire [1:0] m_axi_awburst,
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output wire m_axi_awlock,
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output wire [3:0] m_axi_awcache,
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output wire [2:0] m_axi_awprot,
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output wire [3:0] m_axi_awqos,
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output wire m_axi_awvalid,
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input wire m_axi_awready,
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// AXI write request address channel
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output wire m_axi_awvalid [NUM_BANKS],
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input wire m_axi_awready [NUM_BANKS],
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output wire [ADDR_WIDTH-1:0] m_axi_awaddr [NUM_BANKS],
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output wire [TAG_WIDTH-1:0] m_axi_awid [NUM_BANKS],
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output wire [7:0] m_axi_awlen [NUM_BANKS],
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output wire [2:0] m_axi_awsize [NUM_BANKS],
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output wire [1:0] m_axi_awburst [NUM_BANKS],
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output wire [1:0] m_axi_awlock [NUM_BANKS],
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output wire [3:0] m_axi_awcache [NUM_BANKS],
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output wire [2:0] m_axi_awprot [NUM_BANKS],
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output wire [3:0] m_axi_awqos [NUM_BANKS],
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output wire [3:0] m_axi_awregion [NUM_BANKS],
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// AXI write request data channel
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output wire [AXI_DATA_WIDTH-1:0] m_axi_wdata,
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output wire [AXI_STROBE_WIDTH-1:0] m_axi_wstrb,
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output wire m_axi_wlast,
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output wire m_axi_wvalid,
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input wire m_axi_wready,
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// AXI write request data channel
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output wire m_axi_wvalid [NUM_BANKS],
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input wire m_axi_wready [NUM_BANKS],
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output wire [DATA_WIDTH-1:0] m_axi_wdata [NUM_BANKS],
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output wire [DATA_WIDTH/8-1:0] m_axi_wstrb [NUM_BANKS],
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output wire m_axi_wlast [NUM_BANKS],
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// AXI write response channel
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input wire [AXI_TID_WIDTH-1:0] m_axi_bid,
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input wire [1:0] m_axi_bresp,
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input wire m_axi_bvalid,
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output wire m_axi_bready,
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input wire m_axi_bvalid [NUM_BANKS],
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output wire m_axi_bready [NUM_BANKS],
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input wire [TAG_WIDTH-1:0] m_axi_bid [NUM_BANKS],
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input wire [1:0] m_axi_bresp [NUM_BANKS],
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// AXI read address channel
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output wire [AXI_TID_WIDTH-1:0] m_axi_arid,
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output wire [AXI_ADDR_WIDTH-1:0] m_axi_araddr,
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output wire [7:0] m_axi_arlen,
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output wire [2:0] m_axi_arsize,
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output wire [1:0] m_axi_arburst,
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output wire m_axi_arlock,
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output wire [3:0] m_axi_arcache,
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output wire [2:0] m_axi_arprot,
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output wire [3:0] m_axi_arqos,
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output wire m_axi_arvalid,
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input wire m_axi_arready,
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output wire m_axi_arvalid [NUM_BANKS],
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input wire m_axi_arready [NUM_BANKS],
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output wire [ADDR_WIDTH-1:0] m_axi_araddr [NUM_BANKS],
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output wire [TAG_WIDTH-1:0] m_axi_arid [NUM_BANKS],
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output wire [7:0] m_axi_arlen [NUM_BANKS],
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output wire [2:0] m_axi_arsize [NUM_BANKS],
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output wire [1:0] m_axi_arburst [NUM_BANKS],
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output wire [1:0] m_axi_arlock [NUM_BANKS],
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output wire [3:0] m_axi_arcache [NUM_BANKS],
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output wire [2:0] m_axi_arprot [NUM_BANKS],
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output wire [3:0] m_axi_arqos [NUM_BANKS],
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output wire [3:0] m_axi_arregion [NUM_BANKS],
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// AXI read response channel
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input wire [AXI_TID_WIDTH-1:0] m_axi_rid,
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input wire [AXI_DATA_WIDTH-1:0] m_axi_rdata,
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input wire [1:0] m_axi_rresp,
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input wire m_axi_rlast,
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input wire m_axi_rvalid,
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output wire m_axi_rready
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);
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localparam AXSIZE = $clog2(VX_DATA_WIDTH/8);
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input wire m_axi_rvalid [NUM_BANKS],
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output wire m_axi_rready [NUM_BANKS],
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input wire [DATA_WIDTH-1:0] m_axi_rdata [NUM_BANKS],
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input wire m_axi_rlast [NUM_BANKS],
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input wire [TAG_WIDTH-1:0] m_axi_rid [NUM_BANKS],
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input wire [1:0] m_axi_rresp [NUM_BANKS]
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);
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localparam AXSIZE = `CLOG2(DATA_WIDTH/8);
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localparam BANK_ADDRW = `LOG2UP(NUM_BANKS);
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localparam LOG2_NUM_BANKS = `CLOG2(NUM_BANKS);
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`STATIC_ASSERT((AXI_DATA_WIDTH == VX_DATA_WIDTH), ("invalid parameter"))
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`STATIC_ASSERT((AXI_TID_WIDTH == VX_TAG_WIDTH), ("invalid parameter"))
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wire [BANK_ADDRW-1:0] req_bank_sel;
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//`UNUSED_VAR ()
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reg awvalid_ack;
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reg wvalid_ack;
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if (NUM_BANKS > 1) begin
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assign req_bank_sel = mem_req_addr[BANK_ADDRW-1:0];
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end else begin
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assign req_bank_sel = '0;
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end
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wire mem_req_fire = mem_req_valid && mem_req_ready;
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always @(posedge clk) begin
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if (reset) begin
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awvalid_ack <= 0;
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wvalid_ack <= 0;
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end else begin
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if (mem_req_fire) begin
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awvalid_ack <= 0;
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wvalid_ack <= 0;
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end else begin
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awvalid_ack <= m_axi_awvalid && m_axi_awready;
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wvalid_ack <= m_axi_wvalid && m_axi_wready;
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reg [NUM_BANKS-1:0] m_axi_aw_ack;
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reg [NUM_BANKS-1:0] m_axi_w_ack;
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for (genvar i = 0; i < NUM_BANKS; ++i) begin
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wire m_axi_aw_fire = m_axi_awvalid[i] && m_axi_awready[i];
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wire m_axi_w_fire = m_axi_wvalid[i] && m_axi_wready[i];
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always @(posedge clk) begin
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if (reset) begin
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m_axi_aw_ack[i] <= 0;
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m_axi_w_ack[i] <= 0;
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end else begin
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if (mem_req_fire && (req_bank_sel == i)) begin
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m_axi_aw_ack[i] <= 0;
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m_axi_w_ack[i] <= 0;
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end else begin
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if (m_axi_aw_fire)
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m_axi_aw_ack[i] <= 1;
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if (m_axi_w_fire)
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m_axi_w_ack[i] <= 1;
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end
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end
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end
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end
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end
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end
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wire axi_write_ready = (m_axi_awready || awvalid_ack) && (m_axi_wready || wvalid_ack);
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wire axi_write_ready [NUM_BANKS];
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// AXI write request address channel
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assign m_axi_awvalid = mem_req_valid && mem_req_rw && !awvalid_ack;
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assign m_axi_awid = mem_req_tag;
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assign m_axi_awaddr = AXI_ADDR_WIDTH'(mem_req_addr) << AXSIZE;
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assign m_axi_awlen = 8'b00000000;
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assign m_axi_awsize = 3'(AXSIZE);
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assign m_axi_awburst = 2'b00;
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assign m_axi_awlock = 1'b0;
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assign m_axi_awcache = 4'b0;
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assign m_axi_awprot = 3'b0;
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assign m_axi_awqos = 4'b0;
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// AXI write request data channel
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assign m_axi_wvalid = mem_req_valid && mem_req_rw && !wvalid_ack;
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assign m_axi_wdata = mem_req_data;
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assign m_axi_wstrb = mem_req_byteen;
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assign m_axi_wlast = 1'b1;
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// AXI write response channel
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`UNUSED_VAR (m_axi_bid);
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`RUNTIME_ASSERT(~m_axi_bvalid || m_axi_bresp == 0, ("%t: *** AXI response error", $time));
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assign m_axi_bready = 1'b1;
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// AXI read request channel
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assign m_axi_arvalid = mem_req_valid && !mem_req_rw;
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assign m_axi_arid = mem_req_tag;
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assign m_axi_araddr = AXI_ADDR_WIDTH'(mem_req_addr) << AXSIZE;
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assign m_axi_arlen = 8'b00000000;
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assign m_axi_arsize = 3'(AXSIZE);
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assign m_axi_arburst = 2'b00;
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assign m_axi_arlock = 1'b0;
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assign m_axi_arcache = 4'b0;
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assign m_axi_arprot = 3'b0;
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assign m_axi_arqos = 4'b0;
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// AXI read response channel
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assign mem_rsp_valid = m_axi_rvalid;
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assign mem_rsp_tag = m_axi_rid;
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assign mem_rsp_data = m_axi_rdata;
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`RUNTIME_ASSERT(~m_axi_rvalid || m_axi_rresp == 0, ("%t: *** AXI response error", $time));
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`UNUSED_VAR (m_axi_rlast);
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assign m_axi_rready = mem_rsp_ready;
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for (genvar i = 0; i < NUM_BANKS; ++i) begin
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assign axi_write_ready[i] = (m_axi_awready[i] || m_axi_aw_ack[i])
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&& (m_axi_wready[i] || m_axi_w_ack[i]);
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end
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// Vortex request ack
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assign mem_req_ready = mem_req_rw ? axi_write_ready : m_axi_arready;
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if (NUM_BANKS > 1) begin
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assign mem_req_ready = mem_req_rw ? axi_write_ready[req_bank_sel] : m_axi_arready[req_bank_sel];
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end else begin
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assign mem_req_ready = mem_req_rw ? axi_write_ready[0] : m_axi_arready[0];
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end
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endmodule
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// AXI write request address channel
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for (genvar i = 0; i < NUM_BANKS; ++i) begin
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assign m_axi_awvalid[i] = mem_req_valid && mem_req_rw && (req_bank_sel == i) && ~m_axi_aw_ack[i];
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assign m_axi_awaddr[i] = (ADDR_WIDTH'(mem_req_addr) >> LOG2_NUM_BANKS) << AXSIZE;
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assign m_axi_awid[i] = mem_req_tag;
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assign m_axi_awlen[i] = 8'b00000000;
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assign m_axi_awsize[i] = 3'(AXSIZE);
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assign m_axi_awburst[i] = 2'b00;
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assign m_axi_awlock[i] = 2'b00;
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assign m_axi_awcache[i] = 4'b0000;
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assign m_axi_awprot[i] = 3'b000;
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assign m_axi_awqos[i] = 4'b0000;
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assign m_axi_awregion[i]= 4'b0000;
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end
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// AXI write request data channel
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for (genvar i = 0; i < NUM_BANKS; ++i) begin
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assign m_axi_wvalid[i] = mem_req_valid && mem_req_rw && (req_bank_sel == i) && ~m_axi_w_ack[i];
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assign m_axi_wdata[i] = mem_req_data;
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assign m_axi_wstrb[i] = mem_req_byteen;
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assign m_axi_wlast[i] = 1'b1;
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end
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// AXI write response channel (ignore)
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for (genvar i = 0; i < NUM_BANKS; ++i) begin
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`UNUSED_VAR (m_axi_bvalid[i])
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`UNUSED_VAR (m_axi_bid[i])
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`UNUSED_VAR (m_axi_bresp[i])
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assign m_axi_bready[i] = 1'b1;
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`RUNTIME_ASSERT(~m_axi_bvalid[i] || m_axi_bresp[i] == 0, ("%t: *** AXI response error", $time));
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end
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// AXI read request channel
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for (genvar i = 0; i < NUM_BANKS; ++i) begin
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assign m_axi_arvalid[i] = mem_req_valid && ~mem_req_rw && (req_bank_sel == i);
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assign m_axi_araddr[i] = (ADDR_WIDTH'(mem_req_addr) >> LOG2_NUM_BANKS) << AXSIZE;
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assign m_axi_arid[i] = mem_req_tag;
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assign m_axi_arlen[i] = 8'b00000000;
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assign m_axi_arsize[i] = 3'(AXSIZE);
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assign m_axi_arburst[i] = 2'b00;
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assign m_axi_arlock[i] = 2'b00;
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assign m_axi_arcache[i] = 4'b0000;
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assign m_axi_arprot[i] = 3'b000;
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assign m_axi_arqos[i] = 4'b0000;
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assign m_axi_arregion[i]= 4'b0000;
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end
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// AXI read response channel
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wire [NUM_BANKS-1:0] rsp_arb_valid_in;
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wire [NUM_BANKS-1:0][DATA_WIDTH+TAG_WIDTH-1:0] rsp_arb_data_in;
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wire [NUM_BANKS-1:0] rsp_arb_ready_in;
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`UNUSED_VAR (m_axi_rlast)
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for (genvar i = 0; i < NUM_BANKS; ++i) begin
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assign rsp_arb_valid_in[i] = m_axi_rvalid[i];
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assign rsp_arb_data_in[i] = {m_axi_rdata[i], m_axi_rid[i]};
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assign m_axi_rready[i] = rsp_arb_ready_in[i];
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`RUNTIME_ASSERT(~m_axi_rvalid[i] || m_axi_rlast[i] == 1, ("%t: *** AXI response error", $time));
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`RUNTIME_ASSERT(~m_axi_rvalid[i] || m_axi_rresp[i] == 0, ("%t: *** AXI response error", $time));
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end
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VX_stream_arb #(
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.NUM_INPUTS (NUM_BANKS),
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.DATAW (DATA_WIDTH + TAG_WIDTH),
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.ARBITER ("R"),
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.OUT_REG (OUT_REG_RSP)
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) rsp_arb (
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.clk (clk),
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.reset (reset),
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.valid_in (rsp_arb_valid_in),
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.data_in (rsp_arb_data_in),
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.ready_in (rsp_arb_ready_in),
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.data_out ({mem_rsp_data, mem_rsp_tag}),
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.valid_out (mem_rsp_valid),
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.ready_out (mem_rsp_ready),
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`UNUSED_PIN (sel_out)
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);
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endmodule
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`TRACING_ON
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