Vortex 2.0 changes:

+ Microarchitecture optimizations
+ 64-bit support
+ Xilinx FPGA support
+ LLVM-16 support
+ Refactoring and quality control fixes

hw/rtl/interfaces/VX_branch_ctl_if.sv

@@ -1,14 +1,24 @@
-`ifndef VX_BRANCH_RSP_IF
-`define VX_BRANCH_RSP_IF
+// Copyright © 2019-2023
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+// http://www.apache.org/licenses/LICENSE-2.0
+// 
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
 
 `include "VX_define.vh"
 
 interface VX_branch_ctl_if ();
 
-    wire                valid;    
-    wire [`NW_BITS-1:0] wid;    
-    wire                taken;
-    wire [31:0]         dest;
+    wire                    valid;    
+    wire [`NW_WIDTH-1:0]    wid;    
+    wire                    taken;
+    wire [`XLEN-1:0]        dest;
 
     modport master (
         output valid,    
@@ -25,5 +35,3 @@ interface VX_branch_ctl_if ();
     );
 
 endinterface
-
-`endif