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Vortex 2.0 changes:

Browse Source 
+ Microarchitecture optimizations
+ 64-bit support
+ Xilinx FPGA support
+ LLVM-16 support
+ Refactoring and quality control fixes
This commit is contained in:
Blaise Tine
2023-10-19 20:51:22 -07:00
parent d69a64c32c
commit d47cccc157
1300 changed files with 247321 additions and 311189 deletions
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68
hw/rtl/interfaces/VX_alu_req_if.sv
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@@ -1,68 +0,0 @@
`ifndef VX_ALU_REQ_IF
`define VX_ALU_REQ_IF
`include "VX_define.vh"
interface VX_alu_req_if ();
wire valid;
wire [`UUID_BITS-1:0] uuid;
wire [`NW_BITS-1:0] wid;
wire [`NUM_THREADS-1:0] tmask;
wire [31:0] PC;
wire [31:0] next_PC;
wire [`INST_ALU_BITS-1:0] op_type;
wire [`INST_MOD_BITS-1:0] op_mod;
wire use_PC;
wire use_imm;
wire [31:0] imm;
wire [`NT_BITS-1:0] tid;
wire [`NUM_THREADS-1:0][31:0] rs1_data;
wire [`NUM_THREADS-1:0][31:0] rs2_data;
wire [`NR_BITS-1:0] rd;
wire wb;
wire ready;
modport master (
output valid,
output uuid,
output wid,
output tmask,
output PC,
output next_PC,
output op_type,
output op_mod,
output use_PC,
output use_imm,
output imm,
output tid,
output rs1_data,
output rs2_data,
output rd,
output wb,
input ready
);
modport slave (
input valid,
input uuid,
input wid,
input tmask,
input PC,
input next_PC,
input op_type,
input op_mod,
input use_PC,
input use_imm,
input imm,
input tid,
input rs1_data,
input rs2_data,
input rd,
input wb,
output ready
);
endinterface
`endif

24
hw/rtl/interfaces/VX_branch_ctl_if.sv
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@@ -1,14 +1,24 @@
`ifndef VX_BRANCH_RSP_IF
`define VX_BRANCH_RSP_IF
// Copyright © 2019-2023
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
`include "VX_define.vh"
interface VX_branch_ctl_if ();
wire valid;
wire [`NW_BITS-1:0] wid;
wire taken;
wire [31:0] dest;
wire valid;
wire [`NW_WIDTH-1:0] wid;
wire taken;
wire [`XLEN-1:0] dest;
modport master (
output valid,
@@ -25,5 +35,3 @@ interface VX_branch_ctl_if ();
);
endinterface
`endif

26
hw/rtl/interfaces/VX_cmt_to_csr_if.sv
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@@ -1,26 +0,0 @@
`ifndef VX_CMT_TO_CSR_IF
`define VX_CMT_TO_CSR_IF
`include "VX_define.vh"
interface VX_cmt_to_csr_if ();
wire valid;
`ifdef EXT_F_ENABLE
wire [$clog2(6*`NUM_THREADS+1)-1:0] commit_size;
`else
wire [$clog2(5*`NUM_THREADS+1)-1:0] commit_size;
`endif
modport master (
output valid,
output commit_size
);
modport slave (
input valid,
input commit_size
);
endinterface
`endif

28
hw/rtl/interfaces/VX_commit_csr_if.sv Normal file
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@@ -0,0 +1,28 @@
// Copyright © 2019-2023
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
`include "VX_define.vh"
interface VX_commit_csr_if ();
wire [`PERF_CTR_BITS-1:0] instret;
modport master (
output instret
);
modport slave (
input instret
);
endinterface

61
hw/rtl/interfaces/VX_commit_if.sv
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@@ -1,47 +1,50 @@
`ifndef VX_COMMIT_IF
`define VX_COMMIT_IF
// Copyright © 2019-2023
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
`include "VX_define.vh"
interface VX_commit_if ();
interface VX_commit_if #(
parameter NUM_LANES = `NUM_THREADS,
parameter PID_WIDTH = `LOG2UP(`NUM_THREADS / NUM_LANES)
) ();
typedef struct packed {
logic [`UUID_WIDTH-1:0] uuid;
logic [`NW_WIDTH-1:0] wid;
logic [NUM_LANES-1:0] tmask;
logic [`XLEN-1:0] PC;
logic wb;
logic [`NR_BITS-1:0] rd;
logic [NUM_LANES-1:0][`XLEN-1:0] data;
logic [PID_WIDTH-1:0] pid;
logic sop;
logic eop;
} data_t;
wire valid;
wire [`UUID_BITS-1:0] uuid;
wire [`NW_BITS-1:0] wid;
wire [`NUM_THREADS-1:0] tmask;
wire [31:0] PC;
wire [`NUM_THREADS-1:0][31:0] data;
wire [`NR_BITS-1:0] rd;
wire wb;
wire eop;
wire ready;
logic valid;
data_t data;
logic ready;
modport master (
output valid,
output uuid,
output wid,
output tmask,
output PC,
output data,
output rd,
output wb,
output eop,
input ready
);
modport slave (
input valid,
input uuid,
input wid,
input tmask,
input PC,
input data,
input rd,
input wb,
input eop,
output ready
);
endinterface
`endif

31
hw/rtl/interfaces/VX_commit_sched_if.sv Normal file
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@@ -0,0 +1,31 @@
// Copyright © 2019-2023
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
`include "VX_define.vh"
interface VX_commit_sched_if ();
wire [`ISSUE_WIDTH-1:0] committed;
wire [`ISSUE_WIDTH-1:0][`NW_WIDTH-1:0] committed_wid;
modport master (
output committed,
output committed_wid
);
modport slave (
input committed,
input committed_wid
);
endinterface

56
hw/rtl/interfaces/VX_csr_req_if.sv
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@@ -1,56 +0,0 @@
`ifndef VX_CSR_REQ_IF
`define VX_CSR_REQ_IF
`include "VX_define.vh"
interface VX_csr_req_if ();
wire valid;
wire [`UUID_BITS-1:0] uuid;
wire [`NW_BITS-1:0] wid;
wire [`NUM_THREADS-1:0] tmask;
wire [31:0] PC;
wire [`INST_CSR_BITS-1:0] op_type;
wire [`CSR_ADDR_BITS-1:0] addr;
wire [31:0] rs1_data;
wire use_imm;
wire [`NRI_BITS-1:0] imm;
wire [`NR_BITS-1:0] rd;
wire wb;
wire ready;
modport master (
output valid,
output uuid,
output wid,
output tmask,
output PC,
output op_type,
output addr,
output rs1_data,
output use_imm,
output imm,
output rd,
output wb,
input ready
);
modport slave (
input valid,
input uuid,
input wid,
input tmask,
input PC,
input op_type,
input addr,
input rs1_data,
input use_imm,
input imm,
input rd,
input wb,
output ready
);
endinterface
`endif

42
hw/rtl/interfaces/VX_dcache_req_if.sv
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@@ -1,42 +0,0 @@
`ifndef VX_DCACHE_REQ_IF
`define VX_DCACHE_REQ_IF
`include "../cache/VX_cache_define.vh"
interface VX_dcache_req_if #(
parameter NUM_REQS = 1,
parameter WORD_SIZE = 1,
parameter TAG_WIDTH = 1
) ();
wire [NUM_REQS-1:0] valid;
wire [NUM_REQS-1:0] rw;
wire [NUM_REQS-1:0][WORD_SIZE-1:0] byteen;
wire [NUM_REQS-1:0][`WORD_ADDR_WIDTH-1:0] addr;
wire [NUM_REQS-1:0][`WORD_WIDTH-1:0] data;
wire [NUM_REQS-1:0][TAG_WIDTH-1:0] tag;
wire [NUM_REQS-1:0] ready;
modport master (
output valid,
output rw,
output byteen,
output addr,
output data,
output tag,
input ready
);
modport slave (
input valid,
input rw,
input byteen,
input addr,
input data,
input tag,
output ready
);
endinterface
`endif

36
hw/rtl/interfaces/VX_dcache_rsp_if.sv
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@@ -1,36 +0,0 @@
`ifndef VX_DCACHE_RSP_IF
`define VX_DCACHE_RSP_IF
`include "../cache/VX_cache_define.vh"
interface VX_dcache_rsp_if #(
parameter NUM_REQS = 1,
parameter WORD_SIZE = 1,
parameter TAG_WIDTH = 1
) ();
wire valid;
wire [NUM_REQS-1:0] tmask;
wire [NUM_REQS-1:0][`WORD_WIDTH-1:0] data;
wire [TAG_WIDTH-1:0] tag;
wire ready;
modport master (
output valid,
output tmask,
output data,
output tag,
input ready
);
modport slave (
input valid,
input tmask,
input data,
input tag,
output ready
);
endinterface
`endif

34
hw/rtl/interfaces/VX_dcr_bus_if.sv Normal file
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@@ -0,0 +1,34 @@
// Copyright © 2019-2023
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
`include "VX_define.vh"
interface VX_dcr_bus_if ();
wire write_valid;
wire [`VX_DCR_ADDR_WIDTH-1:0] write_addr;
wire [`VX_DCR_DATA_WIDTH-1:0] write_data;
modport master (
output write_valid,
output write_addr,
output write_data
);
modport slave (
input write_valid,
input write_addr,
input write_data
);
endinterface

90
hw/rtl/interfaces/VX_decode_if.sv
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@@ -1,68 +1,56 @@
`ifndef VX_DECODE_IF
`define VX_DECODE_IF
// Copyright © 2019-2023
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
`include "VX_define.vh"
interface VX_decode_if ();
wire valid;
wire [`UUID_BITS-1:0] uuid;
wire [`NW_BITS-1:0] wid;
wire [`NUM_THREADS-1:0] tmask;
wire [31:0] PC;
wire [`EX_BITS-1:0] ex_type;
wire [`INST_OP_BITS-1:0] op_type;
wire [`INST_MOD_BITS-1:0] op_mod;
wire wb;
wire use_PC;
wire use_imm;
wire [31:0] imm;
wire [`NR_BITS-1:0] rd;
wire [`NR_BITS-1:0] rs1;
wire [`NR_BITS-1:0] rs2;
wire [`NR_BITS-1:0] rs3;
wire ready;
typedef struct packed {
logic [`UUID_WIDTH-1:0] uuid;
logic [`NW_WIDTH-1:0] wid;
logic [`NUM_THREADS-1:0] tmask;
logic [`EX_BITS-1:0] ex_type;
logic [`INST_OP_BITS-1:0] op_type;
logic [`INST_MOD_BITS-1:0] op_mod;
logic wb;
logic use_PC;
logic use_imm;
logic [`XLEN-1:0] PC;
logic [`XLEN-1:0] imm;
logic [`NR_BITS-1:0] rd;
logic [`NR_BITS-1:0] rs1;
logic [`NR_BITS-1:0] rs2;
logic [`NR_BITS-1:0] rs3;
} data_t;
logic valid;
data_t data;
logic ready;
wire [`ISSUE_WIDTH-1:0] ibuf_pop;
modport master (
output valid,
output uuid,
output wid,
output tmask,
output PC,
output ex_type,
output op_type,
output op_mod,
output wb,
output use_PC,
output use_imm,
output imm,
output rd,
output rs1,
output rs2,
output rs3,
output data,
input ibuf_pop,
input ready
);
modport slave (
input valid,
input uuid,
input wid,
input tmask,
input PC,
input ex_type,
input op_type,
input op_mod,
input wb,
input use_PC,
input use_imm,
input imm,
input rd,
input rs1,
input rs2,
input rs3,
input data,
output ibuf_pop,
output ready
);
endinterface
`endif

34
hw/rtl/interfaces/VX_decode_sched_if.sv Normal file
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@@ -0,0 +1,34 @@
// Copyright © 2019-2023
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
`include "VX_define.vh"
interface VX_decode_sched_if ();
wire valid;
wire is_wstall;
wire [`NW_WIDTH-1:0] wid;
modport master (
output valid,
output is_wstall,
output wid
);
modport slave (
input valid,
input is_wstall,
input wid
);
endinterface

52
hw/rtl/interfaces/VX_dispatch_if.sv Normal file
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@@ -0,0 +1,52 @@
// Copyright © 2019-2023
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
`include "VX_define.vh"
interface VX_dispatch_if import VX_gpu_pkg::*; ();
// warning: this layout should not be modified without updating VX_dispatch_unit!!!
typedef struct packed {
logic [`UUID_WIDTH-1:0] uuid;
logic [ISSUE_WIS_W-1:0] wis;
logic [`NUM_THREADS-1:0] tmask;
logic [`INST_ALU_BITS-1:0] op_type;
logic [`INST_MOD_BITS-1:0] op_mod;
logic wb;
logic use_PC;
logic use_imm;
logic [`XLEN-1:0] PC;
logic [`XLEN-1:0] imm;
logic [`NR_BITS-1:0] rd;
logic [`NT_WIDTH-1:0] tid;
logic [`NUM_THREADS-1:0][`XLEN-1:0] rs1_data;
logic [`NUM_THREADS-1:0][`XLEN-1:0] rs2_data;
logic [`NUM_THREADS-1:0][`XLEN-1:0] rs3_data;
} data_t;
logic valid;
data_t data;
logic ready;
modport master (
output valid,
output data,
input ready
);
modport slave (
input valid,
input data,
output ready
);
endinterface

57
hw/rtl/interfaces/VX_execute_if.sv Normal file
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@@ -0,0 +1,57 @@
// Copyright © 2019-2023
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
`include "VX_define.vh"
interface VX_execute_if #(
parameter NUM_LANES = 1,
parameter PID_WIDTH = `LOG2UP(`NUM_THREADS / NUM_LANES)
) ();
typedef struct packed {
logic [`UUID_WIDTH-1:0] uuid;
logic [`NW_WIDTH-1:0] wid;
logic [NUM_LANES-1:0] tmask;
logic [`INST_ALU_BITS-1:0] op_type;
logic [`INST_MOD_BITS-1:0] op_mod;
logic wb;
logic use_PC;
logic use_imm;
logic [`XLEN-1:0] PC;
logic [`XLEN-1:0] imm;
logic [`NR_BITS-1:0] rd;
logic [`NT_WIDTH-1:0] tid;
logic [NUM_LANES-1:0][`XLEN-1:0] rs1_data;
logic [NUM_LANES-1:0][`XLEN-1:0] rs2_data;
logic [NUM_LANES-1:0][`XLEN-1:0] rs3_data;
logic [PID_WIDTH-1:0] pid;
logic sop;
logic eop;
} data_t;
logic valid;
data_t data;
logic ready;
modport master (
output valid,
output data,
input ready
);
modport slave (
input valid,
input data,
output ready
);
endinterface

46
hw/rtl/interfaces/VX_fetch_if.sv Normal file
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@@ -0,0 +1,46 @@
// Copyright © 2019-2023
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
`include "VX_define.vh"
interface VX_fetch_if ();
typedef struct packed {
logic [`UUID_WIDTH-1:0] uuid;
logic [`NW_WIDTH-1:0] wid;
logic [`NUM_THREADS-1:0] tmask;
logic [`XLEN-1:0] PC;
logic [31:0] instr;
} data_t;
logic valid;
data_t data;
logic ready;
logic [`ISSUE_WIDTH-1:0] ibuf_pop;
modport master (
output valid,
output data,
input ibuf_pop,
input ready
);
modport slave (
input valid,
input data,
output ibuf_pop,
output ready
);
endinterface

20
hw/rtl/interfaces/VX_fetch_to_csr_if.sv
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@@ -1,20 +0,0 @@
`ifndef VX_FETCH_TO_CSR_IF
`define VX_FETCH_TO_CSR_IF
`include "VX_define.vh"
interface VX_fetch_to_csr_if ();
wire [`NUM_WARPS-1:0][`NUM_THREADS-1:0] thread_masks;
modport master (
output thread_masks
);
modport slave (
input thread_masks
);
endinterface
`endif

56
hw/rtl/interfaces/VX_fpu_req_if.sv
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@@ -1,56 +0,0 @@
`ifndef VX_FPU_REQ_IF
`define VX_FPU_REQ_IF
`include "VX_define.vh"
interface VX_fpu_req_if ();
wire valid;
wire [`UUID_BITS-1:0] uuid;
wire [`NW_BITS-1:0] wid;
wire [`NUM_THREADS-1:0] tmask;
wire [31:0] PC;
wire [`INST_FPU_BITS-1:0] op_type;
wire [`INST_MOD_BITS-1:0] op_mod;
wire [`NUM_THREADS-1:0][31:0] rs1_data;
wire [`NUM_THREADS-1:0][31:0] rs2_data;
wire [`NUM_THREADS-1:0][31:0] rs3_data;
wire [`NR_BITS-1:0] rd;
wire wb;
wire ready;
modport master (
output valid,
output uuid,
output wid,
output tmask,
output PC,
output op_type,
output op_mod,
output rs1_data,
output rs2_data,
output rs3_data,
output rd,
output wb,
input ready
);
modport slave (
input valid,
input uuid,
input wid,
input tmask,
input PC,
input op_type,
input op_mod,
input rs1_data,
input rs2_data,
input rs3_data,
input rd,
input wb,
output ready
);
endinterface
`endif

33
hw/rtl/interfaces/VX_fpu_to_csr_if.sv
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@@ -1,33 +0,0 @@
`ifndef VX_FPU_TO_CSR_IF
`define VX_FPU_TO_CSR_IF
`include "VX_define.vh"
interface VX_fpu_to_csr_if ();
wire write_enable;
wire [`NW_BITS-1:0] write_wid;
fpu_types::fflags_t write_fflags;
wire [`NW_BITS-1:0] read_wid;
wire [`INST_FRM_BITS-1:0] read_frm;
modport master (
output write_enable,
output write_wid,
output write_fflags,
output read_wid,
input read_frm
);
modport slave (
input write_enable,
input write_wid,
input write_fflags,
input read_wid,
output read_frm
);
endinterface
`endif

29
hw/rtl/interfaces/VX_gpr_req_if.sv
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@@ -1,29 +0,0 @@
`ifndef VX_GPR_REQ_IF
`define VX_GPR_REQ_IF
`include "VX_define.vh"
interface VX_gpr_req_if ();
wire [`NW_BITS-1:0] wid;
wire [`NR_BITS-1:0] rs1;
wire [`NR_BITS-1:0] rs2;
wire [`NR_BITS-1:0] rs3;
modport master (
output wid,
output rs1,
output rs2,
output rs3
);
modport slave (
input wid,
input rs1,
input rs2,
input rs3
);
endinterface
`endif

26
hw/rtl/interfaces/VX_gpr_rsp_if.sv
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@@ -1,26 +0,0 @@
`ifndef VX_GPR_RSP_IF
`define VX_GPR_RSP_IF
`include "VX_define.vh"
interface VX_gpr_rsp_if ();
wire [`NUM_THREADS-1:0][31:0] rs1_data;
wire [`NUM_THREADS-1:0][31:0] rs2_data;
wire [`NUM_THREADS-1:0][31:0] rs3_data;
modport master (
output rs1_data,
output rs2_data,
output rs3_data
);
modport slave (
input rs1_data,
input rs2_data,
input rs3_data
);
endinterface
`endif

62
hw/rtl/interfaces/VX_gpu_req_if.sv
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@@ -1,62 +0,0 @@
`ifndef VX_GPU_REQ_IF
`define VX_GPU_REQ_IF
`include "VX_define.vh"
interface VX_gpu_req_if();
wire valid;
wire [`UUID_BITS-1:0] uuid;
wire [`NW_BITS-1:0] wid;
wire [`NUM_THREADS-1:0] tmask;
wire [31:0] PC;
wire [31:0] next_PC;
wire [`INST_GPU_BITS-1:0] op_type;
wire [`INST_MOD_BITS-1:0] op_mod;
wire [`NT_BITS-1:0] tid;
wire [`NUM_THREADS-1:0][31:0] rs1_data;
wire [`NUM_THREADS-1:0][31:0] rs2_data;
wire [`NUM_THREADS-1:0][31:0] rs3_data;
wire [`NR_BITS-1:0] rd;
wire wb;
wire ready;
modport master (
output valid,
output uuid,
output wid,
output tmask,
output PC,
output next_PC,
output op_type,
output op_mod,
output tid,
output rs1_data,
output rs2_data,
output rs3_data,
output rd,
output wb,
input ready
);
modport slave (
input valid,
input uuid,
input wid,
input tmask,
input PC,
input next_PC,
input op_type,
input op_mod,
input tid,
input rs1_data,
input rs2_data,
input rs3_data,
input rd,
input wb,
output ready
);
endinterface
`endif

105
hw/rtl/interfaces/VX_ibuffer_if.sv
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@@ -1,85 +1,52 @@
`ifndef VX_IBUFFER_IF
`define VX_IBUFFER_IF
// Copyright © 2019-2023
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
`include "VX_define.vh"
interface VX_ibuffer_if ();
interface VX_ibuffer_if import VX_gpu_pkg::*; ();
wire valid;
wire [`UUID_BITS-1:0] uuid;
wire [`NW_BITS-1:0] wid;
wire [`NUM_THREADS-1:0] tmask;
wire [31:0] PC;
wire [`EX_BITS-1:0] ex_type;
wire [`INST_OP_BITS-1:0] op_type;
wire [`INST_MOD_BITS-1:0] op_mod;
wire wb;
wire use_PC;
wire use_imm;
wire [31:0] imm;
wire [`NR_BITS-1:0] rd;
wire [`NR_BITS-1:0] rs1;
wire [`NR_BITS-1:0] rs2;
wire [`NR_BITS-1:0] rs3;
wire [`NR_BITS-1:0] rd_n;
wire [`NR_BITS-1:0] rs1_n;
wire [`NR_BITS-1:0] rs2_n;
wire [`NR_BITS-1:0] rs3_n;
wire [`NW_BITS-1:0] wid_n;
typedef struct packed {
logic [`UUID_WIDTH-1:0] uuid;
logic [ISSUE_WIS_W-1:0] wis;
logic [`NUM_THREADS-1:0] tmask;
logic [`EX_BITS-1:0] ex_type;
logic [`INST_OP_BITS-1:0] op_type;
logic [`INST_MOD_BITS-1:0] op_mod;
logic wb;
logic use_PC;
logic use_imm;
logic [`XLEN-1:0] PC;
logic [`XLEN-1:0] imm;
logic [`NR_BITS-1:0] rd;
logic [`NR_BITS-1:0] rs1;
logic [`NR_BITS-1:0] rs2;
logic [`NR_BITS-1:0] rs3;
} data_t;
wire ready;
logic valid;
data_t data;
logic ready;
modport master (
output valid,
output uuid,
output wid,
output tmask,
output PC,
output ex_type,
output op_type,
output op_mod,
output wb,
output use_PC,
output use_imm,
output imm,
output rd,
output rs1,
output rs2,
output rs3,
output rd_n,
output rs1_n,
output rs2_n,
output rs3_n,
output wid_n,
output data,
input ready
);
modport slave (
input valid,
input uuid,
input wid,
input tmask,
input PC,
input ex_type,
input op_type,
input op_mod,
input wb,
input use_PC,
input use_imm,
input imm,
input rd,
input rs1,
input rs2,
input rs3,
input rd_n,
input rs1_n,
input rs2_n,
input rs3_n,
input wid_n,
input data,
output ready
);
endinterface
`endif
endinterface

32
hw/rtl/interfaces/VX_icache_req_if.sv
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@@ -1,32 +0,0 @@
`ifndef VX_ICACHE_CORE_REQ_IF
`define VX_ICACHE_CORE_REQ_IF
`include "../cache/VX_cache_define.vh"
interface VX_icache_req_if #(
parameter WORD_SIZE = 1,
parameter TAG_WIDTH = 1
) ();
wire valid;
wire [`WORD_ADDR_WIDTH-1:0] addr;
wire [TAG_WIDTH-1:0] tag;
wire ready;
modport master (
output valid,
output addr,
output tag,
input ready
);
modport slave (
input valid,
input addr,
input tag,
output ready
);
endinterface
`endif

32
hw/rtl/interfaces/VX_icache_rsp_if.sv
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@@ -1,32 +0,0 @@
`ifndef VX_ICACHE_CORE_RSP_IF
`define VX_ICACHE_CORE_RSP_IF
`include "../cache/VX_cache_define.vh"
interface VX_icache_rsp_if #(
parameter WORD_SIZE = 1,
parameter TAG_WIDTH = 1
) ();
wire valid;
wire [`WORD_WIDTH-1:0] data;
wire [TAG_WIDTH-1:0] tag;
wire ready;
modport master (
output valid,
output data,
output tag,
input ready
);
modport slave (
input valid,
input data,
input tag,
output ready
);
endinterface
`endif

35
hw/rtl/interfaces/VX_ifetch_req_if.sv
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@@ -1,35 +0,0 @@
`ifndef VX_IFETCH_REQ_IF
`define VX_IFETCH_REQ_IF
`include "VX_define.vh"
interface VX_ifetch_req_if ();
wire valid;
wire [`UUID_BITS-1:0] uuid;
wire [`NUM_THREADS-1:0] tmask;
wire [`NW_BITS-1:0] wid;
wire [31:0] PC;
wire ready;
modport master (
output valid,
output uuid,
output tmask,
output wid,
output PC,
input ready
);
modport slave (
input valid,
input uuid,
input tmask,
input wid,
input PC,
output ready
);
endinterface
`endif

38
hw/rtl/interfaces/VX_ifetch_rsp_if.sv
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@@ -1,38 +0,0 @@
`ifndef VX_IFETCH_RSP_IF
`define VX_IFETCH_RSP_IF
`include "VX_define.vh"
interface VX_ifetch_rsp_if ();
wire valid;
wire [`UUID_BITS-1:0] uuid;
wire [`NUM_THREADS-1:0] tmask;
wire [`NW_BITS-1:0] wid;
wire [31:0] PC;
wire [31:0] data;
wire ready;
modport master (
output valid,
output uuid,
output tmask,
output wid,
output PC,
output data,
input ready
);
modport slave (
input valid,
input uuid,
input tmask,
input wid,
input PC,
input data,
output ready
);
endinterface
`endif

23
hw/rtl/interfaces/VX_join_if.sv
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@@ -1,23 +0,0 @@
`ifndef VX_JOIN_IF
`define VX_JOIN_IF
`include "VX_define.vh"
interface VX_join_if ();
wire valid;
wire [`NW_BITS-1:0] wid;
modport master (
output valid,
output wid
);
modport slave (
input valid,
input wid
);
endinterface
`endif

59
hw/rtl/interfaces/VX_lsu_req_if.sv
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@@ -1,59 +0,0 @@
`ifndef VX_LSU_REQ_IF
`define VX_LSU_REQ_IF
`include "VX_define.vh"
interface VX_lsu_req_if ();
wire valid;
wire [`UUID_BITS-1:0] uuid;
wire [`NW_BITS-1:0] wid;
wire [`NUM_THREADS-1:0] tmask;
wire [31:0] PC;
wire [`INST_LSU_BITS-1:0] op_type;
wire is_fence;
wire [`NUM_THREADS-1:0][31:0] store_data;
wire [`NUM_THREADS-1:0][31:0] base_addr;
wire [31:0] offset;
wire [`NR_BITS-1:0] rd;
wire wb;
wire ready;
wire is_prefetch;
modport master (
output valid,
output uuid,
output wid,
output tmask,
output PC,
output op_type,
output is_fence,
output store_data,
output base_addr,
output offset,
output rd,
output wb,
output is_prefetch,
input ready
);
modport slave (
input valid,
input uuid,
input wid,
input tmask,
input PC,
input op_type,
input is_fence,
input store_data,
input base_addr,
input offset,
input rd,
input wb,
input is_prefetch,
output ready
);
endinterface
`endif

43
hw/rtl/interfaces/VX_mem_req_if.sv
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@@ -1,43 +0,0 @@
`ifndef VX_MEM_REQ_IF
`define VX_MEM_REQ_IF
`include "../cache/VX_cache_define.vh"
interface VX_mem_req_if #(
parameter DATA_WIDTH = 1,
parameter ADDR_WIDTH = 1,
parameter TAG_WIDTH = 1,
parameter DATA_SIZE = DATA_WIDTH / 8
) ();
wire valid;
wire rw;
wire [DATA_SIZE-1:0] byteen;
wire [ADDR_WIDTH-1:0] addr;
wire [DATA_WIDTH-1:0] data;
wire [TAG_WIDTH-1:0] tag;
wire ready;
modport master (
output valid,
output rw,
output byteen,
output addr,
output data,
output tag,
input ready
);
modport slave (
input valid,
input rw,
input byteen,
input addr,
input data,
input tag,
output ready
);
endinterface
`endif

32
hw/rtl/interfaces/VX_mem_rsp_if.sv
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@@ -1,32 +0,0 @@
`ifndef VX_MEM_RSP_IF
`define VX_MEM_RSP_IF
`include "../cache/VX_cache_define.vh"
interface VX_mem_rsp_if #(
parameter DATA_WIDTH = 1,
parameter TAG_WIDTH = 1
) ();
wire valid;
wire [DATA_WIDTH-1:0] data;
wire [TAG_WIDTH-1:0] tag;
wire ready;
modport master (
output valid,
output data,
output tag,
input ready
);
modport slave (
input valid,
input data,
input tag,
output ready
);
endinterface
`endif

52
hw/rtl/interfaces/VX_operands_if.sv Normal file
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@@ -0,0 +1,52 @@
// Copyright © 2019-2023
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
`include "VX_define.vh"
interface VX_operands_if import VX_gpu_pkg::*; ();
typedef struct packed {
logic [`UUID_WIDTH-1:0] uuid;
logic [ISSUE_WIS_W-1:0] wis;
logic [`NUM_THREADS-1:0] tmask;
logic [`XLEN-1:0] PC;
logic [`EX_BITS-1:0] ex_type;
logic [`INST_OP_BITS-1:0] op_type;
logic [`INST_MOD_BITS-1:0] op_mod;
logic wb;
logic use_PC;
logic use_imm;
logic [`XLEN-1:0] imm;
logic [`NR_BITS-1:0] rd;
logic [`NUM_THREADS-1:0][`XLEN-1:0] rs1_data;
logic [`NUM_THREADS-1:0][`XLEN-1:0] rs2_data;
logic [`NUM_THREADS-1:0][`XLEN-1:0] rs3_data;
} data_t;
logic valid;
data_t data;
logic ready;
modport master (
output valid,
output data,
input ready
);
modport slave (
input valid,
input data,
output ready
);
endinterface

41
hw/rtl/interfaces/VX_perf_cache_if.sv
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@@ -1,41 +0,0 @@
`ifndef VX_PERF_CACHE_IF
`define VX_PERF_CACHE_IF
`include "VX_define.vh"
interface VX_perf_cache_if ();
wire [`PERF_CTR_BITS-1:0] reads;
wire [`PERF_CTR_BITS-1:0] writes;
wire [`PERF_CTR_BITS-1:0] read_misses;
wire [`PERF_CTR_BITS-1:0] write_misses;
wire [`PERF_CTR_BITS-1:0] bank_stalls;
wire [`PERF_CTR_BITS-1:0] mshr_stalls;
wire [`PERF_CTR_BITS-1:0] mem_stalls;
wire [`PERF_CTR_BITS-1:0] crsp_stalls;
modport master (
output reads,
output writes,
output read_misses,
output write_misses,
output bank_stalls,
output mshr_stalls,
output mem_stalls,
output crsp_stalls
);
modport slave (
input reads,
input writes,
input read_misses,
input write_misses,
input bank_stalls,
input mshr_stalls,
input mem_stalls,
input crsp_stalls
);
endinterface
`endif

59
hw/rtl/interfaces/VX_perf_memsys_if.sv
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@@ -1,59 +0,0 @@
`ifndef VX_PERF_MEMSYS_IF
`define VX_PERF_MEMSYS_IF
`include "VX_define.vh"
interface VX_perf_memsys_if ();
wire [`PERF_CTR_BITS-1:0] icache_reads;
wire [`PERF_CTR_BITS-1:0] icache_read_misses;
wire [`PERF_CTR_BITS-1:0] dcache_reads;
wire [`PERF_CTR_BITS-1:0] dcache_writes;
wire [`PERF_CTR_BITS-1:0] dcache_read_misses;
wire [`PERF_CTR_BITS-1:0] dcache_write_misses;
wire [`PERF_CTR_BITS-1:0] dcache_bank_stalls;
wire [`PERF_CTR_BITS-1:0] dcache_mshr_stalls;
wire [`PERF_CTR_BITS-1:0] smem_reads;
wire [`PERF_CTR_BITS-1:0] smem_writes;
wire [`PERF_CTR_BITS-1:0] smem_bank_stalls;
wire [`PERF_CTR_BITS-1:0] mem_reads;
wire [`PERF_CTR_BITS-1:0] mem_writes;
wire [`PERF_CTR_BITS-1:0] mem_latency;
modport master (
output icache_reads,
output icache_read_misses,
output dcache_reads,
output dcache_writes,
output dcache_read_misses,
output dcache_write_misses,
output dcache_bank_stalls,
output dcache_mshr_stalls,
output smem_reads,
output smem_writes,
output smem_bank_stalls,
output mem_reads,
output mem_writes,
output mem_latency
);
modport slave (
input icache_reads,
input icache_read_misses,
input dcache_reads,
input dcache_writes,
input dcache_read_misses,
input dcache_write_misses,
input dcache_bank_stalls,
input dcache_mshr_stalls,
input smem_reads,
input smem_writes,
input smem_bank_stalls,
input mem_reads,
input mem_writes,
input mem_latency
);
endinterface
`endif

56
hw/rtl/interfaces/VX_perf_pipeline_if.sv
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@@ -1,56 +0,0 @@
`ifndef VX_PERF_PIPELINE_IF
`define VX_PERF_PIPELINE_IF
`include "VX_define.vh"
interface VX_perf_pipeline_if ();
wire [`PERF_CTR_BITS-1:0] loads;
wire [`PERF_CTR_BITS-1:0] stores;
wire [`PERF_CTR_BITS-1:0] branches;
wire [`PERF_CTR_BITS-1:0] ibf_stalls;
wire [`PERF_CTR_BITS-1:0] scb_stalls;
wire [`PERF_CTR_BITS-1:0] lsu_stalls;
wire [`PERF_CTR_BITS-1:0] csr_stalls;
wire [`PERF_CTR_BITS-1:0] alu_stalls;
`ifdef EXT_F_ENABLE
wire [`PERF_CTR_BITS-1:0] fpu_stalls;
`endif
wire [`PERF_CTR_BITS-1:0] gpu_stalls;
modport decode (
output loads,
output stores,
output branches
);
modport issue (
output ibf_stalls,
output scb_stalls,
output lsu_stalls,
output csr_stalls,
output alu_stalls,
`ifdef EXT_F_ENABLE
output fpu_stalls,
`endif
output gpu_stalls
);
modport slave (
input loads,
input stores,
input branches,
input ibf_stalls,
input scb_stalls,
input lsu_stalls,
input csr_stalls,
input alu_stalls,
`ifdef EXT_F_ENABLE
input fpu_stalls,
`endif
input gpu_stalls
);
endinterface
`endif

23
hw/rtl/interfaces/VX_perf_tex_if.sv
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@@ -1,23 +0,0 @@
`ifndef VX_PERF_TEX_IF
`define VX_PERF_TEX_IF
`include "VX_define.vh"
interface VX_perf_tex_if ();
wire [`PERF_CTR_BITS-1:0] mem_reads;
wire [`PERF_CTR_BITS-1:0] mem_latency;
modport master (
output mem_reads,
output mem_latency
);
modport slave (
input mem_reads,
input mem_latency
);
endinterface
`endif

44
hw/rtl/interfaces/VX_pipeline_perf_if.sv Normal file
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@@ -0,0 +1,44 @@
// Copyright © 2019-2023
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
`include "VX_define.vh"
interface VX_pipeline_perf_if ();
wire [`PERF_CTR_BITS-1:0] ibf_stalls;
wire [`PERF_CTR_BITS-1:0] scb_stalls;
wire [`PERF_CTR_BITS-1:0] dsp_stalls [`NUM_EX_UNITS];
wire [`PERF_CTR_BITS-1:0] ifetches;
wire [`PERF_CTR_BITS-1:0] loads;
wire [`PERF_CTR_BITS-1:0] stores;
wire [`PERF_CTR_BITS-1:0] ifetch_latency;
wire [`PERF_CTR_BITS-1:0] load_latency;
modport issue (
output ibf_stalls,
output scb_stalls,
output dsp_stalls
);
modport slave (
input ibf_stalls,
input scb_stalls,
input dsp_stalls,
input ifetches,
input loads,
input stores,
input ifetch_latency,
input load_latency
);
endinterface

46
hw/rtl/interfaces/VX_sched_csr_if.sv Normal file
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@@ -0,0 +1,46 @@
// Copyright © 2019-2023
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
`include "VX_define.vh"
interface VX_sched_csr_if ();
wire [`PERF_CTR_BITS-1:0] cycles;
wire [`NUM_WARPS-1:0] active_warps;
wire [`NUM_WARPS-1:0][`NUM_THREADS-1:0] thread_masks;
wire alm_empty;
wire [`NW_WIDTH-1:0] alm_empty_wid;
wire unlock_warp;
wire [`NW_WIDTH-1:0] unlock_wid;
modport master (
output cycles,
output active_warps,
output thread_masks,
input alm_empty_wid,
output alm_empty,
input unlock_wid,
input unlock_warp
);
modport slave (
input cycles,
input active_warps,
input thread_masks,
output alm_empty_wid,
input alm_empty,
output unlock_wid,
output unlock_warp
);
endinterface

41
hw/rtl/interfaces/VX_schedule_if.sv Normal file
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@@ -0,0 +1,41 @@
// Copyright © 2019-2023
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
`include "VX_define.vh"
interface VX_schedule_if ();
typedef struct packed {
logic [`UUID_WIDTH-1:0] uuid;
logic [`NW_WIDTH-1:0] wid;
logic [`NUM_THREADS-1:0] tmask;
logic [`XLEN-1:0] PC;
} data_t;
logic valid;
data_t data;
logic ready;
modport master (
output valid,
output data,
input ready
);
modport slave (
input valid,
input data,
output ready
);
endinterface

73
hw/rtl/interfaces/VX_sfu_csr_if.sv Normal file
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@@ -0,0 +1,73 @@
// Copyright © 2019-2023
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
`include "VX_define.vh"
interface VX_sfu_csr_if #(
parameter NUM_LANES = `NUM_SFU_LANES,
parameter PID_WIDTH = `LOG2UP(`NUM_THREADS / NUM_LANES)
) ();
wire read_enable;
wire [`UUID_WIDTH-1:0] read_uuid;
wire [`NW_WIDTH-1:0] read_wid;
wire [NUM_LANES-1:0] read_tmask;
wire [PID_WIDTH-1:0] read_pid;
wire [`VX_CSR_ADDR_BITS-1:0] read_addr;
wire [NUM_LANES-1:0][31:0] read_data;
wire write_enable;
wire [`UUID_WIDTH-1:0] write_uuid;
wire [`NW_WIDTH-1:0] write_wid;
wire [NUM_LANES-1:0] write_tmask;
wire [PID_WIDTH-1:0] write_pid;
wire [`VX_CSR_ADDR_BITS-1:0] write_addr;
wire [NUM_LANES-1:0][31:0] write_data;
modport master (
output read_enable,
output read_uuid,
output read_wid,
output read_tmask,
output read_pid,
output read_addr,
input read_data,
output write_enable,
output write_uuid,
output write_wid,
output write_tmask,
output write_pid,
output write_addr,
output write_data
);
modport slave (
input read_enable,
input read_uuid,
input read_wid,
input read_tmask,
input read_pid,
input read_addr,
output read_data,
input write_enable,
input write_uuid,
input write_wid,
input write_tmask,
input write_pid,
input write_addr,
input write_data
);
endinterface

27
hw/rtl/interfaces/VX_sfu_perf_if.sv Normal file
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@@ -0,0 +1,27 @@
// Copyright © 2019-2023
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
`include "VX_define.vh"
interface VX_sfu_perf_if ();
wire [`PERF_CTR_BITS-1:0] wctl_stalls;
modport master (
output wctl_stalls
);
modport slave (
input wctl_stalls
);
endinterface

29
hw/rtl/interfaces/VX_tex_csr_if.sv
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@@ -1,29 +0,0 @@
`ifndef VX_TEX_CSR_IF
`define VX_TEX_CSR_IF
`include "VX_define.vh"
interface VX_tex_csr_if ();
wire write_enable;
wire [`CSR_ADDR_BITS-1:0] write_addr;
wire [31:0] write_data;
wire [`UUID_BITS-1:0] write_uuid;
modport master (
output write_enable,
output write_addr,
output write_data,
output write_uuid
);
modport slave (
input write_enable,
input write_addr,
input write_data,
input write_uuid
);
endinterface
`endif

54
hw/rtl/interfaces/VX_tex_req_if.sv
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@@ -1,54 +0,0 @@
`ifndef VX_TEX_REQ_IF
`define VX_TEX_REQ_IF
`include "VX_define.vh"
interface VX_tex_req_if ();
wire valid;
wire [`UUID_BITS-1:0] uuid;
wire [`NW_BITS-1:0] wid;
wire [`NUM_THREADS-1:0] tmask;
wire [31:0] PC;
wire [`NR_BITS-1:0] rd;
wire wb;
wire [`NTEX_BITS-1:0] unit;
wire [1:0][`NUM_THREADS-1:0][31:0] coords;
wire [`NUM_THREADS-1:0][31:0] lod;
wire ready;
modport master (
output valid,
output uuid,
output wid,
output tmask,
output PC,
output rd,
output wb,
output unit,
output coords,
output lod,
input ready
);
modport slave (
input valid,
input uuid,
input wid,
input tmask,
input PC,
input rd,
input wb,
input unit,
input coords,
input lod,
output ready
);
endinterface
`endif

46
hw/rtl/interfaces/VX_tex_rsp_if.sv
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@@ -1,46 +0,0 @@
`ifndef VX_TEX_RSP_IF
`define VX_TEX_RSP_IF
`include "VX_define.vh"
interface VX_tex_rsp_if ();
wire valid;
wire [`UUID_BITS-1:0] uuid;
wire [`NW_BITS-1:0] wid;
wire [`NUM_THREADS-1:0] tmask;
wire [31:0] PC;
wire [`NR_BITS-1:0] rd;
wire wb;
wire [`NUM_THREADS-1:0][31:0] data;
wire ready;
modport master (
output valid,
output uuid,
output wid,
output tmask,
output PC,
output rd,
output wb,
output data,
input ready
);
modport slave (
input valid,
input uuid,
input wid,
input tmask,
input PC,
input rd,
input wb,
input data,
output ready
);
endinterface
`endif

45
hw/rtl/interfaces/VX_warp_ctl_if.sv
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@@ -1,35 +1,46 @@
`ifndef VX_WARP_CTL_IF
`define VX_WARP_CTL_IF
// Copyright © 2019-2023
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
`include "VX_define.vh"
interface VX_warp_ctl_if ();
interface VX_warp_ctl_if import VX_gpu_pkg::*; ();
wire valid;
wire [`NW_BITS-1:0] wid;
gpu_types::gpu_tmc_t tmc;
gpu_types::gpu_wspawn_t wspawn;
gpu_types::gpu_barrier_t barrier;
gpu_types::gpu_split_t split;
wire valid;
wire [`NW_WIDTH-1:0] wid;
tmc_t tmc;
wspawn_t wspawn;
split_t split;
join_t sjoin;
barrier_t barrier;
modport master (
output valid,
output wid,
output tmc,
output wspawn,
output barrier,
output split
output tmc,
output split,
output sjoin,
output barrier
);
modport slave (
input valid,
input wid,
input tmc,
input wspawn,
input barrier,
input split
input tmc,
input split,
input sjoin,
input barrier
);
endinterface
`endif

60
hw/rtl/interfaces/VX_writeback_if.sv
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@@ -1,44 +1,42 @@
`ifndef VX_WRITEBACK_IF
`define VX_WRITEBACK_IF
// Copyright © 2019-2023
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
`include "VX_define.vh"
interface VX_writeback_if ();
interface VX_writeback_if import VX_gpu_pkg::*; ();
wire valid;
wire [`UUID_BITS-1:0] uuid;
wire [`NUM_THREADS-1:0] tmask;
wire [`NW_BITS-1:0] wid;
wire [31:0] PC;
wire [`NR_BITS-1:0] rd;
wire [`NUM_THREADS-1:0][31:0] data;
wire eop;
wire ready;
typedef struct packed {
logic [`UUID_WIDTH-1:0] uuid;
logic [ISSUE_WIS_W-1:0] wis;
logic [`NUM_THREADS-1:0] tmask;
logic [`XLEN-1:0] PC;
logic [`NR_BITS-1:0] rd;
logic [`NUM_THREADS-1:0][`XLEN-1:0] data;
logic sop;
logic eop;
} data_t;
logic valid;
data_t data;
modport master (
output valid,
output uuid,
output tmask,
output wid,
output PC,
output rd,
output data,
output eop,
input ready
output data
);
modport slave (
input valid,
input uuid,
input tmask,
input wid,
input PC,
input rd,
input data,
input eop,
output ready
input valid,
input data
);
endinterface
`endif

26
hw/rtl/interfaces/VX_wstall_if.sv
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@@ -1,26 +0,0 @@
`ifndef VX_WSTALL_IF
`define VX_WSTALL_IF
`include "VX_define.vh"
interface VX_wstall_if();
wire valid;
wire [`NW_BITS-1:0] wid;
wire stalled;
modport master (
output valid,
output wid,
output stalled
);
modport slave (
input valid,
input wid,
input stalled
);
endinterface
`endif