FPU float<->int conversion optimization
This commit is contained in:
Blaise Tine
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// -------------------------------------------------------------------------
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// High Level Design Compiler for Intel(R) FPGAs Version 17.1 (Release Build #273)
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// Quartus Prime development tool and MATLAB/Simulink Interface
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//
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// Legal Notice: Copyright 2017 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly
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// subject to the terms and conditions of the Intel FPGA Software License
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// Agreement, Intel MegaCore Function License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for
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// the sole purpose of programming logic devices manufactured by Intel
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// and sold by Intel or its authorized distributors. Please refer to the
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// applicable agreement for further details.
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// ---------------------------------------------------------------------------
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// SystemVerilog created from acl_ftoi
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// SystemVerilog created on Sun Dec 27 09:47:21 2020
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(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
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module acl_ftoi (
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input wire [31:0] a,
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input wire [0:0] en,
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output wire [31:0] q,
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input wire clk,
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input wire areset
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);
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wire [0:0] GND_q;
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wire [7:0] cstAllOWE_uid6_fpToFxPTest_q;
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wire [22:0] cstZeroWF_uid7_fpToFxPTest_q;
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wire [7:0] cstAllZWE_uid8_fpToFxPTest_q;
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wire [7:0] exp_x_uid9_fpToFxPTest_b;
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wire [22:0] frac_x_uid10_fpToFxPTest_b;
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wire [0:0] excZ_x_uid11_fpToFxPTest_qi;
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reg [0:0] excZ_x_uid11_fpToFxPTest_q;
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wire [0:0] expXIsMax_uid12_fpToFxPTest_qi;
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reg [0:0] expXIsMax_uid12_fpToFxPTest_q;
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wire [0:0] fracXIsZero_uid13_fpToFxPTest_qi;
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reg [0:0] fracXIsZero_uid13_fpToFxPTest_q;
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wire [0:0] fracXIsNotZero_uid14_fpToFxPTest_q;
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wire [0:0] excI_x_uid15_fpToFxPTest_q;
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wire [0:0] excN_x_uid16_fpToFxPTest_q;
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wire [0:0] invExcXZ_uid22_fpToFxPTest_q;
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wire [23:0] oFracX_uid23_fpToFxPTest_q;
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wire [0:0] signX_uid25_fpToFxPTest_b;
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wire [8:0] ovfExpVal_uid26_fpToFxPTest_q;
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wire [10:0] ovfExpRange_uid27_fpToFxPTest_a;
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wire [10:0] ovfExpRange_uid27_fpToFxPTest_b;
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logic [10:0] ovfExpRange_uid27_fpToFxPTest_o;
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wire [0:0] ovfExpRange_uid27_fpToFxPTest_n;
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wire [7:0] udfExpVal_uid28_fpToFxPTest_q;
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wire [10:0] udf_uid29_fpToFxPTest_a;
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wire [10:0] udf_uid29_fpToFxPTest_b;
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logic [10:0] udf_uid29_fpToFxPTest_o;
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wire [0:0] udf_uid29_fpToFxPTest_n;
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wire [8:0] ovfExpVal_uid30_fpToFxPTest_q;
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wire [10:0] shiftValE_uid31_fpToFxPTest_a;
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wire [10:0] shiftValE_uid31_fpToFxPTest_b;
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logic [10:0] shiftValE_uid31_fpToFxPTest_o;
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wire [9:0] shiftValE_uid31_fpToFxPTest_q;
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wire [5:0] shiftValRaw_uid32_fpToFxPTest_in;
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wire [5:0] shiftValRaw_uid32_fpToFxPTest_b;
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wire [5:0] maxShiftCst_uid33_fpToFxPTest_q;
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wire [11:0] shiftOutOfRange_uid34_fpToFxPTest_a;
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wire [11:0] shiftOutOfRange_uid34_fpToFxPTest_b;
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logic [11:0] shiftOutOfRange_uid34_fpToFxPTest_o;
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wire [0:0] shiftOutOfRange_uid34_fpToFxPTest_n;
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wire [0:0] shiftVal_uid35_fpToFxPTest_s;
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reg [5:0] shiftVal_uid35_fpToFxPTest_q;
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wire [31:0] shifterIn_uid37_fpToFxPTest_q;
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wire [31:0] maxPosValueS_uid39_fpToFxPTest_q;
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wire [31:0] maxNegValueS_uid40_fpToFxPTest_q;
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wire [32:0] zRightShiferNoStickyOut_uid41_fpToFxPTest_q;
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wire [32:0] xXorSignE_uid42_fpToFxPTest_b;
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wire [32:0] xXorSignE_uid42_fpToFxPTest_q;
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wire [2:0] d0_uid43_fpToFxPTest_q;
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wire [33:0] sPostRndFull_uid44_fpToFxPTest_a;
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wire [33:0] sPostRndFull_uid44_fpToFxPTest_b;
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logic [33:0] sPostRndFull_uid44_fpToFxPTest_o;
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wire [33:0] sPostRndFull_uid44_fpToFxPTest_q;
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wire [32:0] sPostRnd_uid45_fpToFxPTest_in;
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wire [31:0] sPostRnd_uid45_fpToFxPTest_b;
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wire [34:0] sPostRnd_uid46_fpToFxPTest_in;
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wire [33:0] sPostRnd_uid46_fpToFxPTest_b;
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wire [35:0] rndOvfPos_uid47_fpToFxPTest_a;
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wire [35:0] rndOvfPos_uid47_fpToFxPTest_b;
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logic [35:0] rndOvfPos_uid47_fpToFxPTest_o;
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wire [0:0] rndOvfPos_uid47_fpToFxPTest_c;
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wire [0:0] ovfPostRnd_uid48_fpToFxPTest_q;
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wire [2:0] muxSelConc_uid49_fpToFxPTest_q;
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reg [1:0] muxSel_uid50_fpToFxPTest_q;
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wire [31:0] maxNegValueU_uid51_fpToFxPTest_q;
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wire [1:0] finalOut_uid52_fpToFxPTest_s;
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reg [31:0] finalOut_uid52_fpToFxPTest_q;
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wire [15:0] rightShiftStage0Idx1Rng16_uid56_rightShiferNoStickyOut_uid38_fpToFxPTest_b;
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wire [15:0] rightShiftStage0Idx1Pad16_uid57_rightShiferNoStickyOut_uid38_fpToFxPTest_q;
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wire [31:0] rightShiftStage0Idx1_uid58_rightShiferNoStickyOut_uid38_fpToFxPTest_q;
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wire [1:0] rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_s;
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reg [31:0] rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_q;
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wire [27:0] rightShiftStage1Idx1Rng4_uid63_rightShiferNoStickyOut_uid38_fpToFxPTest_b;
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wire [3:0] rightShiftStage1Idx1Pad4_uid64_rightShiferNoStickyOut_uid38_fpToFxPTest_q;
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wire [31:0] rightShiftStage1Idx1_uid65_rightShiferNoStickyOut_uid38_fpToFxPTest_q;
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wire [23:0] rightShiftStage1Idx2Rng8_uid66_rightShiferNoStickyOut_uid38_fpToFxPTest_b;
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wire [31:0] rightShiftStage1Idx2_uid68_rightShiferNoStickyOut_uid38_fpToFxPTest_q;
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wire [19:0] rightShiftStage1Idx3Rng12_uid69_rightShiferNoStickyOut_uid38_fpToFxPTest_b;
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wire [11:0] rightShiftStage1Idx3Pad12_uid70_rightShiferNoStickyOut_uid38_fpToFxPTest_q;
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wire [31:0] rightShiftStage1Idx3_uid71_rightShiferNoStickyOut_uid38_fpToFxPTest_q;
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wire [1:0] rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_s;
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reg [31:0] rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_q;
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wire [30:0] rightShiftStage2Idx1Rng1_uid74_rightShiferNoStickyOut_uid38_fpToFxPTest_b;
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wire [31:0] rightShiftStage2Idx1_uid76_rightShiferNoStickyOut_uid38_fpToFxPTest_q;
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wire [29:0] rightShiftStage2Idx2Rng2_uid77_rightShiferNoStickyOut_uid38_fpToFxPTest_b;
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wire [1:0] rightShiftStage2Idx2Pad2_uid78_rightShiferNoStickyOut_uid38_fpToFxPTest_q;
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wire [31:0] rightShiftStage2Idx2_uid79_rightShiferNoStickyOut_uid38_fpToFxPTest_q;
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wire [28:0] rightShiftStage2Idx3Rng3_uid80_rightShiferNoStickyOut_uid38_fpToFxPTest_b;
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wire [2:0] rightShiftStage2Idx3Pad3_uid81_rightShiferNoStickyOut_uid38_fpToFxPTest_q;
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wire [31:0] rightShiftStage2Idx3_uid82_rightShiferNoStickyOut_uid38_fpToFxPTest_q;
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wire [1:0] rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest_s;
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reg [31:0] rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest_q;
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wire [1:0] rightShiftStageSel5Dto4_uid61_rightShiferNoStickyOut_uid38_fpToFxPTest_merged_bit_select_b;
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wire [1:0] rightShiftStageSel5Dto4_uid61_rightShiferNoStickyOut_uid38_fpToFxPTest_merged_bit_select_c;
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wire [1:0] rightShiftStageSel5Dto4_uid61_rightShiferNoStickyOut_uid38_fpToFxPTest_merged_bit_select_d;
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reg [31:0] redist0_sPostRnd_uid45_fpToFxPTest_b_1_q;
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reg [5:0] redist1_shiftValRaw_uid32_fpToFxPTest_b_1_q;
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reg [0:0] redist2_udf_uid29_fpToFxPTest_n_3_q;
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reg [0:0] redist3_ovfExpRange_uid27_fpToFxPTest_n_3_q;
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reg [0:0] redist4_signX_uid25_fpToFxPTest_b_2_q;
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reg [0:0] redist5_signX_uid25_fpToFxPTest_b_3_q;
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reg [0:0] redist6_fracXIsZero_uid13_fpToFxPTest_q_2_q;
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reg [0:0] redist7_expXIsMax_uid12_fpToFxPTest_q_3_q;
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reg [22:0] redist8_frac_x_uid10_fpToFxPTest_b_1_q;
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// maxNegValueU_uid51_fpToFxPTest(CONSTANT,50)
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assign maxNegValueU_uid51_fpToFxPTest_q = 32'b00000000000000000000000000000000;
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// maxNegValueS_uid40_fpToFxPTest(CONSTANT,39)
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assign maxNegValueS_uid40_fpToFxPTest_q = 32'b10000000000000000000000000000000;
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// maxPosValueS_uid39_fpToFxPTest(CONSTANT,38)
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assign maxPosValueS_uid39_fpToFxPTest_q = 32'b01111111111111111111111111111111;
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// d0_uid43_fpToFxPTest(CONSTANT,42)
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assign d0_uid43_fpToFxPTest_q = 3'b001;
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// signX_uid25_fpToFxPTest(BITSELECT,24)@0
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assign signX_uid25_fpToFxPTest_b = a[31:31];
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// redist4_signX_uid25_fpToFxPTest_b_2(DELAY,90)
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dspba_delay_ver #( .width(1), .depth(2), .reset_kind("ASYNC") )
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redist4_signX_uid25_fpToFxPTest_b_2 ( .xin(signX_uid25_fpToFxPTest_b), .xout(redist4_signX_uid25_fpToFxPTest_b_2_q), .ena(en[0]), .clk(clk), .aclr(areset) );
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// GND(CONSTANT,0)
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assign GND_q = 1'b0;
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// rightShiftStage2Idx3Pad3_uid81_rightShiferNoStickyOut_uid38_fpToFxPTest(CONSTANT,80)
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assign rightShiftStage2Idx3Pad3_uid81_rightShiferNoStickyOut_uid38_fpToFxPTest_q = 3'b000;
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// rightShiftStage2Idx3Rng3_uid80_rightShiferNoStickyOut_uid38_fpToFxPTest(BITSELECT,79)@1
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assign rightShiftStage2Idx3Rng3_uid80_rightShiferNoStickyOut_uid38_fpToFxPTest_b = rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_q[31:3];
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// rightShiftStage2Idx3_uid82_rightShiferNoStickyOut_uid38_fpToFxPTest(BITJOIN,81)@1
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assign rightShiftStage2Idx3_uid82_rightShiferNoStickyOut_uid38_fpToFxPTest_q = {rightShiftStage2Idx3Pad3_uid81_rightShiferNoStickyOut_uid38_fpToFxPTest_q, rightShiftStage2Idx3Rng3_uid80_rightShiferNoStickyOut_uid38_fpToFxPTest_b};
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// rightShiftStage2Idx2Pad2_uid78_rightShiferNoStickyOut_uid38_fpToFxPTest(CONSTANT,77)
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assign rightShiftStage2Idx2Pad2_uid78_rightShiferNoStickyOut_uid38_fpToFxPTest_q = 2'b00;
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// rightShiftStage2Idx2Rng2_uid77_rightShiferNoStickyOut_uid38_fpToFxPTest(BITSELECT,76)@1
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assign rightShiftStage2Idx2Rng2_uid77_rightShiferNoStickyOut_uid38_fpToFxPTest_b = rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_q[31:2];
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// rightShiftStage2Idx2_uid79_rightShiferNoStickyOut_uid38_fpToFxPTest(BITJOIN,78)@1
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assign rightShiftStage2Idx2_uid79_rightShiferNoStickyOut_uid38_fpToFxPTest_q = {rightShiftStage2Idx2Pad2_uid78_rightShiferNoStickyOut_uid38_fpToFxPTest_q, rightShiftStage2Idx2Rng2_uid77_rightShiferNoStickyOut_uid38_fpToFxPTest_b};
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// rightShiftStage2Idx1Rng1_uid74_rightShiferNoStickyOut_uid38_fpToFxPTest(BITSELECT,73)@1
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assign rightShiftStage2Idx1Rng1_uid74_rightShiferNoStickyOut_uid38_fpToFxPTest_b = rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_q[31:1];
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// rightShiftStage2Idx1_uid76_rightShiferNoStickyOut_uid38_fpToFxPTest(BITJOIN,75)@1
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assign rightShiftStage2Idx1_uid76_rightShiferNoStickyOut_uid38_fpToFxPTest_q = {GND_q, rightShiftStage2Idx1Rng1_uid74_rightShiferNoStickyOut_uid38_fpToFxPTest_b};
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// rightShiftStage1Idx3Pad12_uid70_rightShiferNoStickyOut_uid38_fpToFxPTest(CONSTANT,69)
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assign rightShiftStage1Idx3Pad12_uid70_rightShiferNoStickyOut_uid38_fpToFxPTest_q = 12'b000000000000;
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// rightShiftStage1Idx3Rng12_uid69_rightShiferNoStickyOut_uid38_fpToFxPTest(BITSELECT,68)@1
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assign rightShiftStage1Idx3Rng12_uid69_rightShiferNoStickyOut_uid38_fpToFxPTest_b = rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_q[31:12];
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// rightShiftStage1Idx3_uid71_rightShiferNoStickyOut_uid38_fpToFxPTest(BITJOIN,70)@1
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assign rightShiftStage1Idx3_uid71_rightShiferNoStickyOut_uid38_fpToFxPTest_q = {rightShiftStage1Idx3Pad12_uid70_rightShiferNoStickyOut_uid38_fpToFxPTest_q, rightShiftStage1Idx3Rng12_uid69_rightShiferNoStickyOut_uid38_fpToFxPTest_b};
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// cstAllZWE_uid8_fpToFxPTest(CONSTANT,7)
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assign cstAllZWE_uid8_fpToFxPTest_q = 8'b00000000;
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// rightShiftStage1Idx2Rng8_uid66_rightShiferNoStickyOut_uid38_fpToFxPTest(BITSELECT,65)@1
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assign rightShiftStage1Idx2Rng8_uid66_rightShiferNoStickyOut_uid38_fpToFxPTest_b = rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_q[31:8];
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// rightShiftStage1Idx2_uid68_rightShiferNoStickyOut_uid38_fpToFxPTest(BITJOIN,67)@1
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assign rightShiftStage1Idx2_uid68_rightShiferNoStickyOut_uid38_fpToFxPTest_q = {cstAllZWE_uid8_fpToFxPTest_q, rightShiftStage1Idx2Rng8_uid66_rightShiferNoStickyOut_uid38_fpToFxPTest_b};
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// rightShiftStage1Idx1Pad4_uid64_rightShiferNoStickyOut_uid38_fpToFxPTest(CONSTANT,63)
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assign rightShiftStage1Idx1Pad4_uid64_rightShiferNoStickyOut_uid38_fpToFxPTest_q = 4'b0000;
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// rightShiftStage1Idx1Rng4_uid63_rightShiferNoStickyOut_uid38_fpToFxPTest(BITSELECT,62)@1
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assign rightShiftStage1Idx1Rng4_uid63_rightShiferNoStickyOut_uid38_fpToFxPTest_b = rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_q[31:4];
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// rightShiftStage1Idx1_uid65_rightShiferNoStickyOut_uid38_fpToFxPTest(BITJOIN,64)@1
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assign rightShiftStage1Idx1_uid65_rightShiferNoStickyOut_uid38_fpToFxPTest_q = {rightShiftStage1Idx1Pad4_uid64_rightShiferNoStickyOut_uid38_fpToFxPTest_q, rightShiftStage1Idx1Rng4_uid63_rightShiferNoStickyOut_uid38_fpToFxPTest_b};
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// rightShiftStage0Idx1Pad16_uid57_rightShiferNoStickyOut_uid38_fpToFxPTest(CONSTANT,56)
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assign rightShiftStage0Idx1Pad16_uid57_rightShiferNoStickyOut_uid38_fpToFxPTest_q = 16'b0000000000000000;
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// rightShiftStage0Idx1Rng16_uid56_rightShiferNoStickyOut_uid38_fpToFxPTest(BITSELECT,55)@1
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assign rightShiftStage0Idx1Rng16_uid56_rightShiferNoStickyOut_uid38_fpToFxPTest_b = shifterIn_uid37_fpToFxPTest_q[31:16];
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// rightShiftStage0Idx1_uid58_rightShiferNoStickyOut_uid38_fpToFxPTest(BITJOIN,57)@1
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assign rightShiftStage0Idx1_uid58_rightShiferNoStickyOut_uid38_fpToFxPTest_q = {rightShiftStage0Idx1Pad16_uid57_rightShiferNoStickyOut_uid38_fpToFxPTest_q, rightShiftStage0Idx1Rng16_uid56_rightShiferNoStickyOut_uid38_fpToFxPTest_b};
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// exp_x_uid9_fpToFxPTest(BITSELECT,8)@0
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assign exp_x_uid9_fpToFxPTest_b = a[30:23];
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// excZ_x_uid11_fpToFxPTest(LOGICAL,10)@0 + 1
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assign excZ_x_uid11_fpToFxPTest_qi = exp_x_uid9_fpToFxPTest_b == cstAllZWE_uid8_fpToFxPTest_q ? 1'b1 : 1'b0;
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dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
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excZ_x_uid11_fpToFxPTest_delay ( .xin(excZ_x_uid11_fpToFxPTest_qi), .xout(excZ_x_uid11_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
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// invExcXZ_uid22_fpToFxPTest(LOGICAL,21)@1
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assign invExcXZ_uid22_fpToFxPTest_q = ~ (excZ_x_uid11_fpToFxPTest_q);
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// frac_x_uid10_fpToFxPTest(BITSELECT,9)@0
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assign frac_x_uid10_fpToFxPTest_b = a[22:0];
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// redist8_frac_x_uid10_fpToFxPTest_b_1(DELAY,94)
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dspba_delay_ver #( .width(23), .depth(1), .reset_kind("ASYNC") )
|
||||
redist8_frac_x_uid10_fpToFxPTest_b_1 ( .xin(frac_x_uid10_fpToFxPTest_b), .xout(redist8_frac_x_uid10_fpToFxPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// oFracX_uid23_fpToFxPTest(BITJOIN,22)@1
|
||||
assign oFracX_uid23_fpToFxPTest_q = {invExcXZ_uid22_fpToFxPTest_q, redist8_frac_x_uid10_fpToFxPTest_b_1_q};
|
||||
|
||||
// shifterIn_uid37_fpToFxPTest(BITJOIN,36)@1
|
||||
assign shifterIn_uid37_fpToFxPTest_q = {oFracX_uid23_fpToFxPTest_q, cstAllZWE_uid8_fpToFxPTest_q};
|
||||
|
||||
// rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest(MUX,61)@1
|
||||
assign rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_s = rightShiftStageSel5Dto4_uid61_rightShiferNoStickyOut_uid38_fpToFxPTest_merged_bit_select_b;
|
||||
always @(rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_s or en or shifterIn_uid37_fpToFxPTest_q or rightShiftStage0Idx1_uid58_rightShiferNoStickyOut_uid38_fpToFxPTest_q or maxNegValueU_uid51_fpToFxPTest_q)
|
||||
begin
|
||||
unique case (rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_s)
|
||||
2'b00 : rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_q = shifterIn_uid37_fpToFxPTest_q;
|
||||
2'b01 : rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_q = rightShiftStage0Idx1_uid58_rightShiferNoStickyOut_uid38_fpToFxPTest_q;
|
||||
2'b10 : rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_q = maxNegValueU_uid51_fpToFxPTest_q;
|
||||
2'b11 : rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_q = maxNegValueU_uid51_fpToFxPTest_q;
|
||||
default : rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_q = 32'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest(MUX,72)@1
|
||||
assign rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_s = rightShiftStageSel5Dto4_uid61_rightShiferNoStickyOut_uid38_fpToFxPTest_merged_bit_select_c;
|
||||
always @(rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_s or en or rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_q or rightShiftStage1Idx1_uid65_rightShiferNoStickyOut_uid38_fpToFxPTest_q or rightShiftStage1Idx2_uid68_rightShiferNoStickyOut_uid38_fpToFxPTest_q or rightShiftStage1Idx3_uid71_rightShiferNoStickyOut_uid38_fpToFxPTest_q)
|
||||
begin
|
||||
unique case (rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_s)
|
||||
2'b00 : rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_q = rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_q;
|
||||
2'b01 : rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_q = rightShiftStage1Idx1_uid65_rightShiferNoStickyOut_uid38_fpToFxPTest_q;
|
||||
2'b10 : rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_q = rightShiftStage1Idx2_uid68_rightShiferNoStickyOut_uid38_fpToFxPTest_q;
|
||||
2'b11 : rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_q = rightShiftStage1Idx3_uid71_rightShiferNoStickyOut_uid38_fpToFxPTest_q;
|
||||
default : rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_q = 32'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// maxShiftCst_uid33_fpToFxPTest(CONSTANT,32)
|
||||
assign maxShiftCst_uid33_fpToFxPTest_q = 6'b100000;
|
||||
|
||||
// ovfExpVal_uid30_fpToFxPTest(CONSTANT,29)
|
||||
assign ovfExpVal_uid30_fpToFxPTest_q = 9'b010011101;
|
||||
|
||||
// shiftValE_uid31_fpToFxPTest(SUB,30)@0
|
||||
assign shiftValE_uid31_fpToFxPTest_a = {{2{ovfExpVal_uid30_fpToFxPTest_q[8]}}, ovfExpVal_uid30_fpToFxPTest_q};
|
||||
assign shiftValE_uid31_fpToFxPTest_b = {3'b000, exp_x_uid9_fpToFxPTest_b};
|
||||
assign shiftValE_uid31_fpToFxPTest_o = $signed(shiftValE_uid31_fpToFxPTest_a) - $signed(shiftValE_uid31_fpToFxPTest_b);
|
||||
assign shiftValE_uid31_fpToFxPTest_q = shiftValE_uid31_fpToFxPTest_o[9:0];
|
||||
|
||||
// shiftValRaw_uid32_fpToFxPTest(BITSELECT,31)@0
|
||||
assign shiftValRaw_uid32_fpToFxPTest_in = shiftValE_uid31_fpToFxPTest_q[5:0];
|
||||
assign shiftValRaw_uid32_fpToFxPTest_b = shiftValRaw_uid32_fpToFxPTest_in[5:0];
|
||||
|
||||
// redist1_shiftValRaw_uid32_fpToFxPTest_b_1(DELAY,87)
|
||||
dspba_delay_ver #( .width(6), .depth(1), .reset_kind("ASYNC") )
|
||||
redist1_shiftValRaw_uid32_fpToFxPTest_b_1 ( .xin(shiftValRaw_uid32_fpToFxPTest_b), .xout(redist1_shiftValRaw_uid32_fpToFxPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// shiftOutOfRange_uid34_fpToFxPTest(COMPARE,33)@0 + 1
|
||||
assign shiftOutOfRange_uid34_fpToFxPTest_a = {{2{shiftValE_uid31_fpToFxPTest_q[9]}}, shiftValE_uid31_fpToFxPTest_q};
|
||||
assign shiftOutOfRange_uid34_fpToFxPTest_b = {6'b000000, maxShiftCst_uid33_fpToFxPTest_q};
|
||||
always @ (posedge clk or posedge areset)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
shiftOutOfRange_uid34_fpToFxPTest_o <= 12'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
shiftOutOfRange_uid34_fpToFxPTest_o <= $signed(shiftOutOfRange_uid34_fpToFxPTest_a) - $signed(shiftOutOfRange_uid34_fpToFxPTest_b);
|
||||
end
|
||||
end
|
||||
assign shiftOutOfRange_uid34_fpToFxPTest_n[0] = ~ (shiftOutOfRange_uid34_fpToFxPTest_o[11]);
|
||||
|
||||
// shiftVal_uid35_fpToFxPTest(MUX,34)@1
|
||||
assign shiftVal_uid35_fpToFxPTest_s = shiftOutOfRange_uid34_fpToFxPTest_n;
|
||||
always @(shiftVal_uid35_fpToFxPTest_s or en or redist1_shiftValRaw_uid32_fpToFxPTest_b_1_q or maxShiftCst_uid33_fpToFxPTest_q)
|
||||
begin
|
||||
unique case (shiftVal_uid35_fpToFxPTest_s)
|
||||
1'b0 : shiftVal_uid35_fpToFxPTest_q = redist1_shiftValRaw_uid32_fpToFxPTest_b_1_q;
|
||||
1'b1 : shiftVal_uid35_fpToFxPTest_q = maxShiftCst_uid33_fpToFxPTest_q;
|
||||
default : shiftVal_uid35_fpToFxPTest_q = 6'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// rightShiftStageSel5Dto4_uid61_rightShiferNoStickyOut_uid38_fpToFxPTest_merged_bit_select(BITSELECT,85)@1
|
||||
assign rightShiftStageSel5Dto4_uid61_rightShiferNoStickyOut_uid38_fpToFxPTest_merged_bit_select_b = shiftVal_uid35_fpToFxPTest_q[5:4];
|
||||
assign rightShiftStageSel5Dto4_uid61_rightShiferNoStickyOut_uid38_fpToFxPTest_merged_bit_select_c = shiftVal_uid35_fpToFxPTest_q[3:2];
|
||||
assign rightShiftStageSel5Dto4_uid61_rightShiferNoStickyOut_uid38_fpToFxPTest_merged_bit_select_d = shiftVal_uid35_fpToFxPTest_q[1:0];
|
||||
|
||||
// rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest(MUX,83)@1 + 1
|
||||
assign rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest_s = rightShiftStageSel5Dto4_uid61_rightShiferNoStickyOut_uid38_fpToFxPTest_merged_bit_select_d;
|
||||
always @ (posedge clk or posedge areset)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest_q <= 32'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
unique case (rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest_s)
|
||||
2'b00 : rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest_q <= rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_q;
|
||||
2'b01 : rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest_q <= rightShiftStage2Idx1_uid76_rightShiferNoStickyOut_uid38_fpToFxPTest_q;
|
||||
2'b10 : rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest_q <= rightShiftStage2Idx2_uid79_rightShiferNoStickyOut_uid38_fpToFxPTest_q;
|
||||
2'b11 : rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest_q <= rightShiftStage2Idx3_uid82_rightShiferNoStickyOut_uid38_fpToFxPTest_q;
|
||||
default : rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest_q <= 32'b0;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// zRightShiferNoStickyOut_uid41_fpToFxPTest(BITJOIN,40)@2
|
||||
assign zRightShiferNoStickyOut_uid41_fpToFxPTest_q = {GND_q, rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest_q};
|
||||
|
||||
// xXorSignE_uid42_fpToFxPTest(LOGICAL,41)@2
|
||||
assign xXorSignE_uid42_fpToFxPTest_b = {{32{redist4_signX_uid25_fpToFxPTest_b_2_q[0]}}, redist4_signX_uid25_fpToFxPTest_b_2_q};
|
||||
assign xXorSignE_uid42_fpToFxPTest_q = zRightShiferNoStickyOut_uid41_fpToFxPTest_q ^ xXorSignE_uid42_fpToFxPTest_b;
|
||||
|
||||
// sPostRndFull_uid44_fpToFxPTest(ADD,43)@2
|
||||
assign sPostRndFull_uid44_fpToFxPTest_a = {{1{xXorSignE_uid42_fpToFxPTest_q[32]}}, xXorSignE_uid42_fpToFxPTest_q};
|
||||
assign sPostRndFull_uid44_fpToFxPTest_b = {{31{d0_uid43_fpToFxPTest_q[2]}}, d0_uid43_fpToFxPTest_q};
|
||||
assign sPostRndFull_uid44_fpToFxPTest_o = $signed(sPostRndFull_uid44_fpToFxPTest_a) + $signed(sPostRndFull_uid44_fpToFxPTest_b);
|
||||
assign sPostRndFull_uid44_fpToFxPTest_q = sPostRndFull_uid44_fpToFxPTest_o[33:0];
|
||||
|
||||
// sPostRnd_uid45_fpToFxPTest(BITSELECT,44)@2
|
||||
assign sPostRnd_uid45_fpToFxPTest_in = sPostRndFull_uid44_fpToFxPTest_q[32:0];
|
||||
assign sPostRnd_uid45_fpToFxPTest_b = sPostRnd_uid45_fpToFxPTest_in[32:1];
|
||||
|
||||
// redist0_sPostRnd_uid45_fpToFxPTest_b_1(DELAY,86)
|
||||
dspba_delay_ver #( .width(32), .depth(1), .reset_kind("ASYNC") )
|
||||
redist0_sPostRnd_uid45_fpToFxPTest_b_1 ( .xin(sPostRnd_uid45_fpToFxPTest_b), .xout(redist0_sPostRnd_uid45_fpToFxPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// redist5_signX_uid25_fpToFxPTest_b_3(DELAY,91)
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
|
||||
redist5_signX_uid25_fpToFxPTest_b_3 ( .xin(redist4_signX_uid25_fpToFxPTest_b_2_q), .xout(redist5_signX_uid25_fpToFxPTest_b_3_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// udfExpVal_uid28_fpToFxPTest(CONSTANT,27)
|
||||
assign udfExpVal_uid28_fpToFxPTest_q = 8'b01111101;
|
||||
|
||||
// udf_uid29_fpToFxPTest(COMPARE,28)@0 + 1
|
||||
assign udf_uid29_fpToFxPTest_a = {{3{udfExpVal_uid28_fpToFxPTest_q[7]}}, udfExpVal_uid28_fpToFxPTest_q};
|
||||
assign udf_uid29_fpToFxPTest_b = {3'b000, exp_x_uid9_fpToFxPTest_b};
|
||||
always @ (posedge clk or posedge areset)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
udf_uid29_fpToFxPTest_o <= 11'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
udf_uid29_fpToFxPTest_o <= $signed(udf_uid29_fpToFxPTest_a) - $signed(udf_uid29_fpToFxPTest_b);
|
||||
end
|
||||
end
|
||||
assign udf_uid29_fpToFxPTest_n[0] = ~ (udf_uid29_fpToFxPTest_o[10]);
|
||||
|
||||
// redist2_udf_uid29_fpToFxPTest_n_3(DELAY,88)
|
||||
dspba_delay_ver #( .width(1), .depth(2), .reset_kind("ASYNC") )
|
||||
redist2_udf_uid29_fpToFxPTest_n_3 ( .xin(udf_uid29_fpToFxPTest_n), .xout(redist2_udf_uid29_fpToFxPTest_n_3_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// sPostRnd_uid46_fpToFxPTest(BITSELECT,45)@2
|
||||
assign sPostRnd_uid46_fpToFxPTest_in = {{1{sPostRndFull_uid44_fpToFxPTest_q[33]}}, sPostRndFull_uid44_fpToFxPTest_q};
|
||||
assign sPostRnd_uid46_fpToFxPTest_b = sPostRnd_uid46_fpToFxPTest_in[34:1];
|
||||
|
||||
// rndOvfPos_uid47_fpToFxPTest(COMPARE,46)@2 + 1
|
||||
assign rndOvfPos_uid47_fpToFxPTest_a = {4'b0000, maxPosValueS_uid39_fpToFxPTest_q};
|
||||
assign rndOvfPos_uid47_fpToFxPTest_b = {{2{sPostRnd_uid46_fpToFxPTest_b[33]}}, sPostRnd_uid46_fpToFxPTest_b};
|
||||
always @ (posedge clk or posedge areset)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
rndOvfPos_uid47_fpToFxPTest_o <= 36'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
rndOvfPos_uid47_fpToFxPTest_o <= $signed(rndOvfPos_uid47_fpToFxPTest_a) - $signed(rndOvfPos_uid47_fpToFxPTest_b);
|
||||
end
|
||||
end
|
||||
assign rndOvfPos_uid47_fpToFxPTest_c[0] = rndOvfPos_uid47_fpToFxPTest_o[35];
|
||||
|
||||
// ovfExpVal_uid26_fpToFxPTest(CONSTANT,25)
|
||||
assign ovfExpVal_uid26_fpToFxPTest_q = 9'b010011110;
|
||||
|
||||
// ovfExpRange_uid27_fpToFxPTest(COMPARE,26)@0 + 1
|
||||
assign ovfExpRange_uid27_fpToFxPTest_a = {3'b000, exp_x_uid9_fpToFxPTest_b};
|
||||
assign ovfExpRange_uid27_fpToFxPTest_b = {{2{ovfExpVal_uid26_fpToFxPTest_q[8]}}, ovfExpVal_uid26_fpToFxPTest_q};
|
||||
always @ (posedge clk or posedge areset)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
ovfExpRange_uid27_fpToFxPTest_o <= 11'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
ovfExpRange_uid27_fpToFxPTest_o <= $signed(ovfExpRange_uid27_fpToFxPTest_a) - $signed(ovfExpRange_uid27_fpToFxPTest_b);
|
||||
end
|
||||
end
|
||||
assign ovfExpRange_uid27_fpToFxPTest_n[0] = ~ (ovfExpRange_uid27_fpToFxPTest_o[10]);
|
||||
|
||||
// redist3_ovfExpRange_uid27_fpToFxPTest_n_3(DELAY,89)
|
||||
dspba_delay_ver #( .width(1), .depth(2), .reset_kind("ASYNC") )
|
||||
redist3_ovfExpRange_uid27_fpToFxPTest_n_3 ( .xin(ovfExpRange_uid27_fpToFxPTest_n), .xout(redist3_ovfExpRange_uid27_fpToFxPTest_n_3_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// cstZeroWF_uid7_fpToFxPTest(CONSTANT,6)
|
||||
assign cstZeroWF_uid7_fpToFxPTest_q = 23'b00000000000000000000000;
|
||||
|
||||
// fracXIsZero_uid13_fpToFxPTest(LOGICAL,12)@1 + 1
|
||||
assign fracXIsZero_uid13_fpToFxPTest_qi = cstZeroWF_uid7_fpToFxPTest_q == redist8_frac_x_uid10_fpToFxPTest_b_1_q ? 1'b1 : 1'b0;
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
|
||||
fracXIsZero_uid13_fpToFxPTest_delay ( .xin(fracXIsZero_uid13_fpToFxPTest_qi), .xout(fracXIsZero_uid13_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// redist6_fracXIsZero_uid13_fpToFxPTest_q_2(DELAY,92)
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
|
||||
redist6_fracXIsZero_uid13_fpToFxPTest_q_2 ( .xin(fracXIsZero_uid13_fpToFxPTest_q), .xout(redist6_fracXIsZero_uid13_fpToFxPTest_q_2_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// cstAllOWE_uid6_fpToFxPTest(CONSTANT,5)
|
||||
assign cstAllOWE_uid6_fpToFxPTest_q = 8'b11111111;
|
||||
|
||||
// expXIsMax_uid12_fpToFxPTest(LOGICAL,11)@0 + 1
|
||||
assign expXIsMax_uid12_fpToFxPTest_qi = exp_x_uid9_fpToFxPTest_b == cstAllOWE_uid6_fpToFxPTest_q ? 1'b1 : 1'b0;
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
|
||||
expXIsMax_uid12_fpToFxPTest_delay ( .xin(expXIsMax_uid12_fpToFxPTest_qi), .xout(expXIsMax_uid12_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// redist7_expXIsMax_uid12_fpToFxPTest_q_3(DELAY,93)
|
||||
dspba_delay_ver #( .width(1), .depth(2), .reset_kind("ASYNC") )
|
||||
redist7_expXIsMax_uid12_fpToFxPTest_q_3 ( .xin(expXIsMax_uid12_fpToFxPTest_q), .xout(redist7_expXIsMax_uid12_fpToFxPTest_q_3_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// excI_x_uid15_fpToFxPTest(LOGICAL,14)@3
|
||||
assign excI_x_uid15_fpToFxPTest_q = redist7_expXIsMax_uid12_fpToFxPTest_q_3_q & redist6_fracXIsZero_uid13_fpToFxPTest_q_2_q;
|
||||
|
||||
// fracXIsNotZero_uid14_fpToFxPTest(LOGICAL,13)@3
|
||||
assign fracXIsNotZero_uid14_fpToFxPTest_q = ~ (redist6_fracXIsZero_uid13_fpToFxPTest_q_2_q);
|
||||
|
||||
// excN_x_uid16_fpToFxPTest(LOGICAL,15)@3
|
||||
assign excN_x_uid16_fpToFxPTest_q = redist7_expXIsMax_uid12_fpToFxPTest_q_3_q & fracXIsNotZero_uid14_fpToFxPTest_q;
|
||||
|
||||
// ovfPostRnd_uid48_fpToFxPTest(LOGICAL,47)@3
|
||||
assign ovfPostRnd_uid48_fpToFxPTest_q = excN_x_uid16_fpToFxPTest_q | excI_x_uid15_fpToFxPTest_q | redist3_ovfExpRange_uid27_fpToFxPTest_n_3_q | rndOvfPos_uid47_fpToFxPTest_c;
|
||||
|
||||
// muxSelConc_uid49_fpToFxPTest(BITJOIN,48)@3
|
||||
assign muxSelConc_uid49_fpToFxPTest_q = {redist5_signX_uid25_fpToFxPTest_b_3_q, redist2_udf_uid29_fpToFxPTest_n_3_q, ovfPostRnd_uid48_fpToFxPTest_q};
|
||||
|
||||
// muxSel_uid50_fpToFxPTest(LOOKUP,49)@3
|
||||
always @(muxSelConc_uid49_fpToFxPTest_q)
|
||||
begin
|
||||
// Begin reserved scope level
|
||||
unique case (muxSelConc_uid49_fpToFxPTest_q)
|
||||
3'b000 : muxSel_uid50_fpToFxPTest_q = 2'b00;
|
||||
3'b001 : muxSel_uid50_fpToFxPTest_q = 2'b01;
|
||||
3'b010 : muxSel_uid50_fpToFxPTest_q = 2'b11;
|
||||
3'b011 : muxSel_uid50_fpToFxPTest_q = 2'b11;
|
||||
3'b100 : muxSel_uid50_fpToFxPTest_q = 2'b00;
|
||||
3'b101 : muxSel_uid50_fpToFxPTest_q = 2'b10;
|
||||
3'b110 : muxSel_uid50_fpToFxPTest_q = 2'b11;
|
||||
3'b111 : muxSel_uid50_fpToFxPTest_q = 2'b11;
|
||||
default : begin
|
||||
// unreachable
|
||||
muxSel_uid50_fpToFxPTest_q = 2'bxx;
|
||||
end
|
||||
endcase
|
||||
// End reserved scope level
|
||||
end
|
||||
|
||||
// finalOut_uid52_fpToFxPTest(MUX,51)@3
|
||||
assign finalOut_uid52_fpToFxPTest_s = muxSel_uid50_fpToFxPTest_q;
|
||||
always @(finalOut_uid52_fpToFxPTest_s or en or redist0_sPostRnd_uid45_fpToFxPTest_b_1_q or maxPosValueS_uid39_fpToFxPTest_q or maxNegValueS_uid40_fpToFxPTest_q or maxNegValueU_uid51_fpToFxPTest_q)
|
||||
begin
|
||||
unique case (finalOut_uid52_fpToFxPTest_s)
|
||||
2'b00 : finalOut_uid52_fpToFxPTest_q = redist0_sPostRnd_uid45_fpToFxPTest_b_1_q;
|
||||
2'b01 : finalOut_uid52_fpToFxPTest_q = maxPosValueS_uid39_fpToFxPTest_q;
|
||||
2'b10 : finalOut_uid52_fpToFxPTest_q = maxNegValueS_uid40_fpToFxPTest_q;
|
||||
2'b11 : finalOut_uid52_fpToFxPTest_q = maxNegValueU_uid51_fpToFxPTest_q;
|
||||
default : finalOut_uid52_fpToFxPTest_q = 32'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// xOut(GPOUT,4)@3
|
||||
assign q = finalOut_uid52_fpToFxPTest_q;
|
||||
|
||||
endmodule
|
||||
@@ -1,493 +0,0 @@
|
||||
// -------------------------------------------------------------------------
|
||||
// High Level Design Compiler for Intel(R) FPGAs Version 17.1 (Release Build #273)
|
||||
// Quartus Prime development tool and MATLAB/Simulink Interface
|
||||
//
|
||||
// Legal Notice: Copyright 2017 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly
|
||||
// subject to the terms and conditions of the Intel FPGA Software License
|
||||
// Agreement, Intel MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for
|
||||
// the sole purpose of programming logic devices manufactured by Intel
|
||||
// and sold by Intel or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
// ---------------------------------------------------------------------------
|
||||
|
||||
// SystemVerilog created from acl_ftou
|
||||
// SystemVerilog created on Sun Dec 27 09:47:21 2020
|
||||
|
||||
|
||||
(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
|
||||
module acl_ftou (
|
||||
input wire [31:0] a,
|
||||
input wire [0:0] en,
|
||||
output wire [31:0] q,
|
||||
input wire clk,
|
||||
input wire areset
|
||||
);
|
||||
|
||||
wire [0:0] GND_q;
|
||||
wire [0:0] VCC_q;
|
||||
wire [7:0] cstAllOWE_uid6_fpToFxPTest_q;
|
||||
wire [22:0] cstZeroWF_uid7_fpToFxPTest_q;
|
||||
wire [7:0] cstAllZWE_uid8_fpToFxPTest_q;
|
||||
wire [7:0] exp_x_uid9_fpToFxPTest_b;
|
||||
wire [22:0] frac_x_uid10_fpToFxPTest_b;
|
||||
wire [0:0] excZ_x_uid11_fpToFxPTest_qi;
|
||||
reg [0:0] excZ_x_uid11_fpToFxPTest_q;
|
||||
wire [0:0] expXIsMax_uid12_fpToFxPTest_qi;
|
||||
reg [0:0] expXIsMax_uid12_fpToFxPTest_q;
|
||||
wire [0:0] fracXIsZero_uid13_fpToFxPTest_qi;
|
||||
reg [0:0] fracXIsZero_uid13_fpToFxPTest_q;
|
||||
wire [0:0] fracXIsNotZero_uid14_fpToFxPTest_q;
|
||||
wire [0:0] excI_x_uid15_fpToFxPTest_q;
|
||||
wire [0:0] excN_x_uid16_fpToFxPTest_q;
|
||||
wire [0:0] invExcXZ_uid22_fpToFxPTest_q;
|
||||
wire [23:0] oFracX_uid23_fpToFxPTest_q;
|
||||
wire [0:0] signX_uid25_fpToFxPTest_b;
|
||||
wire [8:0] ovfExpVal_uid26_fpToFxPTest_q;
|
||||
wire [10:0] ovf_uid27_fpToFxPTest_a;
|
||||
wire [10:0] ovf_uid27_fpToFxPTest_b;
|
||||
logic [10:0] ovf_uid27_fpToFxPTest_o;
|
||||
wire [0:0] ovf_uid27_fpToFxPTest_n;
|
||||
wire [0:0] negOrOvf_uid28_fpToFxPTest_q;
|
||||
wire [7:0] udfExpVal_uid29_fpToFxPTest_q;
|
||||
wire [10:0] udf_uid30_fpToFxPTest_a;
|
||||
wire [10:0] udf_uid30_fpToFxPTest_b;
|
||||
logic [10:0] udf_uid30_fpToFxPTest_o;
|
||||
wire [0:0] udf_uid30_fpToFxPTest_n;
|
||||
wire [8:0] ovfExpVal_uid31_fpToFxPTest_q;
|
||||
wire [10:0] shiftValE_uid32_fpToFxPTest_a;
|
||||
wire [10:0] shiftValE_uid32_fpToFxPTest_b;
|
||||
logic [10:0] shiftValE_uid32_fpToFxPTest_o;
|
||||
wire [9:0] shiftValE_uid32_fpToFxPTest_q;
|
||||
wire [5:0] shiftValRaw_uid33_fpToFxPTest_in;
|
||||
wire [5:0] shiftValRaw_uid33_fpToFxPTest_b;
|
||||
wire [5:0] maxShiftCst_uid34_fpToFxPTest_q;
|
||||
wire [11:0] shiftOutOfRange_uid35_fpToFxPTest_a;
|
||||
wire [11:0] shiftOutOfRange_uid35_fpToFxPTest_b;
|
||||
logic [11:0] shiftOutOfRange_uid35_fpToFxPTest_o;
|
||||
wire [0:0] shiftOutOfRange_uid35_fpToFxPTest_n;
|
||||
wire [0:0] shiftVal_uid36_fpToFxPTest_s;
|
||||
reg [5:0] shiftVal_uid36_fpToFxPTest_q;
|
||||
wire [8:0] zPadd_uid37_fpToFxPTest_q;
|
||||
wire [32:0] shifterIn_uid38_fpToFxPTest_q;
|
||||
wire [31:0] maxPosValueU_uid40_fpToFxPTest_q;
|
||||
wire [31:0] maxNegValueU_uid41_fpToFxPTest_q;
|
||||
wire [33:0] zRightShiferNoStickyOut_uid43_fpToFxPTest_q;
|
||||
wire [34:0] sPostRndFull_uid44_fpToFxPTest_a;
|
||||
wire [34:0] sPostRndFull_uid44_fpToFxPTest_b;
|
||||
logic [34:0] sPostRndFull_uid44_fpToFxPTest_o;
|
||||
wire [34:0] sPostRndFull_uid44_fpToFxPTest_q;
|
||||
wire [32:0] sPostRnd_uid45_fpToFxPTest_in;
|
||||
wire [31:0] sPostRnd_uid45_fpToFxPTest_b;
|
||||
wire [33:0] sPostRndFullMSBU_uid46_fpToFxPTest_in;
|
||||
wire [0:0] sPostRndFullMSBU_uid46_fpToFxPTest_b;
|
||||
wire [0:0] ovfPostRnd_uid47_fpToFxPTest_q;
|
||||
wire [2:0] muxSelConc_uid48_fpToFxPTest_q;
|
||||
reg [1:0] muxSel_uid49_fpToFxPTest_q;
|
||||
wire [1:0] finalOut_uid51_fpToFxPTest_s;
|
||||
reg [31:0] finalOut_uid51_fpToFxPTest_q;
|
||||
wire [16:0] rightShiftStage0Idx1Rng16_uid55_rightShiferNoStickyOut_uid39_fpToFxPTest_b;
|
||||
wire [15:0] rightShiftStage0Idx1Pad16_uid56_rightShiferNoStickyOut_uid39_fpToFxPTest_q;
|
||||
wire [32:0] rightShiftStage0Idx1_uid57_rightShiferNoStickyOut_uid39_fpToFxPTest_q;
|
||||
wire [0:0] rightShiftStage0Idx2Rng32_uid58_rightShiferNoStickyOut_uid39_fpToFxPTest_b;
|
||||
wire [32:0] rightShiftStage0Idx2_uid60_rightShiferNoStickyOut_uid39_fpToFxPTest_q;
|
||||
wire [32:0] rightShiftStage0Idx3_uid61_rightShiferNoStickyOut_uid39_fpToFxPTest_q;
|
||||
wire [1:0] rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_s;
|
||||
reg [32:0] rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_q;
|
||||
wire [28:0] rightShiftStage1Idx1Rng4_uid64_rightShiferNoStickyOut_uid39_fpToFxPTest_b;
|
||||
wire [3:0] rightShiftStage1Idx1Pad4_uid65_rightShiferNoStickyOut_uid39_fpToFxPTest_q;
|
||||
wire [32:0] rightShiftStage1Idx1_uid66_rightShiferNoStickyOut_uid39_fpToFxPTest_q;
|
||||
wire [24:0] rightShiftStage1Idx2Rng8_uid67_rightShiferNoStickyOut_uid39_fpToFxPTest_b;
|
||||
wire [32:0] rightShiftStage1Idx2_uid69_rightShiferNoStickyOut_uid39_fpToFxPTest_q;
|
||||
wire [20:0] rightShiftStage1Idx3Rng12_uid70_rightShiferNoStickyOut_uid39_fpToFxPTest_b;
|
||||
wire [11:0] rightShiftStage1Idx3Pad12_uid71_rightShiferNoStickyOut_uid39_fpToFxPTest_q;
|
||||
wire [32:0] rightShiftStage1Idx3_uid72_rightShiferNoStickyOut_uid39_fpToFxPTest_q;
|
||||
wire [1:0] rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_s;
|
||||
reg [32:0] rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_q;
|
||||
wire [31:0] rightShiftStage2Idx1Rng1_uid75_rightShiferNoStickyOut_uid39_fpToFxPTest_b;
|
||||
wire [32:0] rightShiftStage2Idx1_uid77_rightShiferNoStickyOut_uid39_fpToFxPTest_q;
|
||||
wire [30:0] rightShiftStage2Idx2Rng2_uid78_rightShiferNoStickyOut_uid39_fpToFxPTest_b;
|
||||
wire [1:0] rightShiftStage2Idx2Pad2_uid79_rightShiferNoStickyOut_uid39_fpToFxPTest_q;
|
||||
wire [32:0] rightShiftStage2Idx2_uid80_rightShiferNoStickyOut_uid39_fpToFxPTest_q;
|
||||
wire [29:0] rightShiftStage2Idx3Rng3_uid81_rightShiferNoStickyOut_uid39_fpToFxPTest_b;
|
||||
wire [2:0] rightShiftStage2Idx3Pad3_uid82_rightShiferNoStickyOut_uid39_fpToFxPTest_q;
|
||||
wire [32:0] rightShiftStage2Idx3_uid83_rightShiferNoStickyOut_uid39_fpToFxPTest_q;
|
||||
wire [1:0] rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest_s;
|
||||
reg [32:0] rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest_q;
|
||||
wire [1:0] rightShiftStageSel5Dto4_uid62_rightShiferNoStickyOut_uid39_fpToFxPTest_merged_bit_select_b;
|
||||
wire [1:0] rightShiftStageSel5Dto4_uid62_rightShiferNoStickyOut_uid39_fpToFxPTest_merged_bit_select_c;
|
||||
wire [1:0] rightShiftStageSel5Dto4_uid62_rightShiferNoStickyOut_uid39_fpToFxPTest_merged_bit_select_d;
|
||||
reg [31:0] redist0_sPostRnd_uid45_fpToFxPTest_b_1_q;
|
||||
reg [5:0] redist1_shiftValRaw_uid33_fpToFxPTest_b_1_q;
|
||||
reg [0:0] redist2_udf_uid30_fpToFxPTest_n_2_q;
|
||||
reg [0:0] redist3_ovf_uid27_fpToFxPTest_n_2_q;
|
||||
reg [0:0] redist4_signX_uid25_fpToFxPTest_b_2_q;
|
||||
reg [0:0] redist5_expXIsMax_uid12_fpToFxPTest_q_2_q;
|
||||
reg [22:0] redist6_frac_x_uid10_fpToFxPTest_b_1_q;
|
||||
|
||||
|
||||
// maxNegValueU_uid41_fpToFxPTest(CONSTANT,40)
|
||||
assign maxNegValueU_uid41_fpToFxPTest_q = 32'b00000000000000000000000000000000;
|
||||
|
||||
// maxPosValueU_uid40_fpToFxPTest(CONSTANT,39)
|
||||
assign maxPosValueU_uid40_fpToFxPTest_q = 32'b11111111111111111111111111111111;
|
||||
|
||||
// VCC(CONSTANT,1)
|
||||
assign VCC_q = 1'b1;
|
||||
|
||||
// GND(CONSTANT,0)
|
||||
assign GND_q = 1'b0;
|
||||
|
||||
// rightShiftStage2Idx3Pad3_uid82_rightShiferNoStickyOut_uid39_fpToFxPTest(CONSTANT,81)
|
||||
assign rightShiftStage2Idx3Pad3_uid82_rightShiferNoStickyOut_uid39_fpToFxPTest_q = 3'b000;
|
||||
|
||||
// rightShiftStage2Idx3Rng3_uid81_rightShiferNoStickyOut_uid39_fpToFxPTest(BITSELECT,80)@1
|
||||
assign rightShiftStage2Idx3Rng3_uid81_rightShiferNoStickyOut_uid39_fpToFxPTest_b = rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_q[32:3];
|
||||
|
||||
// rightShiftStage2Idx3_uid83_rightShiferNoStickyOut_uid39_fpToFxPTest(BITJOIN,82)@1
|
||||
assign rightShiftStage2Idx3_uid83_rightShiferNoStickyOut_uid39_fpToFxPTest_q = {rightShiftStage2Idx3Pad3_uid82_rightShiferNoStickyOut_uid39_fpToFxPTest_q, rightShiftStage2Idx3Rng3_uid81_rightShiferNoStickyOut_uid39_fpToFxPTest_b};
|
||||
|
||||
// rightShiftStage2Idx2Pad2_uid79_rightShiferNoStickyOut_uid39_fpToFxPTest(CONSTANT,78)
|
||||
assign rightShiftStage2Idx2Pad2_uid79_rightShiferNoStickyOut_uid39_fpToFxPTest_q = 2'b00;
|
||||
|
||||
// rightShiftStage2Idx2Rng2_uid78_rightShiferNoStickyOut_uid39_fpToFxPTest(BITSELECT,77)@1
|
||||
assign rightShiftStage2Idx2Rng2_uid78_rightShiferNoStickyOut_uid39_fpToFxPTest_b = rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_q[32:2];
|
||||
|
||||
// rightShiftStage2Idx2_uid80_rightShiferNoStickyOut_uid39_fpToFxPTest(BITJOIN,79)@1
|
||||
assign rightShiftStage2Idx2_uid80_rightShiferNoStickyOut_uid39_fpToFxPTest_q = {rightShiftStage2Idx2Pad2_uid79_rightShiferNoStickyOut_uid39_fpToFxPTest_q, rightShiftStage2Idx2Rng2_uid78_rightShiferNoStickyOut_uid39_fpToFxPTest_b};
|
||||
|
||||
// rightShiftStage2Idx1Rng1_uid75_rightShiferNoStickyOut_uid39_fpToFxPTest(BITSELECT,74)@1
|
||||
assign rightShiftStage2Idx1Rng1_uid75_rightShiferNoStickyOut_uid39_fpToFxPTest_b = rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_q[32:1];
|
||||
|
||||
// rightShiftStage2Idx1_uid77_rightShiferNoStickyOut_uid39_fpToFxPTest(BITJOIN,76)@1
|
||||
assign rightShiftStage2Idx1_uid77_rightShiferNoStickyOut_uid39_fpToFxPTest_q = {GND_q, rightShiftStage2Idx1Rng1_uid75_rightShiferNoStickyOut_uid39_fpToFxPTest_b};
|
||||
|
||||
// rightShiftStage1Idx3Pad12_uid71_rightShiferNoStickyOut_uid39_fpToFxPTest(CONSTANT,70)
|
||||
assign rightShiftStage1Idx3Pad12_uid71_rightShiferNoStickyOut_uid39_fpToFxPTest_q = 12'b000000000000;
|
||||
|
||||
// rightShiftStage1Idx3Rng12_uid70_rightShiferNoStickyOut_uid39_fpToFxPTest(BITSELECT,69)@1
|
||||
assign rightShiftStage1Idx3Rng12_uid70_rightShiferNoStickyOut_uid39_fpToFxPTest_b = rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_q[32:12];
|
||||
|
||||
// rightShiftStage1Idx3_uid72_rightShiferNoStickyOut_uid39_fpToFxPTest(BITJOIN,71)@1
|
||||
assign rightShiftStage1Idx3_uid72_rightShiferNoStickyOut_uid39_fpToFxPTest_q = {rightShiftStage1Idx3Pad12_uid71_rightShiferNoStickyOut_uid39_fpToFxPTest_q, rightShiftStage1Idx3Rng12_uid70_rightShiferNoStickyOut_uid39_fpToFxPTest_b};
|
||||
|
||||
// cstAllZWE_uid8_fpToFxPTest(CONSTANT,7)
|
||||
assign cstAllZWE_uid8_fpToFxPTest_q = 8'b00000000;
|
||||
|
||||
// rightShiftStage1Idx2Rng8_uid67_rightShiferNoStickyOut_uid39_fpToFxPTest(BITSELECT,66)@1
|
||||
assign rightShiftStage1Idx2Rng8_uid67_rightShiferNoStickyOut_uid39_fpToFxPTest_b = rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_q[32:8];
|
||||
|
||||
// rightShiftStage1Idx2_uid69_rightShiferNoStickyOut_uid39_fpToFxPTest(BITJOIN,68)@1
|
||||
assign rightShiftStage1Idx2_uid69_rightShiferNoStickyOut_uid39_fpToFxPTest_q = {cstAllZWE_uid8_fpToFxPTest_q, rightShiftStage1Idx2Rng8_uid67_rightShiferNoStickyOut_uid39_fpToFxPTest_b};
|
||||
|
||||
// rightShiftStage1Idx1Pad4_uid65_rightShiferNoStickyOut_uid39_fpToFxPTest(CONSTANT,64)
|
||||
assign rightShiftStage1Idx1Pad4_uid65_rightShiferNoStickyOut_uid39_fpToFxPTest_q = 4'b0000;
|
||||
|
||||
// rightShiftStage1Idx1Rng4_uid64_rightShiferNoStickyOut_uid39_fpToFxPTest(BITSELECT,63)@1
|
||||
assign rightShiftStage1Idx1Rng4_uid64_rightShiferNoStickyOut_uid39_fpToFxPTest_b = rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_q[32:4];
|
||||
|
||||
// rightShiftStage1Idx1_uid66_rightShiferNoStickyOut_uid39_fpToFxPTest(BITJOIN,65)@1
|
||||
assign rightShiftStage1Idx1_uid66_rightShiferNoStickyOut_uid39_fpToFxPTest_q = {rightShiftStage1Idx1Pad4_uid65_rightShiferNoStickyOut_uid39_fpToFxPTest_q, rightShiftStage1Idx1Rng4_uid64_rightShiferNoStickyOut_uid39_fpToFxPTest_b};
|
||||
|
||||
// rightShiftStage0Idx3_uid61_rightShiferNoStickyOut_uid39_fpToFxPTest(CONSTANT,60)
|
||||
assign rightShiftStage0Idx3_uid61_rightShiferNoStickyOut_uid39_fpToFxPTest_q = 33'b000000000000000000000000000000000;
|
||||
|
||||
// rightShiftStage0Idx2Rng32_uid58_rightShiferNoStickyOut_uid39_fpToFxPTest(BITSELECT,57)@1
|
||||
assign rightShiftStage0Idx2Rng32_uid58_rightShiferNoStickyOut_uid39_fpToFxPTest_b = shifterIn_uid38_fpToFxPTest_q[32:32];
|
||||
|
||||
// rightShiftStage0Idx2_uid60_rightShiferNoStickyOut_uid39_fpToFxPTest(BITJOIN,59)@1
|
||||
assign rightShiftStage0Idx2_uid60_rightShiferNoStickyOut_uid39_fpToFxPTest_q = {maxNegValueU_uid41_fpToFxPTest_q, rightShiftStage0Idx2Rng32_uid58_rightShiferNoStickyOut_uid39_fpToFxPTest_b};
|
||||
|
||||
// rightShiftStage0Idx1Pad16_uid56_rightShiferNoStickyOut_uid39_fpToFxPTest(CONSTANT,55)
|
||||
assign rightShiftStage0Idx1Pad16_uid56_rightShiferNoStickyOut_uid39_fpToFxPTest_q = 16'b0000000000000000;
|
||||
|
||||
// rightShiftStage0Idx1Rng16_uid55_rightShiferNoStickyOut_uid39_fpToFxPTest(BITSELECT,54)@1
|
||||
assign rightShiftStage0Idx1Rng16_uid55_rightShiferNoStickyOut_uid39_fpToFxPTest_b = shifterIn_uid38_fpToFxPTest_q[32:16];
|
||||
|
||||
// rightShiftStage0Idx1_uid57_rightShiferNoStickyOut_uid39_fpToFxPTest(BITJOIN,56)@1
|
||||
assign rightShiftStage0Idx1_uid57_rightShiferNoStickyOut_uid39_fpToFxPTest_q = {rightShiftStage0Idx1Pad16_uid56_rightShiferNoStickyOut_uid39_fpToFxPTest_q, rightShiftStage0Idx1Rng16_uid55_rightShiferNoStickyOut_uid39_fpToFxPTest_b};
|
||||
|
||||
// exp_x_uid9_fpToFxPTest(BITSELECT,8)@0
|
||||
assign exp_x_uid9_fpToFxPTest_b = a[30:23];
|
||||
|
||||
// excZ_x_uid11_fpToFxPTest(LOGICAL,10)@0 + 1
|
||||
assign excZ_x_uid11_fpToFxPTest_qi = exp_x_uid9_fpToFxPTest_b == cstAllZWE_uid8_fpToFxPTest_q ? 1'b1 : 1'b0;
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
|
||||
excZ_x_uid11_fpToFxPTest_delay ( .xin(excZ_x_uid11_fpToFxPTest_qi), .xout(excZ_x_uid11_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// invExcXZ_uid22_fpToFxPTest(LOGICAL,21)@1
|
||||
assign invExcXZ_uid22_fpToFxPTest_q = ~ (excZ_x_uid11_fpToFxPTest_q);
|
||||
|
||||
// frac_x_uid10_fpToFxPTest(BITSELECT,9)@0
|
||||
assign frac_x_uid10_fpToFxPTest_b = a[22:0];
|
||||
|
||||
// redist6_frac_x_uid10_fpToFxPTest_b_1(DELAY,93)
|
||||
dspba_delay_ver #( .width(23), .depth(1), .reset_kind("ASYNC") )
|
||||
redist6_frac_x_uid10_fpToFxPTest_b_1 ( .xin(frac_x_uid10_fpToFxPTest_b), .xout(redist6_frac_x_uid10_fpToFxPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// oFracX_uid23_fpToFxPTest(BITJOIN,22)@1
|
||||
assign oFracX_uid23_fpToFxPTest_q = {invExcXZ_uid22_fpToFxPTest_q, redist6_frac_x_uid10_fpToFxPTest_b_1_q};
|
||||
|
||||
// zPadd_uid37_fpToFxPTest(CONSTANT,36)
|
||||
assign zPadd_uid37_fpToFxPTest_q = 9'b000000000;
|
||||
|
||||
// shifterIn_uid38_fpToFxPTest(BITJOIN,37)@1
|
||||
assign shifterIn_uid38_fpToFxPTest_q = {oFracX_uid23_fpToFxPTest_q, zPadd_uid37_fpToFxPTest_q};
|
||||
|
||||
// rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest(MUX,62)@1
|
||||
assign rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_s = rightShiftStageSel5Dto4_uid62_rightShiferNoStickyOut_uid39_fpToFxPTest_merged_bit_select_b;
|
||||
always @(rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_s or en or shifterIn_uid38_fpToFxPTest_q or rightShiftStage0Idx1_uid57_rightShiferNoStickyOut_uid39_fpToFxPTest_q or rightShiftStage0Idx2_uid60_rightShiferNoStickyOut_uid39_fpToFxPTest_q or rightShiftStage0Idx3_uid61_rightShiferNoStickyOut_uid39_fpToFxPTest_q)
|
||||
begin
|
||||
unique case (rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_s)
|
||||
2'b00 : rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_q = shifterIn_uid38_fpToFxPTest_q;
|
||||
2'b01 : rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_q = rightShiftStage0Idx1_uid57_rightShiferNoStickyOut_uid39_fpToFxPTest_q;
|
||||
2'b10 : rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_q = rightShiftStage0Idx2_uid60_rightShiferNoStickyOut_uid39_fpToFxPTest_q;
|
||||
2'b11 : rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_q = rightShiftStage0Idx3_uid61_rightShiferNoStickyOut_uid39_fpToFxPTest_q;
|
||||
default : rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_q = 33'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest(MUX,73)@1
|
||||
assign rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_s = rightShiftStageSel5Dto4_uid62_rightShiferNoStickyOut_uid39_fpToFxPTest_merged_bit_select_c;
|
||||
always @(rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_s or en or rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_q or rightShiftStage1Idx1_uid66_rightShiferNoStickyOut_uid39_fpToFxPTest_q or rightShiftStage1Idx2_uid69_rightShiferNoStickyOut_uid39_fpToFxPTest_q or rightShiftStage1Idx3_uid72_rightShiferNoStickyOut_uid39_fpToFxPTest_q)
|
||||
begin
|
||||
unique case (rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_s)
|
||||
2'b00 : rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_q = rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_q;
|
||||
2'b01 : rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_q = rightShiftStage1Idx1_uid66_rightShiferNoStickyOut_uid39_fpToFxPTest_q;
|
||||
2'b10 : rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_q = rightShiftStage1Idx2_uid69_rightShiferNoStickyOut_uid39_fpToFxPTest_q;
|
||||
2'b11 : rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_q = rightShiftStage1Idx3_uid72_rightShiferNoStickyOut_uid39_fpToFxPTest_q;
|
||||
default : rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_q = 33'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// maxShiftCst_uid34_fpToFxPTest(CONSTANT,33)
|
||||
assign maxShiftCst_uid34_fpToFxPTest_q = 6'b100001;
|
||||
|
||||
// ovfExpVal_uid31_fpToFxPTest(CONSTANT,30)
|
||||
assign ovfExpVal_uid31_fpToFxPTest_q = 9'b010011110;
|
||||
|
||||
// shiftValE_uid32_fpToFxPTest(SUB,31)@0
|
||||
assign shiftValE_uid32_fpToFxPTest_a = {{2{ovfExpVal_uid31_fpToFxPTest_q[8]}}, ovfExpVal_uid31_fpToFxPTest_q};
|
||||
assign shiftValE_uid32_fpToFxPTest_b = {3'b000, exp_x_uid9_fpToFxPTest_b};
|
||||
assign shiftValE_uid32_fpToFxPTest_o = $signed(shiftValE_uid32_fpToFxPTest_a) - $signed(shiftValE_uid32_fpToFxPTest_b);
|
||||
assign shiftValE_uid32_fpToFxPTest_q = shiftValE_uid32_fpToFxPTest_o[9:0];
|
||||
|
||||
// shiftValRaw_uid33_fpToFxPTest(BITSELECT,32)@0
|
||||
assign shiftValRaw_uid33_fpToFxPTest_in = shiftValE_uid32_fpToFxPTest_q[5:0];
|
||||
assign shiftValRaw_uid33_fpToFxPTest_b = shiftValRaw_uid33_fpToFxPTest_in[5:0];
|
||||
|
||||
// redist1_shiftValRaw_uid33_fpToFxPTest_b_1(DELAY,88)
|
||||
dspba_delay_ver #( .width(6), .depth(1), .reset_kind("ASYNC") )
|
||||
redist1_shiftValRaw_uid33_fpToFxPTest_b_1 ( .xin(shiftValRaw_uid33_fpToFxPTest_b), .xout(redist1_shiftValRaw_uid33_fpToFxPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// shiftOutOfRange_uid35_fpToFxPTest(COMPARE,34)@0 + 1
|
||||
assign shiftOutOfRange_uid35_fpToFxPTest_a = {{2{shiftValE_uid32_fpToFxPTest_q[9]}}, shiftValE_uid32_fpToFxPTest_q};
|
||||
assign shiftOutOfRange_uid35_fpToFxPTest_b = {6'b000000, maxShiftCst_uid34_fpToFxPTest_q};
|
||||
always @ (posedge clk or posedge areset)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
shiftOutOfRange_uid35_fpToFxPTest_o <= 12'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
shiftOutOfRange_uid35_fpToFxPTest_o <= $signed(shiftOutOfRange_uid35_fpToFxPTest_a) - $signed(shiftOutOfRange_uid35_fpToFxPTest_b);
|
||||
end
|
||||
end
|
||||
assign shiftOutOfRange_uid35_fpToFxPTest_n[0] = ~ (shiftOutOfRange_uid35_fpToFxPTest_o[11]);
|
||||
|
||||
// shiftVal_uid36_fpToFxPTest(MUX,35)@1
|
||||
assign shiftVal_uid36_fpToFxPTest_s = shiftOutOfRange_uid35_fpToFxPTest_n;
|
||||
always @(shiftVal_uid36_fpToFxPTest_s or en or redist1_shiftValRaw_uid33_fpToFxPTest_b_1_q or maxShiftCst_uid34_fpToFxPTest_q)
|
||||
begin
|
||||
unique case (shiftVal_uid36_fpToFxPTest_s)
|
||||
1'b0 : shiftVal_uid36_fpToFxPTest_q = redist1_shiftValRaw_uid33_fpToFxPTest_b_1_q;
|
||||
1'b1 : shiftVal_uid36_fpToFxPTest_q = maxShiftCst_uid34_fpToFxPTest_q;
|
||||
default : shiftVal_uid36_fpToFxPTest_q = 6'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// rightShiftStageSel5Dto4_uid62_rightShiferNoStickyOut_uid39_fpToFxPTest_merged_bit_select(BITSELECT,86)@1
|
||||
assign rightShiftStageSel5Dto4_uid62_rightShiferNoStickyOut_uid39_fpToFxPTest_merged_bit_select_b = shiftVal_uid36_fpToFxPTest_q[5:4];
|
||||
assign rightShiftStageSel5Dto4_uid62_rightShiferNoStickyOut_uid39_fpToFxPTest_merged_bit_select_c = shiftVal_uid36_fpToFxPTest_q[3:2];
|
||||
assign rightShiftStageSel5Dto4_uid62_rightShiferNoStickyOut_uid39_fpToFxPTest_merged_bit_select_d = shiftVal_uid36_fpToFxPTest_q[1:0];
|
||||
|
||||
// rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest(MUX,84)@1 + 1
|
||||
assign rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest_s = rightShiftStageSel5Dto4_uid62_rightShiferNoStickyOut_uid39_fpToFxPTest_merged_bit_select_d;
|
||||
always @ (posedge clk or posedge areset)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest_q <= 33'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
unique case (rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest_s)
|
||||
2'b00 : rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest_q <= rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_q;
|
||||
2'b01 : rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest_q <= rightShiftStage2Idx1_uid77_rightShiferNoStickyOut_uid39_fpToFxPTest_q;
|
||||
2'b10 : rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest_q <= rightShiftStage2Idx2_uid80_rightShiferNoStickyOut_uid39_fpToFxPTest_q;
|
||||
2'b11 : rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest_q <= rightShiftStage2Idx3_uid83_rightShiferNoStickyOut_uid39_fpToFxPTest_q;
|
||||
default : rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest_q <= 33'b0;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// zRightShiferNoStickyOut_uid43_fpToFxPTest(BITJOIN,42)@2
|
||||
assign zRightShiferNoStickyOut_uid43_fpToFxPTest_q = {GND_q, rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest_q};
|
||||
|
||||
// sPostRndFull_uid44_fpToFxPTest(ADD,43)@2
|
||||
assign sPostRndFull_uid44_fpToFxPTest_a = {1'b0, zRightShiferNoStickyOut_uid43_fpToFxPTest_q};
|
||||
assign sPostRndFull_uid44_fpToFxPTest_b = {34'b0000000000000000000000000000000000, VCC_q};
|
||||
assign sPostRndFull_uid44_fpToFxPTest_o = $unsigned(sPostRndFull_uid44_fpToFxPTest_a) + $unsigned(sPostRndFull_uid44_fpToFxPTest_b);
|
||||
assign sPostRndFull_uid44_fpToFxPTest_q = sPostRndFull_uid44_fpToFxPTest_o[34:0];
|
||||
|
||||
// sPostRnd_uid45_fpToFxPTest(BITSELECT,44)@2
|
||||
assign sPostRnd_uid45_fpToFxPTest_in = sPostRndFull_uid44_fpToFxPTest_q[32:0];
|
||||
assign sPostRnd_uid45_fpToFxPTest_b = sPostRnd_uid45_fpToFxPTest_in[32:1];
|
||||
|
||||
// redist0_sPostRnd_uid45_fpToFxPTest_b_1(DELAY,87)
|
||||
dspba_delay_ver #( .width(32), .depth(1), .reset_kind("ASYNC") )
|
||||
redist0_sPostRnd_uid45_fpToFxPTest_b_1 ( .xin(sPostRnd_uid45_fpToFxPTest_b), .xout(redist0_sPostRnd_uid45_fpToFxPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// signX_uid25_fpToFxPTest(BITSELECT,24)@0
|
||||
assign signX_uid25_fpToFxPTest_b = a[31:31];
|
||||
|
||||
// redist4_signX_uid25_fpToFxPTest_b_2(DELAY,91)
|
||||
dspba_delay_ver #( .width(1), .depth(2), .reset_kind("ASYNC") )
|
||||
redist4_signX_uid25_fpToFxPTest_b_2 ( .xin(signX_uid25_fpToFxPTest_b), .xout(redist4_signX_uid25_fpToFxPTest_b_2_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// udfExpVal_uid29_fpToFxPTest(CONSTANT,28)
|
||||
assign udfExpVal_uid29_fpToFxPTest_q = 8'b01111101;
|
||||
|
||||
// udf_uid30_fpToFxPTest(COMPARE,29)@0 + 1
|
||||
assign udf_uid30_fpToFxPTest_a = {{3{udfExpVal_uid29_fpToFxPTest_q[7]}}, udfExpVal_uid29_fpToFxPTest_q};
|
||||
assign udf_uid30_fpToFxPTest_b = {3'b000, exp_x_uid9_fpToFxPTest_b};
|
||||
always @ (posedge clk or posedge areset)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
udf_uid30_fpToFxPTest_o <= 11'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
udf_uid30_fpToFxPTest_o <= $signed(udf_uid30_fpToFxPTest_a) - $signed(udf_uid30_fpToFxPTest_b);
|
||||
end
|
||||
end
|
||||
assign udf_uid30_fpToFxPTest_n[0] = ~ (udf_uid30_fpToFxPTest_o[10]);
|
||||
|
||||
// redist2_udf_uid30_fpToFxPTest_n_2(DELAY,89)
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
|
||||
redist2_udf_uid30_fpToFxPTest_n_2 ( .xin(udf_uid30_fpToFxPTest_n), .xout(redist2_udf_uid30_fpToFxPTest_n_2_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// sPostRndFullMSBU_uid46_fpToFxPTest(BITSELECT,45)@2
|
||||
assign sPostRndFullMSBU_uid46_fpToFxPTest_in = sPostRndFull_uid44_fpToFxPTest_q[33:0];
|
||||
assign sPostRndFullMSBU_uid46_fpToFxPTest_b = sPostRndFullMSBU_uid46_fpToFxPTest_in[33:33];
|
||||
|
||||
// ovfExpVal_uid26_fpToFxPTest(CONSTANT,25)
|
||||
assign ovfExpVal_uid26_fpToFxPTest_q = 9'b010011111;
|
||||
|
||||
// ovf_uid27_fpToFxPTest(COMPARE,26)@0 + 1
|
||||
assign ovf_uid27_fpToFxPTest_a = {3'b000, exp_x_uid9_fpToFxPTest_b};
|
||||
assign ovf_uid27_fpToFxPTest_b = {{2{ovfExpVal_uid26_fpToFxPTest_q[8]}}, ovfExpVal_uid26_fpToFxPTest_q};
|
||||
always @ (posedge clk or posedge areset)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
ovf_uid27_fpToFxPTest_o <= 11'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
ovf_uid27_fpToFxPTest_o <= $signed(ovf_uid27_fpToFxPTest_a) - $signed(ovf_uid27_fpToFxPTest_b);
|
||||
end
|
||||
end
|
||||
assign ovf_uid27_fpToFxPTest_n[0] = ~ (ovf_uid27_fpToFxPTest_o[10]);
|
||||
|
||||
// redist3_ovf_uid27_fpToFxPTest_n_2(DELAY,90)
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
|
||||
redist3_ovf_uid27_fpToFxPTest_n_2 ( .xin(ovf_uid27_fpToFxPTest_n), .xout(redist3_ovf_uid27_fpToFxPTest_n_2_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// negOrOvf_uid28_fpToFxPTest(LOGICAL,27)@2
|
||||
assign negOrOvf_uid28_fpToFxPTest_q = redist4_signX_uid25_fpToFxPTest_b_2_q | redist3_ovf_uid27_fpToFxPTest_n_2_q;
|
||||
|
||||
// cstZeroWF_uid7_fpToFxPTest(CONSTANT,6)
|
||||
assign cstZeroWF_uid7_fpToFxPTest_q = 23'b00000000000000000000000;
|
||||
|
||||
// fracXIsZero_uid13_fpToFxPTest(LOGICAL,12)@1 + 1
|
||||
assign fracXIsZero_uid13_fpToFxPTest_qi = cstZeroWF_uid7_fpToFxPTest_q == redist6_frac_x_uid10_fpToFxPTest_b_1_q ? 1'b1 : 1'b0;
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
|
||||
fracXIsZero_uid13_fpToFxPTest_delay ( .xin(fracXIsZero_uid13_fpToFxPTest_qi), .xout(fracXIsZero_uid13_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// cstAllOWE_uid6_fpToFxPTest(CONSTANT,5)
|
||||
assign cstAllOWE_uid6_fpToFxPTest_q = 8'b11111111;
|
||||
|
||||
// expXIsMax_uid12_fpToFxPTest(LOGICAL,11)@0 + 1
|
||||
assign expXIsMax_uid12_fpToFxPTest_qi = exp_x_uid9_fpToFxPTest_b == cstAllOWE_uid6_fpToFxPTest_q ? 1'b1 : 1'b0;
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
|
||||
expXIsMax_uid12_fpToFxPTest_delay ( .xin(expXIsMax_uid12_fpToFxPTest_qi), .xout(expXIsMax_uid12_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// redist5_expXIsMax_uid12_fpToFxPTest_q_2(DELAY,92)
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
|
||||
redist5_expXIsMax_uid12_fpToFxPTest_q_2 ( .xin(expXIsMax_uid12_fpToFxPTest_q), .xout(redist5_expXIsMax_uid12_fpToFxPTest_q_2_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// excI_x_uid15_fpToFxPTest(LOGICAL,14)@2
|
||||
assign excI_x_uid15_fpToFxPTest_q = redist5_expXIsMax_uid12_fpToFxPTest_q_2_q & fracXIsZero_uid13_fpToFxPTest_q;
|
||||
|
||||
// fracXIsNotZero_uid14_fpToFxPTest(LOGICAL,13)@2
|
||||
assign fracXIsNotZero_uid14_fpToFxPTest_q = ~ (fracXIsZero_uid13_fpToFxPTest_q);
|
||||
|
||||
// excN_x_uid16_fpToFxPTest(LOGICAL,15)@2
|
||||
assign excN_x_uid16_fpToFxPTest_q = redist5_expXIsMax_uid12_fpToFxPTest_q_2_q & fracXIsNotZero_uid14_fpToFxPTest_q;
|
||||
|
||||
// ovfPostRnd_uid47_fpToFxPTest(LOGICAL,46)@2
|
||||
assign ovfPostRnd_uid47_fpToFxPTest_q = excN_x_uid16_fpToFxPTest_q | excI_x_uid15_fpToFxPTest_q | negOrOvf_uid28_fpToFxPTest_q | sPostRndFullMSBU_uid46_fpToFxPTest_b;
|
||||
|
||||
// muxSelConc_uid48_fpToFxPTest(BITJOIN,47)@2
|
||||
assign muxSelConc_uid48_fpToFxPTest_q = {redist4_signX_uid25_fpToFxPTest_b_2_q, redist2_udf_uid30_fpToFxPTest_n_2_q, ovfPostRnd_uid47_fpToFxPTest_q};
|
||||
|
||||
// muxSel_uid49_fpToFxPTest(LOOKUP,48)@2 + 1
|
||||
always @ (posedge clk or posedge areset)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
muxSel_uid49_fpToFxPTest_q <= 2'b00;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
unique case (muxSelConc_uid48_fpToFxPTest_q)
|
||||
3'b000 : muxSel_uid49_fpToFxPTest_q <= 2'b00;
|
||||
3'b001 : muxSel_uid49_fpToFxPTest_q <= 2'b01;
|
||||
3'b010 : muxSel_uid49_fpToFxPTest_q <= 2'b11;
|
||||
3'b011 : muxSel_uid49_fpToFxPTest_q <= 2'b00;
|
||||
3'b100 : muxSel_uid49_fpToFxPTest_q <= 2'b10;
|
||||
3'b101 : muxSel_uid49_fpToFxPTest_q <= 2'b10;
|
||||
3'b110 : muxSel_uid49_fpToFxPTest_q <= 2'b10;
|
||||
3'b111 : muxSel_uid49_fpToFxPTest_q <= 2'b10;
|
||||
default : begin
|
||||
// unreachable
|
||||
muxSel_uid49_fpToFxPTest_q <= 2'bxx;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// finalOut_uid51_fpToFxPTest(MUX,50)@3
|
||||
assign finalOut_uid51_fpToFxPTest_s = muxSel_uid49_fpToFxPTest_q;
|
||||
always @(finalOut_uid51_fpToFxPTest_s or en or redist0_sPostRnd_uid45_fpToFxPTest_b_1_q or maxPosValueU_uid40_fpToFxPTest_q or maxNegValueU_uid41_fpToFxPTest_q)
|
||||
begin
|
||||
unique case (finalOut_uid51_fpToFxPTest_s)
|
||||
2'b00 : finalOut_uid51_fpToFxPTest_q = redist0_sPostRnd_uid45_fpToFxPTest_b_1_q;
|
||||
2'b01 : finalOut_uid51_fpToFxPTest_q = maxPosValueU_uid40_fpToFxPTest_q;
|
||||
2'b10 : finalOut_uid51_fpToFxPTest_q = maxNegValueU_uid41_fpToFxPTest_q;
|
||||
2'b11 : finalOut_uid51_fpToFxPTest_q = maxNegValueU_uid41_fpToFxPTest_q;
|
||||
default : finalOut_uid51_fpToFxPTest_q = 32'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// xOut(GPOUT,4)@3
|
||||
assign q = finalOut_uid51_fpToFxPTest_q;
|
||||
|
||||
endmodule
|
||||
@@ -18,13 +18,16 @@ FBITS="f$(($EXP_BITS + $MAN_BITS + 1))"
|
||||
|
||||
echo Generating IP cores for $FBITS
|
||||
{
|
||||
#$CMD -name "$PREFIX"_fadd -frequency 250 FPAdd $EXP_BITS $MAN_BITS
|
||||
#$CMD -name "$PREFIX"_fsub -frequency 250 FPSub $EXP_BITS $MAN_BITS
|
||||
#$CMD -name "$PREFIX"_fmul -frequency 250 FPMul $EXP_BITS $MAN_BITS
|
||||
$CMD -name "$PREFIX"_fmadd -frequency 250 FPMultAdd $EXP_BITS $MAN_BITS
|
||||
$CMD -name "$PREFIX"_fdiv -frequency 250 FPDiv $EXP_BITS $MAN_BITS 0
|
||||
$CMD -name "$PREFIX"_fsqrt -frequency 250 FPSqrt $EXP_BITS $MAN_BITS
|
||||
$CMD -name "$PREFIX"_ftoi -frequency 250 FPToFXP $EXP_BITS $MAN_BITS 32 0 1
|
||||
$CMD -name "$PREFIX"_ftou -frequency 250 FPToFXP $EXP_BITS $MAN_BITS 32 0 0
|
||||
$CMD -name "$PREFIX"_itof -frequency 250 FXPToFP 32 0 1 $EXP_BITS $MAN_BITS
|
||||
$CMD -name "$PREFIX"_utof -frequency 300 FXPToFP 32 0 0 $EXP_BITS $MAN_BITS
|
||||
#$CMD -name "$PREFIX"_ftoi -frequency 250 FPToFXP $EXP_BITS $MAN_BITS 32 0 1
|
||||
#$CMD -name "$PREFIX"_ftou -frequency 250 FPToFXP $EXP_BITS $MAN_BITS 32 0 0
|
||||
#$CMD -name "$PREFIX"_itof -frequency 250 FXPToFP 32 0 1 $EXP_BITS $MAN_BITS
|
||||
#$CMD -name "$PREFIX"_utof -frequency 300 FXPToFP 32 0 0 $EXP_BITS $MAN_BITS
|
||||
} > acl_gen.log 2>&1
|
||||
|
||||
#cp $QUARTUS_HOME/dspba/backend/Libraries/sv/base/dspba_library_ver.sv .
|
||||
@@ -1,520 +0,0 @@
|
||||
// -------------------------------------------------------------------------
|
||||
// High Level Design Compiler for Intel(R) FPGAs Version 17.1 (Release Build #273)
|
||||
// Quartus Prime development tool and MATLAB/Simulink Interface
|
||||
//
|
||||
// Legal Notice: Copyright 2017 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly
|
||||
// subject to the terms and conditions of the Intel FPGA Software License
|
||||
// Agreement, Intel MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for
|
||||
// the sole purpose of programming logic devices manufactured by Intel
|
||||
// and sold by Intel or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
// ---------------------------------------------------------------------------
|
||||
|
||||
// SystemVerilog created from acl_itof
|
||||
// SystemVerilog created on Sun Dec 27 09:47:21 2020
|
||||
|
||||
|
||||
(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
|
||||
module acl_itof (
|
||||
input wire [31:0] a,
|
||||
input wire [0:0] en,
|
||||
output wire [31:0] q,
|
||||
input wire clk,
|
||||
input wire areset
|
||||
);
|
||||
|
||||
wire [0:0] GND_q;
|
||||
wire [0:0] signX_uid6_fxpToFPTest_b;
|
||||
wire [31:0] xXorSign_uid7_fxpToFPTest_b;
|
||||
wire [31:0] xXorSign_uid7_fxpToFPTest_qi;
|
||||
reg [31:0] xXorSign_uid7_fxpToFPTest_q;
|
||||
wire [32:0] yE_uid8_fxpToFPTest_a;
|
||||
wire [32:0] yE_uid8_fxpToFPTest_b;
|
||||
logic [32:0] yE_uid8_fxpToFPTest_o;
|
||||
wire [32:0] yE_uid8_fxpToFPTest_q;
|
||||
wire [31:0] y_uid9_fxpToFPTest_in;
|
||||
wire [31:0] y_uid9_fxpToFPTest_b;
|
||||
wire [5:0] maxCount_uid11_fxpToFPTest_q;
|
||||
wire [0:0] inIsZero_uid12_fxpToFPTest_qi;
|
||||
reg [0:0] inIsZero_uid12_fxpToFPTest_q;
|
||||
wire [7:0] msbIn_uid13_fxpToFPTest_q;
|
||||
wire [8:0] expPreRnd_uid14_fxpToFPTest_a;
|
||||
wire [8:0] expPreRnd_uid14_fxpToFPTest_b;
|
||||
logic [8:0] expPreRnd_uid14_fxpToFPTest_o;
|
||||
wire [8:0] expPreRnd_uid14_fxpToFPTest_q;
|
||||
wire [32:0] expFracRnd_uid16_fxpToFPTest_q;
|
||||
wire [0:0] sticky_uid20_fxpToFPTest_qi;
|
||||
reg [0:0] sticky_uid20_fxpToFPTest_q;
|
||||
wire [0:0] nr_uid21_fxpToFPTest_q;
|
||||
wire [0:0] rnd_uid22_fxpToFPTest_q;
|
||||
wire [34:0] expFracR_uid24_fxpToFPTest_a;
|
||||
wire [34:0] expFracR_uid24_fxpToFPTest_b;
|
||||
logic [34:0] expFracR_uid24_fxpToFPTest_o;
|
||||
wire [33:0] expFracR_uid24_fxpToFPTest_q;
|
||||
wire [23:0] fracR_uid25_fxpToFPTest_in;
|
||||
wire [22:0] fracR_uid25_fxpToFPTest_b;
|
||||
wire [9:0] expR_uid26_fxpToFPTest_b;
|
||||
wire [11:0] udf_uid27_fxpToFPTest_a;
|
||||
wire [11:0] udf_uid27_fxpToFPTest_b;
|
||||
logic [11:0] udf_uid27_fxpToFPTest_o;
|
||||
wire [0:0] udf_uid27_fxpToFPTest_n;
|
||||
wire [7:0] expInf_uid28_fxpToFPTest_q;
|
||||
wire [11:0] ovf_uid29_fxpToFPTest_a;
|
||||
wire [11:0] ovf_uid29_fxpToFPTest_b;
|
||||
logic [11:0] ovf_uid29_fxpToFPTest_o;
|
||||
wire [0:0] ovf_uid29_fxpToFPTest_n;
|
||||
wire [0:0] excSelector_uid30_fxpToFPTest_q;
|
||||
wire [22:0] fracZ_uid31_fxpToFPTest_q;
|
||||
wire [0:0] fracRPostExc_uid32_fxpToFPTest_s;
|
||||
reg [22:0] fracRPostExc_uid32_fxpToFPTest_q;
|
||||
wire [0:0] udfOrInZero_uid33_fxpToFPTest_q;
|
||||
wire [1:0] excSelector_uid34_fxpToFPTest_q;
|
||||
wire [7:0] expZ_uid37_fxpToFPTest_q;
|
||||
wire [7:0] expR_uid38_fxpToFPTest_in;
|
||||
wire [7:0] expR_uid38_fxpToFPTest_b;
|
||||
wire [1:0] expRPostExc_uid39_fxpToFPTest_s;
|
||||
reg [7:0] expRPostExc_uid39_fxpToFPTest_q;
|
||||
wire [31:0] outRes_uid40_fxpToFPTest_q;
|
||||
wire [31:0] zs_uid42_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [0:0] vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_qi;
|
||||
reg [0:0] vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [0:0] vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_s;
|
||||
reg [31:0] vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [15:0] zs_uid47_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [0:0] vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [31:0] cStage_uid52_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [0:0] vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_s;
|
||||
reg [31:0] vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [0:0] vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [31:0] cStage_uid59_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [0:0] vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_s;
|
||||
reg [31:0] vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [3:0] zs_uid61_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [0:0] vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [31:0] cStage_uid66_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [0:0] vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_s;
|
||||
reg [31:0] vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [1:0] zs_uid68_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [0:0] vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [31:0] cStage_uid73_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [0:0] vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_s;
|
||||
reg [31:0] vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [0:0] vCount_uid77_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [31:0] cStage_uid80_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [0:0] vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_s;
|
||||
reg [31:0] vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [5:0] vCount_uid82_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [7:0] vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_a;
|
||||
wire [7:0] vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_b;
|
||||
logic [7:0] vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_o;
|
||||
wire [0:0] vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_c;
|
||||
wire [0:0] vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_s;
|
||||
reg [5:0] vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [1:0] l_uid17_fxpToFPTest_merged_bit_select_in;
|
||||
wire [0:0] l_uid17_fxpToFPTest_merged_bit_select_b;
|
||||
wire [0:0] l_uid17_fxpToFPTest_merged_bit_select_c;
|
||||
wire [15:0] rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b;
|
||||
wire [15:0] rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c;
|
||||
wire [7:0] rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b;
|
||||
wire [23:0] rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c;
|
||||
wire [3:0] rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b;
|
||||
wire [27:0] rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c;
|
||||
wire [1:0] rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b;
|
||||
wire [29:0] rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c;
|
||||
wire [0:0] rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b;
|
||||
wire [30:0] rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c;
|
||||
wire [30:0] fracRnd_uid15_fxpToFPTest_merged_bit_select_in;
|
||||
wire [23:0] fracRnd_uid15_fxpToFPTest_merged_bit_select_b;
|
||||
wire [6:0] fracRnd_uid15_fxpToFPTest_merged_bit_select_c;
|
||||
reg [23:0] redist0_fracRnd_uid15_fxpToFPTest_merged_bit_select_b_2_q;
|
||||
reg [0:0] redist1_vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q_1_q;
|
||||
reg [0:0] redist2_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_1_q;
|
||||
reg [0:0] redist3_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_2_q;
|
||||
reg [0:0] redist4_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_3_q;
|
||||
reg [9:0] redist5_expR_uid26_fxpToFPTest_b_1_q;
|
||||
reg [22:0] redist6_fracR_uid25_fxpToFPTest_b_1_q;
|
||||
reg [0:0] redist7_sticky_uid20_fxpToFPTest_q_2_q;
|
||||
reg [0:0] redist8_inIsZero_uid12_fxpToFPTest_q_2_q;
|
||||
reg [31:0] redist9_y_uid9_fxpToFPTest_b_1_q;
|
||||
reg [0:0] redist10_signX_uid6_fxpToFPTest_b_1_q;
|
||||
reg [0:0] redist11_signX_uid6_fxpToFPTest_b_7_q;
|
||||
|
||||
|
||||
// signX_uid6_fxpToFPTest(BITSELECT,5)@0
|
||||
assign signX_uid6_fxpToFPTest_b = a[31:31];
|
||||
|
||||
// redist10_signX_uid6_fxpToFPTest_b_1(DELAY,105)
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
|
||||
redist10_signX_uid6_fxpToFPTest_b_1 ( .xin(signX_uid6_fxpToFPTest_b), .xout(redist10_signX_uid6_fxpToFPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// redist11_signX_uid6_fxpToFPTest_b_7(DELAY,106)
|
||||
dspba_delay_ver #( .width(1), .depth(6), .reset_kind("ASYNC") )
|
||||
redist11_signX_uid6_fxpToFPTest_b_7 ( .xin(redist10_signX_uid6_fxpToFPTest_b_1_q), .xout(redist11_signX_uid6_fxpToFPTest_b_7_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// expInf_uid28_fxpToFPTest(CONSTANT,27)
|
||||
assign expInf_uid28_fxpToFPTest_q = 8'b11111111;
|
||||
|
||||
// expZ_uid37_fxpToFPTest(CONSTANT,36)
|
||||
assign expZ_uid37_fxpToFPTest_q = 8'b00000000;
|
||||
|
||||
// rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select(BITSELECT,93)@4
|
||||
assign rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b = vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q[31:31];
|
||||
assign rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c = vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q[30:0];
|
||||
|
||||
// GND(CONSTANT,0)
|
||||
assign GND_q = 1'b0;
|
||||
|
||||
// cStage_uid80_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,79)@4
|
||||
assign cStage_uid80_lzcShifterZ1_uid10_fxpToFPTest_q = {rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c, GND_q};
|
||||
|
||||
// rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select(BITSELECT,92)@4
|
||||
assign rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b = vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q[31:30];
|
||||
assign rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c = vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q[29:0];
|
||||
|
||||
// zs_uid68_lzcShifterZ1_uid10_fxpToFPTest(CONSTANT,67)
|
||||
assign zs_uid68_lzcShifterZ1_uid10_fxpToFPTest_q = 2'b00;
|
||||
|
||||
// cStage_uid73_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,72)@4
|
||||
assign cStage_uid73_lzcShifterZ1_uid10_fxpToFPTest_q = {rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c, zs_uid68_lzcShifterZ1_uid10_fxpToFPTest_q};
|
||||
|
||||
// rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select(BITSELECT,91)@3
|
||||
assign rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b = vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q[31:28];
|
||||
assign rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c = vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q[27:0];
|
||||
|
||||
// zs_uid61_lzcShifterZ1_uid10_fxpToFPTest(CONSTANT,60)
|
||||
assign zs_uid61_lzcShifterZ1_uid10_fxpToFPTest_q = 4'b0000;
|
||||
|
||||
// cStage_uid66_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,65)@3
|
||||
assign cStage_uid66_lzcShifterZ1_uid10_fxpToFPTest_q = {rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c, zs_uid61_lzcShifterZ1_uid10_fxpToFPTest_q};
|
||||
|
||||
// rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select(BITSELECT,90)@3
|
||||
assign rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b = vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q[31:24];
|
||||
assign rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c = vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q[23:0];
|
||||
|
||||
// cStage_uid59_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,58)@3
|
||||
assign cStage_uid59_lzcShifterZ1_uid10_fxpToFPTest_q = {rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c, expZ_uid37_fxpToFPTest_q};
|
||||
|
||||
// rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select(BITSELECT,89)@2
|
||||
assign rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b = vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q[31:16];
|
||||
assign rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c = vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q[15:0];
|
||||
|
||||
// zs_uid47_lzcShifterZ1_uid10_fxpToFPTest(CONSTANT,46)
|
||||
assign zs_uid47_lzcShifterZ1_uid10_fxpToFPTest_q = 16'b0000000000000000;
|
||||
|
||||
// cStage_uid52_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,51)@2
|
||||
assign cStage_uid52_lzcShifterZ1_uid10_fxpToFPTest_q = {rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c, zs_uid47_lzcShifterZ1_uid10_fxpToFPTest_q};
|
||||
|
||||
// zs_uid42_lzcShifterZ1_uid10_fxpToFPTest(CONSTANT,41)
|
||||
assign zs_uid42_lzcShifterZ1_uid10_fxpToFPTest_q = 32'b00000000000000000000000000000000;
|
||||
|
||||
// xXorSign_uid7_fxpToFPTest(LOGICAL,6)@0 + 1
|
||||
assign xXorSign_uid7_fxpToFPTest_b = {{31{signX_uid6_fxpToFPTest_b[0]}}, signX_uid6_fxpToFPTest_b};
|
||||
assign xXorSign_uid7_fxpToFPTest_qi = a ^ xXorSign_uid7_fxpToFPTest_b;
|
||||
dspba_delay_ver #( .width(32), .depth(1), .reset_kind("ASYNC") )
|
||||
xXorSign_uid7_fxpToFPTest_delay ( .xin(xXorSign_uid7_fxpToFPTest_qi), .xout(xXorSign_uid7_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// yE_uid8_fxpToFPTest(ADD,7)@1
|
||||
assign yE_uid8_fxpToFPTest_a = {1'b0, xXorSign_uid7_fxpToFPTest_q};
|
||||
assign yE_uid8_fxpToFPTest_b = {32'b00000000000000000000000000000000, redist10_signX_uid6_fxpToFPTest_b_1_q};
|
||||
assign yE_uid8_fxpToFPTest_o = $unsigned(yE_uid8_fxpToFPTest_a) + $unsigned(yE_uid8_fxpToFPTest_b);
|
||||
assign yE_uid8_fxpToFPTest_q = yE_uid8_fxpToFPTest_o[32:0];
|
||||
|
||||
// y_uid9_fxpToFPTest(BITSELECT,8)@1
|
||||
assign y_uid9_fxpToFPTest_in = yE_uid8_fxpToFPTest_q[31:0];
|
||||
assign y_uid9_fxpToFPTest_b = y_uid9_fxpToFPTest_in[31:0];
|
||||
|
||||
// redist9_y_uid9_fxpToFPTest_b_1(DELAY,104)
|
||||
dspba_delay_ver #( .width(32), .depth(1), .reset_kind("ASYNC") )
|
||||
redist9_y_uid9_fxpToFPTest_b_1 ( .xin(y_uid9_fxpToFPTest_b), .xout(redist9_y_uid9_fxpToFPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,43)@1 + 1
|
||||
assign vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_qi = y_uid9_fxpToFPTest_b == zs_uid42_lzcShifterZ1_uid10_fxpToFPTest_q ? 1'b1 : 1'b0;
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
|
||||
vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_delay ( .xin(vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_qi), .xout(vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest(MUX,45)@2
|
||||
assign vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_s = vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
always @(vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_s or en or redist9_y_uid9_fxpToFPTest_b_1_q or zs_uid42_lzcShifterZ1_uid10_fxpToFPTest_q)
|
||||
begin
|
||||
unique case (vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_s)
|
||||
1'b0 : vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q = redist9_y_uid9_fxpToFPTest_b_1_q;
|
||||
1'b1 : vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q = zs_uid42_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
default : vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q = 32'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,48)@2
|
||||
assign vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q = rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b == zs_uid47_lzcShifterZ1_uid10_fxpToFPTest_q ? 1'b1 : 1'b0;
|
||||
|
||||
// vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest(MUX,52)@2 + 1
|
||||
assign vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_s = vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
always @ (posedge clk or posedge areset)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q <= 32'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
unique case (vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_s)
|
||||
1'b0 : vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q <= vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
1'b1 : vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q <= cStage_uid52_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
default : vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q <= 32'b0;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,55)@3
|
||||
assign vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q = rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b == expZ_uid37_fxpToFPTest_q ? 1'b1 : 1'b0;
|
||||
|
||||
// vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest(MUX,59)@3
|
||||
assign vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_s = vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
always @(vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_s or en or vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q or cStage_uid59_lzcShifterZ1_uid10_fxpToFPTest_q)
|
||||
begin
|
||||
unique case (vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_s)
|
||||
1'b0 : vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q = vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
1'b1 : vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q = cStage_uid59_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
default : vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q = 32'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,62)@3
|
||||
assign vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q = rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b == zs_uid61_lzcShifterZ1_uid10_fxpToFPTest_q ? 1'b1 : 1'b0;
|
||||
|
||||
// vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest(MUX,66)@3 + 1
|
||||
assign vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_s = vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
always @ (posedge clk or posedge areset)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q <= 32'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
unique case (vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_s)
|
||||
1'b0 : vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q <= vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
1'b1 : vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q <= cStage_uid66_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
default : vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q <= 32'b0;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,69)@4
|
||||
assign vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q = rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b == zs_uid68_lzcShifterZ1_uid10_fxpToFPTest_q ? 1'b1 : 1'b0;
|
||||
|
||||
// vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest(MUX,73)@4
|
||||
assign vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_s = vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
always @(vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_s or en or vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q or cStage_uid73_lzcShifterZ1_uid10_fxpToFPTest_q)
|
||||
begin
|
||||
unique case (vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_s)
|
||||
1'b0 : vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q = vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
1'b1 : vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q = cStage_uid73_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
default : vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q = 32'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// vCount_uid77_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,76)@4
|
||||
assign vCount_uid77_lzcShifterZ1_uid10_fxpToFPTest_q = rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b == GND_q ? 1'b1 : 1'b0;
|
||||
|
||||
// vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest(MUX,80)@4
|
||||
assign vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_s = vCount_uid77_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
always @(vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_s or en or vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q or cStage_uid80_lzcShifterZ1_uid10_fxpToFPTest_q)
|
||||
begin
|
||||
unique case (vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_s)
|
||||
1'b0 : vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_q = vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
1'b1 : vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_q = cStage_uid80_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
default : vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_q = 32'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// fracRnd_uid15_fxpToFPTest_merged_bit_select(BITSELECT,94)@4
|
||||
assign fracRnd_uid15_fxpToFPTest_merged_bit_select_in = vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_q[30:0];
|
||||
assign fracRnd_uid15_fxpToFPTest_merged_bit_select_b = fracRnd_uid15_fxpToFPTest_merged_bit_select_in[30:7];
|
||||
assign fracRnd_uid15_fxpToFPTest_merged_bit_select_c = fracRnd_uid15_fxpToFPTest_merged_bit_select_in[6:0];
|
||||
|
||||
// sticky_uid20_fxpToFPTest(LOGICAL,19)@4 + 1
|
||||
assign sticky_uid20_fxpToFPTest_qi = fracRnd_uid15_fxpToFPTest_merged_bit_select_c != 7'b0000000 ? 1'b1 : 1'b0;
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
|
||||
sticky_uid20_fxpToFPTest_delay ( .xin(sticky_uid20_fxpToFPTest_qi), .xout(sticky_uid20_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// redist7_sticky_uid20_fxpToFPTest_q_2(DELAY,102)
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
|
||||
redist7_sticky_uid20_fxpToFPTest_q_2 ( .xin(sticky_uid20_fxpToFPTest_q), .xout(redist7_sticky_uid20_fxpToFPTest_q_2_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// nr_uid21_fxpToFPTest(LOGICAL,20)@6
|
||||
assign nr_uid21_fxpToFPTest_q = ~ (l_uid17_fxpToFPTest_merged_bit_select_c);
|
||||
|
||||
// l_uid17_fxpToFPTest_merged_bit_select(BITSELECT,88)@6
|
||||
assign l_uid17_fxpToFPTest_merged_bit_select_in = expFracRnd_uid16_fxpToFPTest_q[1:0];
|
||||
assign l_uid17_fxpToFPTest_merged_bit_select_b = l_uid17_fxpToFPTest_merged_bit_select_in[1:1];
|
||||
assign l_uid17_fxpToFPTest_merged_bit_select_c = l_uid17_fxpToFPTest_merged_bit_select_in[0:0];
|
||||
|
||||
// rnd_uid22_fxpToFPTest(LOGICAL,21)@6
|
||||
assign rnd_uid22_fxpToFPTest_q = l_uid17_fxpToFPTest_merged_bit_select_b | nr_uid21_fxpToFPTest_q | redist7_sticky_uid20_fxpToFPTest_q_2_q;
|
||||
|
||||
// maxCount_uid11_fxpToFPTest(CONSTANT,10)
|
||||
assign maxCount_uid11_fxpToFPTest_q = 6'b100000;
|
||||
|
||||
// redist4_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_3(DELAY,99)
|
||||
dspba_delay_ver #( .width(1), .depth(2), .reset_kind("ASYNC") )
|
||||
redist4_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_3 ( .xin(vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q), .xout(redist4_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_3_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// redist3_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_2(DELAY,98)
|
||||
dspba_delay_ver #( .width(1), .depth(2), .reset_kind("ASYNC") )
|
||||
redist3_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_2 ( .xin(vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q), .xout(redist3_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_2_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// redist2_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_1(DELAY,97)
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
|
||||
redist2_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_1 ( .xin(vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q), .xout(redist2_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_1_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// redist1_vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q_1(DELAY,96)
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
|
||||
redist1_vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q_1 ( .xin(vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q), .xout(redist1_vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q_1_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// vCount_uid82_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,81)@4
|
||||
assign vCount_uid82_lzcShifterZ1_uid10_fxpToFPTest_q = {redist4_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_3_q, redist3_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_2_q, redist2_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_1_q, redist1_vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q_1_q, vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q, vCount_uid77_lzcShifterZ1_uid10_fxpToFPTest_q};
|
||||
|
||||
// vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest(COMPARE,83)@4
|
||||
assign vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_a = {2'b00, maxCount_uid11_fxpToFPTest_q};
|
||||
assign vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_b = {2'b00, vCount_uid82_lzcShifterZ1_uid10_fxpToFPTest_q};
|
||||
assign vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_o = $unsigned(vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_a) - $unsigned(vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_b);
|
||||
assign vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_c[0] = vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_o[7];
|
||||
|
||||
// vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest(MUX,85)@4 + 1
|
||||
assign vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_s = vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_c;
|
||||
always @ (posedge clk or posedge areset)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q <= 6'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
unique case (vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_s)
|
||||
1'b0 : vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q <= vCount_uid82_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
1'b1 : vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q <= maxCount_uid11_fxpToFPTest_q;
|
||||
default : vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q <= 6'b0;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// msbIn_uid13_fxpToFPTest(CONSTANT,12)
|
||||
assign msbIn_uid13_fxpToFPTest_q = 8'b10011110;
|
||||
|
||||
// expPreRnd_uid14_fxpToFPTest(SUB,13)@5 + 1
|
||||
assign expPreRnd_uid14_fxpToFPTest_a = {1'b0, msbIn_uid13_fxpToFPTest_q};
|
||||
assign expPreRnd_uid14_fxpToFPTest_b = {3'b000, vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q};
|
||||
always @ (posedge clk or posedge areset)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
expPreRnd_uid14_fxpToFPTest_o <= 9'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
expPreRnd_uid14_fxpToFPTest_o <= $unsigned(expPreRnd_uid14_fxpToFPTest_a) - $unsigned(expPreRnd_uid14_fxpToFPTest_b);
|
||||
end
|
||||
end
|
||||
assign expPreRnd_uid14_fxpToFPTest_q = expPreRnd_uid14_fxpToFPTest_o[8:0];
|
||||
|
||||
// redist0_fracRnd_uid15_fxpToFPTest_merged_bit_select_b_2(DELAY,95)
|
||||
dspba_delay_ver #( .width(24), .depth(2), .reset_kind("ASYNC") )
|
||||
redist0_fracRnd_uid15_fxpToFPTest_merged_bit_select_b_2 ( .xin(fracRnd_uid15_fxpToFPTest_merged_bit_select_b), .xout(redist0_fracRnd_uid15_fxpToFPTest_merged_bit_select_b_2_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// expFracRnd_uid16_fxpToFPTest(BITJOIN,15)@6
|
||||
assign expFracRnd_uid16_fxpToFPTest_q = {expPreRnd_uid14_fxpToFPTest_q, redist0_fracRnd_uid15_fxpToFPTest_merged_bit_select_b_2_q};
|
||||
|
||||
// expFracR_uid24_fxpToFPTest(ADD,23)@6
|
||||
assign expFracR_uid24_fxpToFPTest_a = {{2{expFracRnd_uid16_fxpToFPTest_q[32]}}, expFracRnd_uid16_fxpToFPTest_q};
|
||||
assign expFracR_uid24_fxpToFPTest_b = {34'b0000000000000000000000000000000000, rnd_uid22_fxpToFPTest_q};
|
||||
assign expFracR_uid24_fxpToFPTest_o = $signed(expFracR_uid24_fxpToFPTest_a) + $signed(expFracR_uid24_fxpToFPTest_b);
|
||||
assign expFracR_uid24_fxpToFPTest_q = expFracR_uid24_fxpToFPTest_o[33:0];
|
||||
|
||||
// expR_uid26_fxpToFPTest(BITSELECT,25)@6
|
||||
assign expR_uid26_fxpToFPTest_b = expFracR_uid24_fxpToFPTest_q[33:24];
|
||||
|
||||
// redist5_expR_uid26_fxpToFPTest_b_1(DELAY,100)
|
||||
dspba_delay_ver #( .width(10), .depth(1), .reset_kind("ASYNC") )
|
||||
redist5_expR_uid26_fxpToFPTest_b_1 ( .xin(expR_uid26_fxpToFPTest_b), .xout(redist5_expR_uid26_fxpToFPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// expR_uid38_fxpToFPTest(BITSELECT,37)@7
|
||||
assign expR_uid38_fxpToFPTest_in = redist5_expR_uid26_fxpToFPTest_b_1_q[7:0];
|
||||
assign expR_uid38_fxpToFPTest_b = expR_uid38_fxpToFPTest_in[7:0];
|
||||
|
||||
// ovf_uid29_fxpToFPTest(COMPARE,28)@7
|
||||
assign ovf_uid29_fxpToFPTest_a = {{2{redist5_expR_uid26_fxpToFPTest_b_1_q[9]}}, redist5_expR_uid26_fxpToFPTest_b_1_q};
|
||||
assign ovf_uid29_fxpToFPTest_b = {4'b0000, expInf_uid28_fxpToFPTest_q};
|
||||
assign ovf_uid29_fxpToFPTest_o = $signed(ovf_uid29_fxpToFPTest_a) - $signed(ovf_uid29_fxpToFPTest_b);
|
||||
assign ovf_uid29_fxpToFPTest_n[0] = ~ (ovf_uid29_fxpToFPTest_o[11]);
|
||||
|
||||
// inIsZero_uid12_fxpToFPTest(LOGICAL,11)@5 + 1
|
||||
assign inIsZero_uid12_fxpToFPTest_qi = vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q == maxCount_uid11_fxpToFPTest_q ? 1'b1 : 1'b0;
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
|
||||
inIsZero_uid12_fxpToFPTest_delay ( .xin(inIsZero_uid12_fxpToFPTest_qi), .xout(inIsZero_uid12_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// redist8_inIsZero_uid12_fxpToFPTest_q_2(DELAY,103)
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
|
||||
redist8_inIsZero_uid12_fxpToFPTest_q_2 ( .xin(inIsZero_uid12_fxpToFPTest_q), .xout(redist8_inIsZero_uid12_fxpToFPTest_q_2_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// udf_uid27_fxpToFPTest(COMPARE,26)@7
|
||||
assign udf_uid27_fxpToFPTest_a = {11'b00000000000, GND_q};
|
||||
assign udf_uid27_fxpToFPTest_b = {{2{redist5_expR_uid26_fxpToFPTest_b_1_q[9]}}, redist5_expR_uid26_fxpToFPTest_b_1_q};
|
||||
assign udf_uid27_fxpToFPTest_o = $signed(udf_uid27_fxpToFPTest_a) - $signed(udf_uid27_fxpToFPTest_b);
|
||||
assign udf_uid27_fxpToFPTest_n[0] = ~ (udf_uid27_fxpToFPTest_o[11]);
|
||||
|
||||
// udfOrInZero_uid33_fxpToFPTest(LOGICAL,32)@7
|
||||
assign udfOrInZero_uid33_fxpToFPTest_q = udf_uid27_fxpToFPTest_n | redist8_inIsZero_uid12_fxpToFPTest_q_2_q;
|
||||
|
||||
// excSelector_uid34_fxpToFPTest(BITJOIN,33)@7
|
||||
assign excSelector_uid34_fxpToFPTest_q = {ovf_uid29_fxpToFPTest_n, udfOrInZero_uid33_fxpToFPTest_q};
|
||||
|
||||
// expRPostExc_uid39_fxpToFPTest(MUX,38)@7
|
||||
assign expRPostExc_uid39_fxpToFPTest_s = excSelector_uid34_fxpToFPTest_q;
|
||||
always @(expRPostExc_uid39_fxpToFPTest_s or en or expR_uid38_fxpToFPTest_b or expZ_uid37_fxpToFPTest_q or expInf_uid28_fxpToFPTest_q)
|
||||
begin
|
||||
unique case (expRPostExc_uid39_fxpToFPTest_s)
|
||||
2'b00 : expRPostExc_uid39_fxpToFPTest_q = expR_uid38_fxpToFPTest_b;
|
||||
2'b01 : expRPostExc_uid39_fxpToFPTest_q = expZ_uid37_fxpToFPTest_q;
|
||||
2'b10 : expRPostExc_uid39_fxpToFPTest_q = expInf_uid28_fxpToFPTest_q;
|
||||
2'b11 : expRPostExc_uid39_fxpToFPTest_q = expInf_uid28_fxpToFPTest_q;
|
||||
default : expRPostExc_uid39_fxpToFPTest_q = 8'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// fracZ_uid31_fxpToFPTest(CONSTANT,30)
|
||||
assign fracZ_uid31_fxpToFPTest_q = 23'b00000000000000000000000;
|
||||
|
||||
// fracR_uid25_fxpToFPTest(BITSELECT,24)@6
|
||||
assign fracR_uid25_fxpToFPTest_in = expFracR_uid24_fxpToFPTest_q[23:0];
|
||||
assign fracR_uid25_fxpToFPTest_b = fracR_uid25_fxpToFPTest_in[23:1];
|
||||
|
||||
// redist6_fracR_uid25_fxpToFPTest_b_1(DELAY,101)
|
||||
dspba_delay_ver #( .width(23), .depth(1), .reset_kind("ASYNC") )
|
||||
redist6_fracR_uid25_fxpToFPTest_b_1 ( .xin(fracR_uid25_fxpToFPTest_b), .xout(redist6_fracR_uid25_fxpToFPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// excSelector_uid30_fxpToFPTest(LOGICAL,29)@7
|
||||
assign excSelector_uid30_fxpToFPTest_q = redist8_inIsZero_uid12_fxpToFPTest_q_2_q | ovf_uid29_fxpToFPTest_n | udf_uid27_fxpToFPTest_n;
|
||||
|
||||
// fracRPostExc_uid32_fxpToFPTest(MUX,31)@7
|
||||
assign fracRPostExc_uid32_fxpToFPTest_s = excSelector_uid30_fxpToFPTest_q;
|
||||
always @(fracRPostExc_uid32_fxpToFPTest_s or en or redist6_fracR_uid25_fxpToFPTest_b_1_q or fracZ_uid31_fxpToFPTest_q)
|
||||
begin
|
||||
unique case (fracRPostExc_uid32_fxpToFPTest_s)
|
||||
1'b0 : fracRPostExc_uid32_fxpToFPTest_q = redist6_fracR_uid25_fxpToFPTest_b_1_q;
|
||||
1'b1 : fracRPostExc_uid32_fxpToFPTest_q = fracZ_uid31_fxpToFPTest_q;
|
||||
default : fracRPostExc_uid32_fxpToFPTest_q = 23'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// outRes_uid40_fxpToFPTest(BITJOIN,39)@7
|
||||
assign outRes_uid40_fxpToFPTest_q = {redist11_signX_uid6_fxpToFPTest_b_7_q, expRPostExc_uid39_fxpToFPTest_q, fracRPostExc_uid32_fxpToFPTest_q};
|
||||
|
||||
// xOut(GPOUT,4)@7
|
||||
assign q = outRes_uid40_fxpToFPTest_q;
|
||||
|
||||
endmodule
|
||||
@@ -1,486 +0,0 @@
|
||||
// -------------------------------------------------------------------------
|
||||
// High Level Design Compiler for Intel(R) FPGAs Version 17.1 (Release Build #273)
|
||||
// Quartus Prime development tool and MATLAB/Simulink Interface
|
||||
//
|
||||
// Legal Notice: Copyright 2017 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly
|
||||
// subject to the terms and conditions of the Intel FPGA Software License
|
||||
// Agreement, Intel MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for
|
||||
// the sole purpose of programming logic devices manufactured by Intel
|
||||
// and sold by Intel or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
// ---------------------------------------------------------------------------
|
||||
|
||||
// SystemVerilog created from acl_utof
|
||||
// SystemVerilog created on Sun Dec 27 09:47:21 2020
|
||||
|
||||
|
||||
(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
|
||||
module acl_utof (
|
||||
input wire [31:0] a,
|
||||
input wire [0:0] en,
|
||||
output wire [31:0] q,
|
||||
input wire clk,
|
||||
input wire areset
|
||||
);
|
||||
|
||||
wire [0:0] GND_q;
|
||||
wire [5:0] maxCount_uid7_fxpToFPTest_q;
|
||||
wire [0:0] inIsZero_uid8_fxpToFPTest_qi;
|
||||
reg [0:0] inIsZero_uid8_fxpToFPTest_q;
|
||||
wire [7:0] msbIn_uid9_fxpToFPTest_q;
|
||||
wire [8:0] expPreRnd_uid10_fxpToFPTest_a;
|
||||
wire [8:0] expPreRnd_uid10_fxpToFPTest_b;
|
||||
logic [8:0] expPreRnd_uid10_fxpToFPTest_o;
|
||||
wire [8:0] expPreRnd_uid10_fxpToFPTest_q;
|
||||
wire [32:0] expFracRnd_uid12_fxpToFPTest_q;
|
||||
wire [0:0] sticky_uid16_fxpToFPTest_qi;
|
||||
reg [0:0] sticky_uid16_fxpToFPTest_q;
|
||||
wire [0:0] nr_uid17_fxpToFPTest_q;
|
||||
wire [0:0] rnd_uid18_fxpToFPTest_qi;
|
||||
reg [0:0] rnd_uid18_fxpToFPTest_q;
|
||||
wire [34:0] expFracR_uid20_fxpToFPTest_a;
|
||||
wire [34:0] expFracR_uid20_fxpToFPTest_b;
|
||||
logic [34:0] expFracR_uid20_fxpToFPTest_o;
|
||||
wire [33:0] expFracR_uid20_fxpToFPTest_q;
|
||||
wire [23:0] fracR_uid21_fxpToFPTest_in;
|
||||
wire [22:0] fracR_uid21_fxpToFPTest_b;
|
||||
wire [9:0] expR_uid22_fxpToFPTest_b;
|
||||
wire [11:0] udf_uid23_fxpToFPTest_a;
|
||||
wire [11:0] udf_uid23_fxpToFPTest_b;
|
||||
logic [11:0] udf_uid23_fxpToFPTest_o;
|
||||
wire [0:0] udf_uid23_fxpToFPTest_n;
|
||||
wire [7:0] expInf_uid24_fxpToFPTest_q;
|
||||
wire [11:0] ovf_uid25_fxpToFPTest_a;
|
||||
wire [11:0] ovf_uid25_fxpToFPTest_b;
|
||||
logic [11:0] ovf_uid25_fxpToFPTest_o;
|
||||
wire [0:0] ovf_uid25_fxpToFPTest_n;
|
||||
wire [0:0] excSelector_uid26_fxpToFPTest_q;
|
||||
wire [22:0] fracZ_uid27_fxpToFPTest_q;
|
||||
wire [0:0] fracRPostExc_uid28_fxpToFPTest_s;
|
||||
reg [22:0] fracRPostExc_uid28_fxpToFPTest_q;
|
||||
wire [0:0] udfOrInZero_uid29_fxpToFPTest_q;
|
||||
wire [1:0] excSelector_uid30_fxpToFPTest_q;
|
||||
wire [7:0] expZ_uid33_fxpToFPTest_q;
|
||||
wire [7:0] expR_uid34_fxpToFPTest_in;
|
||||
wire [7:0] expR_uid34_fxpToFPTest_b;
|
||||
wire [1:0] expRPostExc_uid35_fxpToFPTest_s;
|
||||
reg [7:0] expRPostExc_uid35_fxpToFPTest_q;
|
||||
wire [31:0] outRes_uid36_fxpToFPTest_q;
|
||||
wire [31:0] zs_uid38_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [0:0] vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_qi;
|
||||
reg [0:0] vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [0:0] vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_s;
|
||||
reg [31:0] vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [15:0] zs_uid43_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [0:0] vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [31:0] cStage_uid48_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [0:0] vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_s;
|
||||
reg [31:0] vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [0:0] vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [31:0] cStage_uid55_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [0:0] vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_s;
|
||||
reg [31:0] vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [3:0] zs_uid57_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [0:0] vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [31:0] cStage_uid62_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [0:0] vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_s;
|
||||
reg [31:0] vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [1:0] zs_uid64_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [0:0] vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [31:0] cStage_uid69_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [0:0] vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_s;
|
||||
reg [31:0] vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [0:0] vCount_uid73_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [31:0] cStage_uid76_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [0:0] vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_s;
|
||||
reg [31:0] vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [5:0] vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [7:0] vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_a;
|
||||
wire [7:0] vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_b;
|
||||
logic [7:0] vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_o;
|
||||
wire [0:0] vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_c;
|
||||
wire [0:0] vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_s;
|
||||
reg [5:0] vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [1:0] l_uid13_fxpToFPTest_merged_bit_select_in;
|
||||
wire [0:0] l_uid13_fxpToFPTest_merged_bit_select_b;
|
||||
wire [0:0] l_uid13_fxpToFPTest_merged_bit_select_c;
|
||||
wire [15:0] rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b;
|
||||
wire [15:0] rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c;
|
||||
wire [7:0] rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b;
|
||||
wire [23:0] rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c;
|
||||
wire [3:0] rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b;
|
||||
wire [27:0] rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c;
|
||||
wire [1:0] rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b;
|
||||
wire [29:0] rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c;
|
||||
wire [0:0] rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b;
|
||||
wire [30:0] rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c;
|
||||
wire [30:0] fracRnd_uid11_fxpToFPTest_merged_bit_select_in;
|
||||
wire [23:0] fracRnd_uid11_fxpToFPTest_merged_bit_select_b;
|
||||
wire [6:0] fracRnd_uid11_fxpToFPTest_merged_bit_select_c;
|
||||
reg [23:0] redist0_fracRnd_uid11_fxpToFPTest_merged_bit_select_b_1_q;
|
||||
reg [0:0] redist1_vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q_1_q;
|
||||
reg [0:0] redist2_vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q_1_q;
|
||||
reg [0:0] redist3_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2_q;
|
||||
reg [0:0] redist4_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_q;
|
||||
reg [0:0] redist5_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_q;
|
||||
reg [9:0] redist6_expR_uid22_fxpToFPTest_b_1_q;
|
||||
reg [22:0] redist7_fracR_uid21_fxpToFPTest_b_1_q;
|
||||
reg [32:0] redist8_expFracRnd_uid12_fxpToFPTest_q_1_q;
|
||||
reg [0:0] redist9_inIsZero_uid8_fxpToFPTest_q_2_q;
|
||||
reg [31:0] redist10_xIn_a_1_q;
|
||||
|
||||
|
||||
// GND(CONSTANT,0)
|
||||
assign GND_q = 1'b0;
|
||||
|
||||
// expInf_uid24_fxpToFPTest(CONSTANT,23)
|
||||
assign expInf_uid24_fxpToFPTest_q = 8'b11111111;
|
||||
|
||||
// expZ_uid33_fxpToFPTest(CONSTANT,32)
|
||||
assign expZ_uid33_fxpToFPTest_q = 8'b00000000;
|
||||
|
||||
// rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select(BITSELECT,89)@4
|
||||
assign rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b = vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q[31:31];
|
||||
assign rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c = vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q[30:0];
|
||||
|
||||
// cStage_uid76_lzcShifterZ1_uid6_fxpToFPTest(BITJOIN,75)@4
|
||||
assign cStage_uid76_lzcShifterZ1_uid6_fxpToFPTest_q = {rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c, GND_q};
|
||||
|
||||
// rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select(BITSELECT,88)@3
|
||||
assign rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b = vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q[31:30];
|
||||
assign rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c = vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q[29:0];
|
||||
|
||||
// zs_uid64_lzcShifterZ1_uid6_fxpToFPTest(CONSTANT,63)
|
||||
assign zs_uid64_lzcShifterZ1_uid6_fxpToFPTest_q = 2'b00;
|
||||
|
||||
// cStage_uid69_lzcShifterZ1_uid6_fxpToFPTest(BITJOIN,68)@3
|
||||
assign cStage_uid69_lzcShifterZ1_uid6_fxpToFPTest_q = {rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c, zs_uid64_lzcShifterZ1_uid6_fxpToFPTest_q};
|
||||
|
||||
// rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select(BITSELECT,87)@3
|
||||
assign rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b = vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q[31:28];
|
||||
assign rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c = vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q[27:0];
|
||||
|
||||
// zs_uid57_lzcShifterZ1_uid6_fxpToFPTest(CONSTANT,56)
|
||||
assign zs_uid57_lzcShifterZ1_uid6_fxpToFPTest_q = 4'b0000;
|
||||
|
||||
// cStage_uid62_lzcShifterZ1_uid6_fxpToFPTest(BITJOIN,61)@3
|
||||
assign cStage_uid62_lzcShifterZ1_uid6_fxpToFPTest_q = {rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c, zs_uid57_lzcShifterZ1_uid6_fxpToFPTest_q};
|
||||
|
||||
// rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select(BITSELECT,86)@2
|
||||
assign rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b = vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q[31:24];
|
||||
assign rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c = vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q[23:0];
|
||||
|
||||
// cStage_uid55_lzcShifterZ1_uid6_fxpToFPTest(BITJOIN,54)@2
|
||||
assign cStage_uid55_lzcShifterZ1_uid6_fxpToFPTest_q = {rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c, expZ_uid33_fxpToFPTest_q};
|
||||
|
||||
// rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select(BITSELECT,85)@1
|
||||
assign rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b = vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q[31:16];
|
||||
assign rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c = vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q[15:0];
|
||||
|
||||
// zs_uid43_lzcShifterZ1_uid6_fxpToFPTest(CONSTANT,42)
|
||||
assign zs_uid43_lzcShifterZ1_uid6_fxpToFPTest_q = 16'b0000000000000000;
|
||||
|
||||
// cStage_uid48_lzcShifterZ1_uid6_fxpToFPTest(BITJOIN,47)@1
|
||||
assign cStage_uid48_lzcShifterZ1_uid6_fxpToFPTest_q = {rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c, zs_uid43_lzcShifterZ1_uid6_fxpToFPTest_q};
|
||||
|
||||
// zs_uid38_lzcShifterZ1_uid6_fxpToFPTest(CONSTANT,37)
|
||||
assign zs_uid38_lzcShifterZ1_uid6_fxpToFPTest_q = 32'b00000000000000000000000000000000;
|
||||
|
||||
// redist10_xIn_a_1(DELAY,101)
|
||||
dspba_delay_ver #( .width(32), .depth(1), .reset_kind("ASYNC") )
|
||||
redist10_xIn_a_1 ( .xin(a), .xout(redist10_xIn_a_1_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest(LOGICAL,39)@0 + 1
|
||||
assign vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_qi = a == zs_uid38_lzcShifterZ1_uid6_fxpToFPTest_q ? 1'b1 : 1'b0;
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
|
||||
vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_delay ( .xin(vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_qi), .xout(vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest(MUX,41)@1
|
||||
assign vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_s = vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
always @(vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_s or en or redist10_xIn_a_1_q or zs_uid38_lzcShifterZ1_uid6_fxpToFPTest_q)
|
||||
begin
|
||||
unique case (vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_s)
|
||||
1'b0 : vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q = redist10_xIn_a_1_q;
|
||||
1'b1 : vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q = zs_uid38_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
default : vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q = 32'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest(LOGICAL,44)@1
|
||||
assign vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q = rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b == zs_uid43_lzcShifterZ1_uid6_fxpToFPTest_q ? 1'b1 : 1'b0;
|
||||
|
||||
// vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest(MUX,48)@1 + 1
|
||||
assign vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_s = vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
always @ (posedge clk or posedge areset)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
unique case (vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_s)
|
||||
1'b0 : vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q <= vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
1'b1 : vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q <= cStage_uid48_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
default : vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest(LOGICAL,51)@2
|
||||
assign vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q = rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b == expZ_uid33_fxpToFPTest_q ? 1'b1 : 1'b0;
|
||||
|
||||
// vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest(MUX,55)@2 + 1
|
||||
assign vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_s = vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
always @ (posedge clk or posedge areset)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
unique case (vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_s)
|
||||
1'b0 : vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q <= vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
1'b1 : vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q <= cStage_uid55_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
default : vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest(LOGICAL,58)@3
|
||||
assign vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q = rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b == zs_uid57_lzcShifterZ1_uid6_fxpToFPTest_q ? 1'b1 : 1'b0;
|
||||
|
||||
// vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest(MUX,62)@3
|
||||
assign vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_s = vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
always @(vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_s or en or vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q or cStage_uid62_lzcShifterZ1_uid6_fxpToFPTest_q)
|
||||
begin
|
||||
unique case (vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_s)
|
||||
1'b0 : vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q = vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
1'b1 : vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q = cStage_uid62_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
default : vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q = 32'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest(LOGICAL,65)@3
|
||||
assign vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q = rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b == zs_uid64_lzcShifterZ1_uid6_fxpToFPTest_q ? 1'b1 : 1'b0;
|
||||
|
||||
// vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest(MUX,69)@3 + 1
|
||||
assign vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_s = vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
always @ (posedge clk or posedge areset)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
unique case (vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_s)
|
||||
1'b0 : vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q <= vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
1'b1 : vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q <= cStage_uid69_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
default : vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// vCount_uid73_lzcShifterZ1_uid6_fxpToFPTest(LOGICAL,72)@4
|
||||
assign vCount_uid73_lzcShifterZ1_uid6_fxpToFPTest_q = rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b == GND_q ? 1'b1 : 1'b0;
|
||||
|
||||
// vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest(MUX,76)@4
|
||||
assign vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_s = vCount_uid73_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
always @(vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_s or en or vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q or cStage_uid76_lzcShifterZ1_uid6_fxpToFPTest_q)
|
||||
begin
|
||||
unique case (vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_s)
|
||||
1'b0 : vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_q = vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
1'b1 : vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_q = cStage_uid76_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
default : vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_q = 32'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// fracRnd_uid11_fxpToFPTest_merged_bit_select(BITSELECT,90)@4
|
||||
assign fracRnd_uid11_fxpToFPTest_merged_bit_select_in = vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_q[30:0];
|
||||
assign fracRnd_uid11_fxpToFPTest_merged_bit_select_b = fracRnd_uid11_fxpToFPTest_merged_bit_select_in[30:7];
|
||||
assign fracRnd_uid11_fxpToFPTest_merged_bit_select_c = fracRnd_uid11_fxpToFPTest_merged_bit_select_in[6:0];
|
||||
|
||||
// sticky_uid16_fxpToFPTest(LOGICAL,15)@4 + 1
|
||||
assign sticky_uid16_fxpToFPTest_qi = fracRnd_uid11_fxpToFPTest_merged_bit_select_c != 7'b0000000 ? 1'b1 : 1'b0;
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
|
||||
sticky_uid16_fxpToFPTest_delay ( .xin(sticky_uid16_fxpToFPTest_qi), .xout(sticky_uid16_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// nr_uid17_fxpToFPTest(LOGICAL,16)@5
|
||||
assign nr_uid17_fxpToFPTest_q = ~ (l_uid13_fxpToFPTest_merged_bit_select_c);
|
||||
|
||||
// maxCount_uid7_fxpToFPTest(CONSTANT,6)
|
||||
assign maxCount_uid7_fxpToFPTest_q = 6'b100000;
|
||||
|
||||
// redist5_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4(DELAY,96)
|
||||
dspba_delay_ver #( .width(1), .depth(3), .reset_kind("ASYNC") )
|
||||
redist5_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4 ( .xin(vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q), .xout(redist5_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// redist4_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3(DELAY,95)
|
||||
dspba_delay_ver #( .width(1), .depth(3), .reset_kind("ASYNC") )
|
||||
redist4_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3 ( .xin(vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q), .xout(redist4_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// redist3_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2(DELAY,94)
|
||||
dspba_delay_ver #( .width(1), .depth(2), .reset_kind("ASYNC") )
|
||||
redist3_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2 ( .xin(vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q), .xout(redist3_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// redist2_vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q_1(DELAY,93)
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
|
||||
redist2_vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q_1 ( .xin(vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q), .xout(redist2_vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q_1_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// redist1_vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q_1(DELAY,92)
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
|
||||
redist1_vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q_1 ( .xin(vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q), .xout(redist1_vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q_1_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest(BITJOIN,77)@4
|
||||
assign vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest_q = {redist5_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_q, redist4_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_q, redist3_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2_q, redist2_vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q_1_q, redist1_vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q_1_q, vCount_uid73_lzcShifterZ1_uid6_fxpToFPTest_q};
|
||||
|
||||
// vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest(COMPARE,79)@4
|
||||
assign vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_a = {2'b00, maxCount_uid7_fxpToFPTest_q};
|
||||
assign vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_b = {2'b00, vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest_q};
|
||||
assign vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_o = $unsigned(vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_a) - $unsigned(vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_b);
|
||||
assign vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_c[0] = vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_o[7];
|
||||
|
||||
// vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest(MUX,81)@4 + 1
|
||||
assign vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_s = vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_c;
|
||||
always @ (posedge clk or posedge areset)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_q <= 6'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
unique case (vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_s)
|
||||
1'b0 : vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_q <= vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
1'b1 : vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_q <= maxCount_uid7_fxpToFPTest_q;
|
||||
default : vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_q <= 6'b0;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// msbIn_uid9_fxpToFPTest(CONSTANT,8)
|
||||
assign msbIn_uid9_fxpToFPTest_q = 8'b10011110;
|
||||
|
||||
// expPreRnd_uid10_fxpToFPTest(SUB,9)@5
|
||||
assign expPreRnd_uid10_fxpToFPTest_a = {1'b0, msbIn_uid9_fxpToFPTest_q};
|
||||
assign expPreRnd_uid10_fxpToFPTest_b = {3'b000, vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_q};
|
||||
assign expPreRnd_uid10_fxpToFPTest_o = $unsigned(expPreRnd_uid10_fxpToFPTest_a) - $unsigned(expPreRnd_uid10_fxpToFPTest_b);
|
||||
assign expPreRnd_uid10_fxpToFPTest_q = expPreRnd_uid10_fxpToFPTest_o[8:0];
|
||||
|
||||
// redist0_fracRnd_uid11_fxpToFPTest_merged_bit_select_b_1(DELAY,91)
|
||||
dspba_delay_ver #( .width(24), .depth(1), .reset_kind("ASYNC") )
|
||||
redist0_fracRnd_uid11_fxpToFPTest_merged_bit_select_b_1 ( .xin(fracRnd_uid11_fxpToFPTest_merged_bit_select_b), .xout(redist0_fracRnd_uid11_fxpToFPTest_merged_bit_select_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// expFracRnd_uid12_fxpToFPTest(BITJOIN,11)@5
|
||||
assign expFracRnd_uid12_fxpToFPTest_q = {expPreRnd_uid10_fxpToFPTest_q, redist0_fracRnd_uid11_fxpToFPTest_merged_bit_select_b_1_q};
|
||||
|
||||
// l_uid13_fxpToFPTest_merged_bit_select(BITSELECT,84)@5
|
||||
assign l_uid13_fxpToFPTest_merged_bit_select_in = expFracRnd_uid12_fxpToFPTest_q[1:0];
|
||||
assign l_uid13_fxpToFPTest_merged_bit_select_b = l_uid13_fxpToFPTest_merged_bit_select_in[1:1];
|
||||
assign l_uid13_fxpToFPTest_merged_bit_select_c = l_uid13_fxpToFPTest_merged_bit_select_in[0:0];
|
||||
|
||||
// rnd_uid18_fxpToFPTest(LOGICAL,17)@5 + 1
|
||||
assign rnd_uid18_fxpToFPTest_qi = l_uid13_fxpToFPTest_merged_bit_select_b | nr_uid17_fxpToFPTest_q | sticky_uid16_fxpToFPTest_q;
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
|
||||
rnd_uid18_fxpToFPTest_delay ( .xin(rnd_uid18_fxpToFPTest_qi), .xout(rnd_uid18_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// redist8_expFracRnd_uid12_fxpToFPTest_q_1(DELAY,99)
|
||||
dspba_delay_ver #( .width(33), .depth(1), .reset_kind("ASYNC") )
|
||||
redist8_expFracRnd_uid12_fxpToFPTest_q_1 ( .xin(expFracRnd_uid12_fxpToFPTest_q), .xout(redist8_expFracRnd_uid12_fxpToFPTest_q_1_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// expFracR_uid20_fxpToFPTest(ADD,19)@6
|
||||
assign expFracR_uid20_fxpToFPTest_a = {{2{redist8_expFracRnd_uid12_fxpToFPTest_q_1_q[32]}}, redist8_expFracRnd_uid12_fxpToFPTest_q_1_q};
|
||||
assign expFracR_uid20_fxpToFPTest_b = {34'b0000000000000000000000000000000000, rnd_uid18_fxpToFPTest_q};
|
||||
assign expFracR_uid20_fxpToFPTest_o = $signed(expFracR_uid20_fxpToFPTest_a) + $signed(expFracR_uid20_fxpToFPTest_b);
|
||||
assign expFracR_uid20_fxpToFPTest_q = expFracR_uid20_fxpToFPTest_o[33:0];
|
||||
|
||||
// expR_uid22_fxpToFPTest(BITSELECT,21)@6
|
||||
assign expR_uid22_fxpToFPTest_b = expFracR_uid20_fxpToFPTest_q[33:24];
|
||||
|
||||
// redist6_expR_uid22_fxpToFPTest_b_1(DELAY,97)
|
||||
dspba_delay_ver #( .width(10), .depth(1), .reset_kind("ASYNC") )
|
||||
redist6_expR_uid22_fxpToFPTest_b_1 ( .xin(expR_uid22_fxpToFPTest_b), .xout(redist6_expR_uid22_fxpToFPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// expR_uid34_fxpToFPTest(BITSELECT,33)@7
|
||||
assign expR_uid34_fxpToFPTest_in = redist6_expR_uid22_fxpToFPTest_b_1_q[7:0];
|
||||
assign expR_uid34_fxpToFPTest_b = expR_uid34_fxpToFPTest_in[7:0];
|
||||
|
||||
// ovf_uid25_fxpToFPTest(COMPARE,24)@7
|
||||
assign ovf_uid25_fxpToFPTest_a = {{2{redist6_expR_uid22_fxpToFPTest_b_1_q[9]}}, redist6_expR_uid22_fxpToFPTest_b_1_q};
|
||||
assign ovf_uid25_fxpToFPTest_b = {4'b0000, expInf_uid24_fxpToFPTest_q};
|
||||
assign ovf_uid25_fxpToFPTest_o = $signed(ovf_uid25_fxpToFPTest_a) - $signed(ovf_uid25_fxpToFPTest_b);
|
||||
assign ovf_uid25_fxpToFPTest_n[0] = ~ (ovf_uid25_fxpToFPTest_o[11]);
|
||||
|
||||
// inIsZero_uid8_fxpToFPTest(LOGICAL,7)@5 + 1
|
||||
assign inIsZero_uid8_fxpToFPTest_qi = vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_q == maxCount_uid7_fxpToFPTest_q ? 1'b1 : 1'b0;
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
|
||||
inIsZero_uid8_fxpToFPTest_delay ( .xin(inIsZero_uid8_fxpToFPTest_qi), .xout(inIsZero_uid8_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// redist9_inIsZero_uid8_fxpToFPTest_q_2(DELAY,100)
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
|
||||
redist9_inIsZero_uid8_fxpToFPTest_q_2 ( .xin(inIsZero_uid8_fxpToFPTest_q), .xout(redist9_inIsZero_uid8_fxpToFPTest_q_2_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// udf_uid23_fxpToFPTest(COMPARE,22)@7
|
||||
assign udf_uid23_fxpToFPTest_a = {11'b00000000000, GND_q};
|
||||
assign udf_uid23_fxpToFPTest_b = {{2{redist6_expR_uid22_fxpToFPTest_b_1_q[9]}}, redist6_expR_uid22_fxpToFPTest_b_1_q};
|
||||
assign udf_uid23_fxpToFPTest_o = $signed(udf_uid23_fxpToFPTest_a) - $signed(udf_uid23_fxpToFPTest_b);
|
||||
assign udf_uid23_fxpToFPTest_n[0] = ~ (udf_uid23_fxpToFPTest_o[11]);
|
||||
|
||||
// udfOrInZero_uid29_fxpToFPTest(LOGICAL,28)@7
|
||||
assign udfOrInZero_uid29_fxpToFPTest_q = udf_uid23_fxpToFPTest_n | redist9_inIsZero_uid8_fxpToFPTest_q_2_q;
|
||||
|
||||
// excSelector_uid30_fxpToFPTest(BITJOIN,29)@7
|
||||
assign excSelector_uid30_fxpToFPTest_q = {ovf_uid25_fxpToFPTest_n, udfOrInZero_uid29_fxpToFPTest_q};
|
||||
|
||||
// expRPostExc_uid35_fxpToFPTest(MUX,34)@7
|
||||
assign expRPostExc_uid35_fxpToFPTest_s = excSelector_uid30_fxpToFPTest_q;
|
||||
always @(expRPostExc_uid35_fxpToFPTest_s or en or expR_uid34_fxpToFPTest_b or expZ_uid33_fxpToFPTest_q or expInf_uid24_fxpToFPTest_q)
|
||||
begin
|
||||
unique case (expRPostExc_uid35_fxpToFPTest_s)
|
||||
2'b00 : expRPostExc_uid35_fxpToFPTest_q = expR_uid34_fxpToFPTest_b;
|
||||
2'b01 : expRPostExc_uid35_fxpToFPTest_q = expZ_uid33_fxpToFPTest_q;
|
||||
2'b10 : expRPostExc_uid35_fxpToFPTest_q = expInf_uid24_fxpToFPTest_q;
|
||||
2'b11 : expRPostExc_uid35_fxpToFPTest_q = expInf_uid24_fxpToFPTest_q;
|
||||
default : expRPostExc_uid35_fxpToFPTest_q = 8'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// fracZ_uid27_fxpToFPTest(CONSTANT,26)
|
||||
assign fracZ_uid27_fxpToFPTest_q = 23'b00000000000000000000000;
|
||||
|
||||
// fracR_uid21_fxpToFPTest(BITSELECT,20)@6
|
||||
assign fracR_uid21_fxpToFPTest_in = expFracR_uid20_fxpToFPTest_q[23:0];
|
||||
assign fracR_uid21_fxpToFPTest_b = fracR_uid21_fxpToFPTest_in[23:1];
|
||||
|
||||
// redist7_fracR_uid21_fxpToFPTest_b_1(DELAY,98)
|
||||
dspba_delay_ver #( .width(23), .depth(1), .reset_kind("ASYNC") )
|
||||
redist7_fracR_uid21_fxpToFPTest_b_1 ( .xin(fracR_uid21_fxpToFPTest_b), .xout(redist7_fracR_uid21_fxpToFPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// excSelector_uid26_fxpToFPTest(LOGICAL,25)@7
|
||||
assign excSelector_uid26_fxpToFPTest_q = redist9_inIsZero_uid8_fxpToFPTest_q_2_q | ovf_uid25_fxpToFPTest_n | udf_uid23_fxpToFPTest_n;
|
||||
|
||||
// fracRPostExc_uid28_fxpToFPTest(MUX,27)@7
|
||||
assign fracRPostExc_uid28_fxpToFPTest_s = excSelector_uid26_fxpToFPTest_q;
|
||||
always @(fracRPostExc_uid28_fxpToFPTest_s or en or redist7_fracR_uid21_fxpToFPTest_b_1_q or fracZ_uid27_fxpToFPTest_q)
|
||||
begin
|
||||
unique case (fracRPostExc_uid28_fxpToFPTest_s)
|
||||
1'b0 : fracRPostExc_uid28_fxpToFPTest_q = redist7_fracR_uid21_fxpToFPTest_b_1_q;
|
||||
1'b1 : fracRPostExc_uid28_fxpToFPTest_q = fracZ_uid27_fxpToFPTest_q;
|
||||
default : fracRPostExc_uid28_fxpToFPTest_q = 23'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// outRes_uid36_fxpToFPTest(BITJOIN,35)@7
|
||||
assign outRes_uid36_fxpToFPTest_q = {GND_q, expRPostExc_uid35_fxpToFPTest_q, fracRPostExc_uid28_fxpToFPTest_q};
|
||||
|
||||
// xOut(GPOUT,4)@7
|
||||
assign q = outRes_uid36_fxpToFPTest_q;
|
||||
|
||||
endmodule
|
||||
@@ -1,586 +0,0 @@
|
||||
// -------------------------------------------------------------------------
|
||||
// High Level Design Compiler for Intel(R) FPGAs Version 18.1 (Release Build #277)
|
||||
// Quartus Prime development tool and MATLAB/Simulink Interface
|
||||
//
|
||||
// Legal Notice: Copyright 2019 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly
|
||||
// subject to the terms and conditions of the Intel FPGA Software License
|
||||
// Agreement, Intel MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for
|
||||
// the sole purpose of programming logic devices manufactured by Intel
|
||||
// and sold by Intel or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
// ---------------------------------------------------------------------------
|
||||
|
||||
// SystemVerilog created from acl_ftoi
|
||||
// SystemVerilog created on Sun Dec 27 09:48:58 2020
|
||||
|
||||
|
||||
(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
|
||||
module acl_ftoi (
|
||||
input wire [31:0] a,
|
||||
input wire [0:0] en,
|
||||
output wire [31:0] q,
|
||||
input wire clk,
|
||||
input wire areset
|
||||
);
|
||||
|
||||
wire [0:0] GND_q;
|
||||
wire [7:0] cstAllOWE_uid6_fpToFxPTest_q;
|
||||
wire [22:0] cstZeroWF_uid7_fpToFxPTest_q;
|
||||
wire [7:0] cstAllZWE_uid8_fpToFxPTest_q;
|
||||
wire [7:0] exp_x_uid9_fpToFxPTest_b;
|
||||
wire [22:0] frac_x_uid10_fpToFxPTest_b;
|
||||
wire [0:0] excZ_x_uid11_fpToFxPTest_q;
|
||||
wire [0:0] expXIsMax_uid12_fpToFxPTest_q;
|
||||
wire [0:0] fracXIsZero_uid13_fpToFxPTest_q;
|
||||
wire [0:0] fracXIsNotZero_uid14_fpToFxPTest_q;
|
||||
wire [0:0] excI_x_uid15_fpToFxPTest_qi;
|
||||
reg [0:0] excI_x_uid15_fpToFxPTest_q;
|
||||
wire [0:0] excN_x_uid16_fpToFxPTest_q;
|
||||
wire [0:0] fracPostZ_uid23_fpToFxPTest_s;
|
||||
reg [22:0] fracPostZ_uid23_fpToFxPTest_q;
|
||||
wire [0:0] invExcXZ_uid24_fpToFxPTest_qi;
|
||||
reg [0:0] invExcXZ_uid24_fpToFxPTest_q;
|
||||
wire [23:0] oFracX_uid25_fpToFxPTest_q;
|
||||
wire [0:0] signX_uid27_fpToFxPTest_b;
|
||||
wire [0:0] notNan_uid28_fpToFxPTest_q;
|
||||
wire [0:0] signX_uid29_fpToFxPTest_qi;
|
||||
reg [0:0] signX_uid29_fpToFxPTest_q;
|
||||
wire [8:0] ovfExpVal_uid30_fpToFxPTest_q;
|
||||
wire [10:0] ovfExpRange_uid31_fpToFxPTest_a;
|
||||
wire [10:0] ovfExpRange_uid31_fpToFxPTest_b;
|
||||
logic [10:0] ovfExpRange_uid31_fpToFxPTest_o;
|
||||
wire [0:0] ovfExpRange_uid31_fpToFxPTest_n;
|
||||
wire [7:0] udfExpVal_uid32_fpToFxPTest_q;
|
||||
wire [10:0] udf_uid33_fpToFxPTest_a;
|
||||
wire [10:0] udf_uid33_fpToFxPTest_b;
|
||||
logic [10:0] udf_uid33_fpToFxPTest_o;
|
||||
wire [0:0] udf_uid33_fpToFxPTest_n;
|
||||
wire [8:0] ovfExpVal_uid34_fpToFxPTest_q;
|
||||
wire [10:0] shiftValE_uid35_fpToFxPTest_a;
|
||||
wire [10:0] shiftValE_uid35_fpToFxPTest_b;
|
||||
logic [10:0] shiftValE_uid35_fpToFxPTest_o;
|
||||
wire [9:0] shiftValE_uid35_fpToFxPTest_q;
|
||||
wire [5:0] shiftValRaw_uid36_fpToFxPTest_in;
|
||||
wire [5:0] shiftValRaw_uid36_fpToFxPTest_b;
|
||||
wire [5:0] maxShiftCst_uid37_fpToFxPTest_q;
|
||||
wire [11:0] shiftOutOfRange_uid38_fpToFxPTest_a;
|
||||
wire [11:0] shiftOutOfRange_uid38_fpToFxPTest_b;
|
||||
logic [11:0] shiftOutOfRange_uid38_fpToFxPTest_o;
|
||||
wire [0:0] shiftOutOfRange_uid38_fpToFxPTest_n;
|
||||
wire [0:0] shiftVal_uid39_fpToFxPTest_s;
|
||||
reg [5:0] shiftVal_uid39_fpToFxPTest_q;
|
||||
wire [31:0] shifterIn_uid41_fpToFxPTest_q;
|
||||
wire [31:0] maxPosValueS_uid43_fpToFxPTest_q;
|
||||
wire [31:0] maxNegValueS_uid44_fpToFxPTest_q;
|
||||
wire [32:0] zRightShiferNoStickyOut_uid45_fpToFxPTest_q;
|
||||
wire [32:0] xXorSignE_uid46_fpToFxPTest_b;
|
||||
wire [32:0] xXorSignE_uid46_fpToFxPTest_qi;
|
||||
reg [32:0] xXorSignE_uid46_fpToFxPTest_q;
|
||||
wire [2:0] d0_uid47_fpToFxPTest_q;
|
||||
wire [33:0] sPostRndFull_uid48_fpToFxPTest_a;
|
||||
wire [33:0] sPostRndFull_uid48_fpToFxPTest_b;
|
||||
logic [33:0] sPostRndFull_uid48_fpToFxPTest_o;
|
||||
wire [33:0] sPostRndFull_uid48_fpToFxPTest_q;
|
||||
wire [32:0] sPostRnd_uid49_fpToFxPTest_in;
|
||||
wire [31:0] sPostRnd_uid49_fpToFxPTest_b;
|
||||
wire [34:0] sPostRnd_uid50_fpToFxPTest_in;
|
||||
wire [33:0] sPostRnd_uid50_fpToFxPTest_b;
|
||||
wire [35:0] rndOvfPos_uid51_fpToFxPTest_a;
|
||||
wire [35:0] rndOvfPos_uid51_fpToFxPTest_b;
|
||||
logic [35:0] rndOvfPos_uid51_fpToFxPTest_o;
|
||||
wire [0:0] rndOvfPos_uid51_fpToFxPTest_c;
|
||||
wire [0:0] ovfPostRnd_uid52_fpToFxPTest_q;
|
||||
wire [2:0] muxSelConc_uid53_fpToFxPTest_q;
|
||||
reg [1:0] muxSel_uid54_fpToFxPTest_q;
|
||||
wire [31:0] maxNegValueU_uid55_fpToFxPTest_q;
|
||||
wire [1:0] finalOut_uid56_fpToFxPTest_s;
|
||||
reg [31:0] finalOut_uid56_fpToFxPTest_q;
|
||||
wire [30:0] rightShiftStage0Idx1Rng1_uid60_rightShiferNoStickyOut_uid42_fpToFxPTest_b;
|
||||
wire [31:0] rightShiftStage0Idx1_uid62_rightShiferNoStickyOut_uid42_fpToFxPTest_q;
|
||||
wire [29:0] rightShiftStage0Idx2Rng2_uid63_rightShiferNoStickyOut_uid42_fpToFxPTest_b;
|
||||
wire [1:0] rightShiftStage0Idx2Pad2_uid64_rightShiferNoStickyOut_uid42_fpToFxPTest_q;
|
||||
wire [31:0] rightShiftStage0Idx2_uid65_rightShiferNoStickyOut_uid42_fpToFxPTest_q;
|
||||
wire [28:0] rightShiftStage0Idx3Rng3_uid66_rightShiferNoStickyOut_uid42_fpToFxPTest_b;
|
||||
wire [2:0] rightShiftStage0Idx3Pad3_uid67_rightShiferNoStickyOut_uid42_fpToFxPTest_q;
|
||||
wire [31:0] rightShiftStage0Idx3_uid68_rightShiferNoStickyOut_uid42_fpToFxPTest_q;
|
||||
wire [1:0] rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest_s;
|
||||
reg [31:0] rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest_q;
|
||||
wire [27:0] rightShiftStage1Idx1Rng4_uid71_rightShiferNoStickyOut_uid42_fpToFxPTest_b;
|
||||
wire [3:0] rightShiftStage1Idx1Pad4_uid72_rightShiferNoStickyOut_uid42_fpToFxPTest_q;
|
||||
wire [31:0] rightShiftStage1Idx1_uid73_rightShiferNoStickyOut_uid42_fpToFxPTest_q;
|
||||
wire [23:0] rightShiftStage1Idx2Rng8_uid74_rightShiferNoStickyOut_uid42_fpToFxPTest_b;
|
||||
wire [31:0] rightShiftStage1Idx2_uid76_rightShiferNoStickyOut_uid42_fpToFxPTest_q;
|
||||
wire [19:0] rightShiftStage1Idx3Rng12_uid77_rightShiferNoStickyOut_uid42_fpToFxPTest_b;
|
||||
wire [11:0] rightShiftStage1Idx3Pad12_uid78_rightShiferNoStickyOut_uid42_fpToFxPTest_q;
|
||||
wire [31:0] rightShiftStage1Idx3_uid79_rightShiferNoStickyOut_uid42_fpToFxPTest_q;
|
||||
wire [1:0] rightShiftStage1_uid81_rightShiferNoStickyOut_uid42_fpToFxPTest_s;
|
||||
reg [31:0] rightShiftStage1_uid81_rightShiferNoStickyOut_uid42_fpToFxPTest_q;
|
||||
wire [15:0] rightShiftStage2Idx1Rng16_uid82_rightShiferNoStickyOut_uid42_fpToFxPTest_b;
|
||||
wire [15:0] rightShiftStage2Idx1Pad16_uid83_rightShiferNoStickyOut_uid42_fpToFxPTest_q;
|
||||
wire [31:0] rightShiftStage2Idx1_uid84_rightShiferNoStickyOut_uid42_fpToFxPTest_q;
|
||||
wire [1:0] rightShiftStage2_uid88_rightShiferNoStickyOut_uid42_fpToFxPTest_s;
|
||||
reg [31:0] rightShiftStage2_uid88_rightShiferNoStickyOut_uid42_fpToFxPTest_q;
|
||||
wire [1:0] rightShiftStageSel0Dto0_uid69_rightShiferNoStickyOut_uid42_fpToFxPTest_merged_bit_select_b;
|
||||
wire [1:0] rightShiftStageSel0Dto0_uid69_rightShiferNoStickyOut_uid42_fpToFxPTest_merged_bit_select_c;
|
||||
wire [1:0] rightShiftStageSel0Dto0_uid69_rightShiferNoStickyOut_uid42_fpToFxPTest_merged_bit_select_d;
|
||||
reg [31:0] redist0_sPostRnd_uid49_fpToFxPTest_b_1_q;
|
||||
reg [0:0] redist1_udf_uid33_fpToFxPTest_n_3_q;
|
||||
reg [0:0] redist1_udf_uid33_fpToFxPTest_n_3_delay_0;
|
||||
reg [0:0] redist2_ovfExpRange_uid31_fpToFxPTest_n_3_q;
|
||||
reg [0:0] redist2_ovfExpRange_uid31_fpToFxPTest_n_3_delay_0;
|
||||
reg [0:0] redist3_signX_uid29_fpToFxPTest_q_3_q;
|
||||
reg [0:0] redist3_signX_uid29_fpToFxPTest_q_3_delay_0;
|
||||
reg [0:0] redist4_excN_x_uid16_fpToFxPTest_q_3_q;
|
||||
reg [0:0] redist4_excN_x_uid16_fpToFxPTest_q_3_delay_0;
|
||||
reg [0:0] redist4_excN_x_uid16_fpToFxPTest_q_3_delay_1;
|
||||
reg [0:0] redist5_excI_x_uid15_fpToFxPTest_q_3_q;
|
||||
reg [0:0] redist5_excI_x_uid15_fpToFxPTest_q_3_delay_0;
|
||||
|
||||
|
||||
// maxNegValueU_uid55_fpToFxPTest(CONSTANT,54)
|
||||
assign maxNegValueU_uid55_fpToFxPTest_q = 32'b00000000000000000000000000000000;
|
||||
|
||||
// maxNegValueS_uid44_fpToFxPTest(CONSTANT,43)
|
||||
assign maxNegValueS_uid44_fpToFxPTest_q = 32'b10000000000000000000000000000000;
|
||||
|
||||
// maxPosValueS_uid43_fpToFxPTest(CONSTANT,42)
|
||||
assign maxPosValueS_uid43_fpToFxPTest_q = 32'b01111111111111111111111111111111;
|
||||
|
||||
// d0_uid47_fpToFxPTest(CONSTANT,46)
|
||||
assign d0_uid47_fpToFxPTest_q = 3'b001;
|
||||
|
||||
// signX_uid27_fpToFxPTest(BITSELECT,26)@0
|
||||
assign signX_uid27_fpToFxPTest_b = a[31:31];
|
||||
|
||||
// frac_x_uid10_fpToFxPTest(BITSELECT,9)@0
|
||||
assign frac_x_uid10_fpToFxPTest_b = a[22:0];
|
||||
|
||||
// cstZeroWF_uid7_fpToFxPTest(CONSTANT,6)
|
||||
assign cstZeroWF_uid7_fpToFxPTest_q = 23'b00000000000000000000000;
|
||||
|
||||
// fracXIsZero_uid13_fpToFxPTest(LOGICAL,12)@0
|
||||
assign fracXIsZero_uid13_fpToFxPTest_q = cstZeroWF_uid7_fpToFxPTest_q == frac_x_uid10_fpToFxPTest_b ? 1'b1 : 1'b0;
|
||||
|
||||
// fracXIsNotZero_uid14_fpToFxPTest(LOGICAL,13)@0
|
||||
assign fracXIsNotZero_uid14_fpToFxPTest_q = ~ (fracXIsZero_uid13_fpToFxPTest_q);
|
||||
|
||||
// cstAllOWE_uid6_fpToFxPTest(CONSTANT,5)
|
||||
assign cstAllOWE_uid6_fpToFxPTest_q = 8'b11111111;
|
||||
|
||||
// exp_x_uid9_fpToFxPTest(BITSELECT,8)@0
|
||||
assign exp_x_uid9_fpToFxPTest_b = a[30:23];
|
||||
|
||||
// expXIsMax_uid12_fpToFxPTest(LOGICAL,11)@0
|
||||
assign expXIsMax_uid12_fpToFxPTest_q = exp_x_uid9_fpToFxPTest_b == cstAllOWE_uid6_fpToFxPTest_q ? 1'b1 : 1'b0;
|
||||
|
||||
// excN_x_uid16_fpToFxPTest(LOGICAL,15)@0
|
||||
assign excN_x_uid16_fpToFxPTest_q = expXIsMax_uid12_fpToFxPTest_q & fracXIsNotZero_uid14_fpToFxPTest_q;
|
||||
|
||||
// notNan_uid28_fpToFxPTest(LOGICAL,27)@0
|
||||
assign notNan_uid28_fpToFxPTest_q = ~ (excN_x_uid16_fpToFxPTest_q);
|
||||
|
||||
// signX_uid29_fpToFxPTest(LOGICAL,28)@0 + 1
|
||||
assign signX_uid29_fpToFxPTest_qi = notNan_uid28_fpToFxPTest_q & signX_uid27_fpToFxPTest_b;
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) )
|
||||
signX_uid29_fpToFxPTest_delay ( .xin(signX_uid29_fpToFxPTest_qi), .xout(signX_uid29_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// GND(CONSTANT,0)
|
||||
assign GND_q = 1'b0;
|
||||
|
||||
// rightShiftStage2Idx1Pad16_uid83_rightShiferNoStickyOut_uid42_fpToFxPTest(CONSTANT,82)
|
||||
assign rightShiftStage2Idx1Pad16_uid83_rightShiferNoStickyOut_uid42_fpToFxPTest_q = 16'b0000000000000000;
|
||||
|
||||
// rightShiftStage2Idx1Rng16_uid82_rightShiferNoStickyOut_uid42_fpToFxPTest(BITSELECT,81)@1
|
||||
assign rightShiftStage2Idx1Rng16_uid82_rightShiferNoStickyOut_uid42_fpToFxPTest_b = rightShiftStage1_uid81_rightShiferNoStickyOut_uid42_fpToFxPTest_q[31:16];
|
||||
|
||||
// rightShiftStage2Idx1_uid84_rightShiferNoStickyOut_uid42_fpToFxPTest(BITJOIN,83)@1
|
||||
assign rightShiftStage2Idx1_uid84_rightShiferNoStickyOut_uid42_fpToFxPTest_q = {rightShiftStage2Idx1Pad16_uid83_rightShiferNoStickyOut_uid42_fpToFxPTest_q, rightShiftStage2Idx1Rng16_uid82_rightShiferNoStickyOut_uid42_fpToFxPTest_b};
|
||||
|
||||
// rightShiftStage1Idx3Pad12_uid78_rightShiferNoStickyOut_uid42_fpToFxPTest(CONSTANT,77)
|
||||
assign rightShiftStage1Idx3Pad12_uid78_rightShiferNoStickyOut_uid42_fpToFxPTest_q = 12'b000000000000;
|
||||
|
||||
// rightShiftStage1Idx3Rng12_uid77_rightShiferNoStickyOut_uid42_fpToFxPTest(BITSELECT,76)@1
|
||||
assign rightShiftStage1Idx3Rng12_uid77_rightShiferNoStickyOut_uid42_fpToFxPTest_b = rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest_q[31:12];
|
||||
|
||||
// rightShiftStage1Idx3_uid79_rightShiferNoStickyOut_uid42_fpToFxPTest(BITJOIN,78)@1
|
||||
assign rightShiftStage1Idx3_uid79_rightShiferNoStickyOut_uid42_fpToFxPTest_q = {rightShiftStage1Idx3Pad12_uid78_rightShiferNoStickyOut_uid42_fpToFxPTest_q, rightShiftStage1Idx3Rng12_uid77_rightShiferNoStickyOut_uid42_fpToFxPTest_b};
|
||||
|
||||
// cstAllZWE_uid8_fpToFxPTest(CONSTANT,7)
|
||||
assign cstAllZWE_uid8_fpToFxPTest_q = 8'b00000000;
|
||||
|
||||
// rightShiftStage1Idx2Rng8_uid74_rightShiferNoStickyOut_uid42_fpToFxPTest(BITSELECT,73)@1
|
||||
assign rightShiftStage1Idx2Rng8_uid74_rightShiferNoStickyOut_uid42_fpToFxPTest_b = rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest_q[31:8];
|
||||
|
||||
// rightShiftStage1Idx2_uid76_rightShiferNoStickyOut_uid42_fpToFxPTest(BITJOIN,75)@1
|
||||
assign rightShiftStage1Idx2_uid76_rightShiferNoStickyOut_uid42_fpToFxPTest_q = {cstAllZWE_uid8_fpToFxPTest_q, rightShiftStage1Idx2Rng8_uid74_rightShiferNoStickyOut_uid42_fpToFxPTest_b};
|
||||
|
||||
// rightShiftStage1Idx1Pad4_uid72_rightShiferNoStickyOut_uid42_fpToFxPTest(CONSTANT,71)
|
||||
assign rightShiftStage1Idx1Pad4_uid72_rightShiferNoStickyOut_uid42_fpToFxPTest_q = 4'b0000;
|
||||
|
||||
// rightShiftStage1Idx1Rng4_uid71_rightShiferNoStickyOut_uid42_fpToFxPTest(BITSELECT,70)@1
|
||||
assign rightShiftStage1Idx1Rng4_uid71_rightShiferNoStickyOut_uid42_fpToFxPTest_b = rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest_q[31:4];
|
||||
|
||||
// rightShiftStage1Idx1_uid73_rightShiferNoStickyOut_uid42_fpToFxPTest(BITJOIN,72)@1
|
||||
assign rightShiftStage1Idx1_uid73_rightShiferNoStickyOut_uid42_fpToFxPTest_q = {rightShiftStage1Idx1Pad4_uid72_rightShiferNoStickyOut_uid42_fpToFxPTest_q, rightShiftStage1Idx1Rng4_uid71_rightShiferNoStickyOut_uid42_fpToFxPTest_b};
|
||||
|
||||
// rightShiftStage0Idx3Pad3_uid67_rightShiferNoStickyOut_uid42_fpToFxPTest(CONSTANT,66)
|
||||
assign rightShiftStage0Idx3Pad3_uid67_rightShiferNoStickyOut_uid42_fpToFxPTest_q = 3'b000;
|
||||
|
||||
// rightShiftStage0Idx3Rng3_uid66_rightShiferNoStickyOut_uid42_fpToFxPTest(BITSELECT,65)@1
|
||||
assign rightShiftStage0Idx3Rng3_uid66_rightShiferNoStickyOut_uid42_fpToFxPTest_b = shifterIn_uid41_fpToFxPTest_q[31:3];
|
||||
|
||||
// rightShiftStage0Idx3_uid68_rightShiferNoStickyOut_uid42_fpToFxPTest(BITJOIN,67)@1
|
||||
assign rightShiftStage0Idx3_uid68_rightShiferNoStickyOut_uid42_fpToFxPTest_q = {rightShiftStage0Idx3Pad3_uid67_rightShiferNoStickyOut_uid42_fpToFxPTest_q, rightShiftStage0Idx3Rng3_uid66_rightShiferNoStickyOut_uid42_fpToFxPTest_b};
|
||||
|
||||
// rightShiftStage0Idx2Pad2_uid64_rightShiferNoStickyOut_uid42_fpToFxPTest(CONSTANT,63)
|
||||
assign rightShiftStage0Idx2Pad2_uid64_rightShiferNoStickyOut_uid42_fpToFxPTest_q = 2'b00;
|
||||
|
||||
// rightShiftStage0Idx2Rng2_uid63_rightShiferNoStickyOut_uid42_fpToFxPTest(BITSELECT,62)@1
|
||||
assign rightShiftStage0Idx2Rng2_uid63_rightShiferNoStickyOut_uid42_fpToFxPTest_b = shifterIn_uid41_fpToFxPTest_q[31:2];
|
||||
|
||||
// rightShiftStage0Idx2_uid65_rightShiferNoStickyOut_uid42_fpToFxPTest(BITJOIN,64)@1
|
||||
assign rightShiftStage0Idx2_uid65_rightShiferNoStickyOut_uid42_fpToFxPTest_q = {rightShiftStage0Idx2Pad2_uid64_rightShiferNoStickyOut_uid42_fpToFxPTest_q, rightShiftStage0Idx2Rng2_uid63_rightShiferNoStickyOut_uid42_fpToFxPTest_b};
|
||||
|
||||
// rightShiftStage0Idx1Rng1_uid60_rightShiferNoStickyOut_uid42_fpToFxPTest(BITSELECT,59)@1
|
||||
assign rightShiftStage0Idx1Rng1_uid60_rightShiferNoStickyOut_uid42_fpToFxPTest_b = shifterIn_uid41_fpToFxPTest_q[31:1];
|
||||
|
||||
// rightShiftStage0Idx1_uid62_rightShiferNoStickyOut_uid42_fpToFxPTest(BITJOIN,61)@1
|
||||
assign rightShiftStage0Idx1_uid62_rightShiferNoStickyOut_uid42_fpToFxPTest_q = {GND_q, rightShiftStage0Idx1Rng1_uid60_rightShiferNoStickyOut_uid42_fpToFxPTest_b};
|
||||
|
||||
// excZ_x_uid11_fpToFxPTest(LOGICAL,10)@0
|
||||
assign excZ_x_uid11_fpToFxPTest_q = exp_x_uid9_fpToFxPTest_b == cstAllZWE_uid8_fpToFxPTest_q ? 1'b1 : 1'b0;
|
||||
|
||||
// invExcXZ_uid24_fpToFxPTest(LOGICAL,23)@0 + 1
|
||||
assign invExcXZ_uid24_fpToFxPTest_qi = ~ (excZ_x_uid11_fpToFxPTest_q);
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) )
|
||||
invExcXZ_uid24_fpToFxPTest_delay ( .xin(invExcXZ_uid24_fpToFxPTest_qi), .xout(invExcXZ_uid24_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// fracPostZ_uid23_fpToFxPTest(MUX,22)@0 + 1
|
||||
assign fracPostZ_uid23_fpToFxPTest_s = excZ_x_uid11_fpToFxPTest_q;
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
fracPostZ_uid23_fpToFxPTest_q <= 23'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
unique case (fracPostZ_uid23_fpToFxPTest_s)
|
||||
1'b0 : fracPostZ_uid23_fpToFxPTest_q <= frac_x_uid10_fpToFxPTest_b;
|
||||
1'b1 : fracPostZ_uid23_fpToFxPTest_q <= cstZeroWF_uid7_fpToFxPTest_q;
|
||||
default : fracPostZ_uid23_fpToFxPTest_q <= 23'b0;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// oFracX_uid25_fpToFxPTest(BITJOIN,24)@1
|
||||
assign oFracX_uid25_fpToFxPTest_q = {invExcXZ_uid24_fpToFxPTest_q, fracPostZ_uid23_fpToFxPTest_q};
|
||||
|
||||
// shifterIn_uid41_fpToFxPTest(BITJOIN,40)@1
|
||||
assign shifterIn_uid41_fpToFxPTest_q = {oFracX_uid25_fpToFxPTest_q, cstAllZWE_uid8_fpToFxPTest_q};
|
||||
|
||||
// rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest(MUX,69)@1
|
||||
assign rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest_s = rightShiftStageSel0Dto0_uid69_rightShiferNoStickyOut_uid42_fpToFxPTest_merged_bit_select_b;
|
||||
always @(rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest_s or en or shifterIn_uid41_fpToFxPTest_q or rightShiftStage0Idx1_uid62_rightShiferNoStickyOut_uid42_fpToFxPTest_q or rightShiftStage0Idx2_uid65_rightShiferNoStickyOut_uid42_fpToFxPTest_q or rightShiftStage0Idx3_uid68_rightShiferNoStickyOut_uid42_fpToFxPTest_q)
|
||||
begin
|
||||
unique case (rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest_s)
|
||||
2'b00 : rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest_q = shifterIn_uid41_fpToFxPTest_q;
|
||||
2'b01 : rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest_q = rightShiftStage0Idx1_uid62_rightShiferNoStickyOut_uid42_fpToFxPTest_q;
|
||||
2'b10 : rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest_q = rightShiftStage0Idx2_uid65_rightShiferNoStickyOut_uid42_fpToFxPTest_q;
|
||||
2'b11 : rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest_q = rightShiftStage0Idx3_uid68_rightShiferNoStickyOut_uid42_fpToFxPTest_q;
|
||||
default : rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest_q = 32'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// rightShiftStage1_uid81_rightShiferNoStickyOut_uid42_fpToFxPTest(MUX,80)@1
|
||||
assign rightShiftStage1_uid81_rightShiferNoStickyOut_uid42_fpToFxPTest_s = rightShiftStageSel0Dto0_uid69_rightShiferNoStickyOut_uid42_fpToFxPTest_merged_bit_select_c;
|
||||
always @(rightShiftStage1_uid81_rightShiferNoStickyOut_uid42_fpToFxPTest_s or en or rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest_q or rightShiftStage1Idx1_uid73_rightShiferNoStickyOut_uid42_fpToFxPTest_q or rightShiftStage1Idx2_uid76_rightShiferNoStickyOut_uid42_fpToFxPTest_q or rightShiftStage1Idx3_uid79_rightShiferNoStickyOut_uid42_fpToFxPTest_q)
|
||||
begin
|
||||
unique case (rightShiftStage1_uid81_rightShiferNoStickyOut_uid42_fpToFxPTest_s)
|
||||
2'b00 : rightShiftStage1_uid81_rightShiferNoStickyOut_uid42_fpToFxPTest_q = rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest_q;
|
||||
2'b01 : rightShiftStage1_uid81_rightShiferNoStickyOut_uid42_fpToFxPTest_q = rightShiftStage1Idx1_uid73_rightShiferNoStickyOut_uid42_fpToFxPTest_q;
|
||||
2'b10 : rightShiftStage1_uid81_rightShiferNoStickyOut_uid42_fpToFxPTest_q = rightShiftStage1Idx2_uid76_rightShiferNoStickyOut_uid42_fpToFxPTest_q;
|
||||
2'b11 : rightShiftStage1_uid81_rightShiferNoStickyOut_uid42_fpToFxPTest_q = rightShiftStage1Idx3_uid79_rightShiferNoStickyOut_uid42_fpToFxPTest_q;
|
||||
default : rightShiftStage1_uid81_rightShiferNoStickyOut_uid42_fpToFxPTest_q = 32'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// maxShiftCst_uid37_fpToFxPTest(CONSTANT,36)
|
||||
assign maxShiftCst_uid37_fpToFxPTest_q = 6'b100000;
|
||||
|
||||
// ovfExpVal_uid34_fpToFxPTest(CONSTANT,33)
|
||||
assign ovfExpVal_uid34_fpToFxPTest_q = 9'b010011101;
|
||||
|
||||
// shiftValE_uid35_fpToFxPTest(SUB,34)@0
|
||||
assign shiftValE_uid35_fpToFxPTest_a = {{2{ovfExpVal_uid34_fpToFxPTest_q[8]}}, ovfExpVal_uid34_fpToFxPTest_q};
|
||||
assign shiftValE_uid35_fpToFxPTest_b = {3'b000, exp_x_uid9_fpToFxPTest_b};
|
||||
assign shiftValE_uid35_fpToFxPTest_o = $signed(shiftValE_uid35_fpToFxPTest_a) - $signed(shiftValE_uid35_fpToFxPTest_b);
|
||||
assign shiftValE_uid35_fpToFxPTest_q = shiftValE_uid35_fpToFxPTest_o[9:0];
|
||||
|
||||
// shiftValRaw_uid36_fpToFxPTest(BITSELECT,35)@0
|
||||
assign shiftValRaw_uid36_fpToFxPTest_in = shiftValE_uid35_fpToFxPTest_q[5:0];
|
||||
assign shiftValRaw_uid36_fpToFxPTest_b = shiftValRaw_uid36_fpToFxPTest_in[5:0];
|
||||
|
||||
// shiftOutOfRange_uid38_fpToFxPTest(COMPARE,37)@0
|
||||
assign shiftOutOfRange_uid38_fpToFxPTest_a = {{2{shiftValE_uid35_fpToFxPTest_q[9]}}, shiftValE_uid35_fpToFxPTest_q};
|
||||
assign shiftOutOfRange_uid38_fpToFxPTest_b = {6'b000000, maxShiftCst_uid37_fpToFxPTest_q};
|
||||
assign shiftOutOfRange_uid38_fpToFxPTest_o = $signed(shiftOutOfRange_uid38_fpToFxPTest_a) - $signed(shiftOutOfRange_uid38_fpToFxPTest_b);
|
||||
assign shiftOutOfRange_uid38_fpToFxPTest_n[0] = ~ (shiftOutOfRange_uid38_fpToFxPTest_o[11]);
|
||||
|
||||
// shiftVal_uid39_fpToFxPTest(MUX,38)@0 + 1
|
||||
assign shiftVal_uid39_fpToFxPTest_s = shiftOutOfRange_uid38_fpToFxPTest_n;
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
shiftVal_uid39_fpToFxPTest_q <= 6'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
unique case (shiftVal_uid39_fpToFxPTest_s)
|
||||
1'b0 : shiftVal_uid39_fpToFxPTest_q <= shiftValRaw_uid36_fpToFxPTest_b;
|
||||
1'b1 : shiftVal_uid39_fpToFxPTest_q <= maxShiftCst_uid37_fpToFxPTest_q;
|
||||
default : shiftVal_uid39_fpToFxPTest_q <= 6'b0;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// rightShiftStageSel0Dto0_uid69_rightShiferNoStickyOut_uid42_fpToFxPTest_merged_bit_select(BITSELECT,89)@1
|
||||
assign rightShiftStageSel0Dto0_uid69_rightShiferNoStickyOut_uid42_fpToFxPTest_merged_bit_select_b = shiftVal_uid39_fpToFxPTest_q[1:0];
|
||||
assign rightShiftStageSel0Dto0_uid69_rightShiferNoStickyOut_uid42_fpToFxPTest_merged_bit_select_c = shiftVal_uid39_fpToFxPTest_q[3:2];
|
||||
assign rightShiftStageSel0Dto0_uid69_rightShiferNoStickyOut_uid42_fpToFxPTest_merged_bit_select_d = shiftVal_uid39_fpToFxPTest_q[5:4];
|
||||
|
||||
// rightShiftStage2_uid88_rightShiferNoStickyOut_uid42_fpToFxPTest(MUX,87)@1
|
||||
assign rightShiftStage2_uid88_rightShiferNoStickyOut_uid42_fpToFxPTest_s = rightShiftStageSel0Dto0_uid69_rightShiferNoStickyOut_uid42_fpToFxPTest_merged_bit_select_d;
|
||||
always @(rightShiftStage2_uid88_rightShiferNoStickyOut_uid42_fpToFxPTest_s or en or rightShiftStage1_uid81_rightShiferNoStickyOut_uid42_fpToFxPTest_q or rightShiftStage2Idx1_uid84_rightShiferNoStickyOut_uid42_fpToFxPTest_q or maxNegValueU_uid55_fpToFxPTest_q)
|
||||
begin
|
||||
unique case (rightShiftStage2_uid88_rightShiferNoStickyOut_uid42_fpToFxPTest_s)
|
||||
2'b00 : rightShiftStage2_uid88_rightShiferNoStickyOut_uid42_fpToFxPTest_q = rightShiftStage1_uid81_rightShiferNoStickyOut_uid42_fpToFxPTest_q;
|
||||
2'b01 : rightShiftStage2_uid88_rightShiferNoStickyOut_uid42_fpToFxPTest_q = rightShiftStage2Idx1_uid84_rightShiferNoStickyOut_uid42_fpToFxPTest_q;
|
||||
2'b10 : rightShiftStage2_uid88_rightShiferNoStickyOut_uid42_fpToFxPTest_q = maxNegValueU_uid55_fpToFxPTest_q;
|
||||
2'b11 : rightShiftStage2_uid88_rightShiferNoStickyOut_uid42_fpToFxPTest_q = maxNegValueU_uid55_fpToFxPTest_q;
|
||||
default : rightShiftStage2_uid88_rightShiferNoStickyOut_uid42_fpToFxPTest_q = 32'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// zRightShiferNoStickyOut_uid45_fpToFxPTest(BITJOIN,44)@1
|
||||
assign zRightShiferNoStickyOut_uid45_fpToFxPTest_q = {GND_q, rightShiftStage2_uid88_rightShiferNoStickyOut_uid42_fpToFxPTest_q};
|
||||
|
||||
// xXorSignE_uid46_fpToFxPTest(LOGICAL,45)@1 + 1
|
||||
assign xXorSignE_uid46_fpToFxPTest_b = {{32{signX_uid29_fpToFxPTest_q[0]}}, signX_uid29_fpToFxPTest_q};
|
||||
assign xXorSignE_uid46_fpToFxPTest_qi = zRightShiferNoStickyOut_uid45_fpToFxPTest_q ^ xXorSignE_uid46_fpToFxPTest_b;
|
||||
dspba_delay_ver #( .width(33), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) )
|
||||
xXorSignE_uid46_fpToFxPTest_delay ( .xin(xXorSignE_uid46_fpToFxPTest_qi), .xout(xXorSignE_uid46_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// sPostRndFull_uid48_fpToFxPTest(ADD,47)@2
|
||||
assign sPostRndFull_uid48_fpToFxPTest_a = {{1{xXorSignE_uid46_fpToFxPTest_q[32]}}, xXorSignE_uid46_fpToFxPTest_q};
|
||||
assign sPostRndFull_uid48_fpToFxPTest_b = {{31{d0_uid47_fpToFxPTest_q[2]}}, d0_uid47_fpToFxPTest_q};
|
||||
assign sPostRndFull_uid48_fpToFxPTest_o = $signed(sPostRndFull_uid48_fpToFxPTest_a) + $signed(sPostRndFull_uid48_fpToFxPTest_b);
|
||||
assign sPostRndFull_uid48_fpToFxPTest_q = sPostRndFull_uid48_fpToFxPTest_o[33:0];
|
||||
|
||||
// sPostRnd_uid49_fpToFxPTest(BITSELECT,48)@2
|
||||
assign sPostRnd_uid49_fpToFxPTest_in = sPostRndFull_uid48_fpToFxPTest_q[32:0];
|
||||
assign sPostRnd_uid49_fpToFxPTest_b = sPostRnd_uid49_fpToFxPTest_in[32:1];
|
||||
|
||||
// redist0_sPostRnd_uid49_fpToFxPTest_b_1(DELAY,90)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist0_sPostRnd_uid49_fpToFxPTest_b_1_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist0_sPostRnd_uid49_fpToFxPTest_b_1_q <= sPostRnd_uid49_fpToFxPTest_b;
|
||||
end
|
||||
end
|
||||
|
||||
// redist3_signX_uid29_fpToFxPTest_q_3(DELAY,93)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist3_signX_uid29_fpToFxPTest_q_3_delay_0 <= '0;
|
||||
redist3_signX_uid29_fpToFxPTest_q_3_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist3_signX_uid29_fpToFxPTest_q_3_delay_0 <= signX_uid29_fpToFxPTest_q;
|
||||
redist3_signX_uid29_fpToFxPTest_q_3_q <= redist3_signX_uid29_fpToFxPTest_q_3_delay_0;
|
||||
end
|
||||
end
|
||||
|
||||
// udfExpVal_uid32_fpToFxPTest(CONSTANT,31)
|
||||
assign udfExpVal_uid32_fpToFxPTest_q = 8'b01111101;
|
||||
|
||||
// udf_uid33_fpToFxPTest(COMPARE,32)@0 + 1
|
||||
assign udf_uid33_fpToFxPTest_a = {{3{udfExpVal_uid32_fpToFxPTest_q[7]}}, udfExpVal_uid32_fpToFxPTest_q};
|
||||
assign udf_uid33_fpToFxPTest_b = {3'b000, exp_x_uid9_fpToFxPTest_b};
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
udf_uid33_fpToFxPTest_o <= 11'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
udf_uid33_fpToFxPTest_o <= $signed(udf_uid33_fpToFxPTest_a) - $signed(udf_uid33_fpToFxPTest_b);
|
||||
end
|
||||
end
|
||||
assign udf_uid33_fpToFxPTest_n[0] = ~ (udf_uid33_fpToFxPTest_o[10]);
|
||||
|
||||
// redist1_udf_uid33_fpToFxPTest_n_3(DELAY,91)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist1_udf_uid33_fpToFxPTest_n_3_delay_0 <= '0;
|
||||
redist1_udf_uid33_fpToFxPTest_n_3_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist1_udf_uid33_fpToFxPTest_n_3_delay_0 <= udf_uid33_fpToFxPTest_n;
|
||||
redist1_udf_uid33_fpToFxPTest_n_3_q <= redist1_udf_uid33_fpToFxPTest_n_3_delay_0;
|
||||
end
|
||||
end
|
||||
|
||||
// sPostRnd_uid50_fpToFxPTest(BITSELECT,49)@2
|
||||
assign sPostRnd_uid50_fpToFxPTest_in = {{1{sPostRndFull_uid48_fpToFxPTest_q[33]}}, sPostRndFull_uid48_fpToFxPTest_q};
|
||||
assign sPostRnd_uid50_fpToFxPTest_b = sPostRnd_uid50_fpToFxPTest_in[34:1];
|
||||
|
||||
// rndOvfPos_uid51_fpToFxPTest(COMPARE,50)@2 + 1
|
||||
assign rndOvfPos_uid51_fpToFxPTest_a = {4'b0000, maxPosValueS_uid43_fpToFxPTest_q};
|
||||
assign rndOvfPos_uid51_fpToFxPTest_b = {{2{sPostRnd_uid50_fpToFxPTest_b[33]}}, sPostRnd_uid50_fpToFxPTest_b};
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
rndOvfPos_uid51_fpToFxPTest_o <= 36'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
rndOvfPos_uid51_fpToFxPTest_o <= $signed(rndOvfPos_uid51_fpToFxPTest_a) - $signed(rndOvfPos_uid51_fpToFxPTest_b);
|
||||
end
|
||||
end
|
||||
assign rndOvfPos_uid51_fpToFxPTest_c[0] = rndOvfPos_uid51_fpToFxPTest_o[35];
|
||||
|
||||
// ovfExpVal_uid30_fpToFxPTest(CONSTANT,29)
|
||||
assign ovfExpVal_uid30_fpToFxPTest_q = 9'b010011110;
|
||||
|
||||
// ovfExpRange_uid31_fpToFxPTest(COMPARE,30)@0 + 1
|
||||
assign ovfExpRange_uid31_fpToFxPTest_a = {3'b000, exp_x_uid9_fpToFxPTest_b};
|
||||
assign ovfExpRange_uid31_fpToFxPTest_b = {{2{ovfExpVal_uid30_fpToFxPTest_q[8]}}, ovfExpVal_uid30_fpToFxPTest_q};
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
ovfExpRange_uid31_fpToFxPTest_o <= 11'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
ovfExpRange_uid31_fpToFxPTest_o <= $signed(ovfExpRange_uid31_fpToFxPTest_a) - $signed(ovfExpRange_uid31_fpToFxPTest_b);
|
||||
end
|
||||
end
|
||||
assign ovfExpRange_uid31_fpToFxPTest_n[0] = ~ (ovfExpRange_uid31_fpToFxPTest_o[10]);
|
||||
|
||||
// redist2_ovfExpRange_uid31_fpToFxPTest_n_3(DELAY,92)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist2_ovfExpRange_uid31_fpToFxPTest_n_3_delay_0 <= '0;
|
||||
redist2_ovfExpRange_uid31_fpToFxPTest_n_3_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist2_ovfExpRange_uid31_fpToFxPTest_n_3_delay_0 <= ovfExpRange_uid31_fpToFxPTest_n;
|
||||
redist2_ovfExpRange_uid31_fpToFxPTest_n_3_q <= redist2_ovfExpRange_uid31_fpToFxPTest_n_3_delay_0;
|
||||
end
|
||||
end
|
||||
|
||||
// excI_x_uid15_fpToFxPTest(LOGICAL,14)@0 + 1
|
||||
assign excI_x_uid15_fpToFxPTest_qi = expXIsMax_uid12_fpToFxPTest_q & fracXIsZero_uid13_fpToFxPTest_q;
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) )
|
||||
excI_x_uid15_fpToFxPTest_delay ( .xin(excI_x_uid15_fpToFxPTest_qi), .xout(excI_x_uid15_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// redist5_excI_x_uid15_fpToFxPTest_q_3(DELAY,95)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist5_excI_x_uid15_fpToFxPTest_q_3_delay_0 <= '0;
|
||||
redist5_excI_x_uid15_fpToFxPTest_q_3_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist5_excI_x_uid15_fpToFxPTest_q_3_delay_0 <= excI_x_uid15_fpToFxPTest_q;
|
||||
redist5_excI_x_uid15_fpToFxPTest_q_3_q <= redist5_excI_x_uid15_fpToFxPTest_q_3_delay_0;
|
||||
end
|
||||
end
|
||||
|
||||
// redist4_excN_x_uid16_fpToFxPTest_q_3(DELAY,94)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist4_excN_x_uid16_fpToFxPTest_q_3_delay_0 <= '0;
|
||||
redist4_excN_x_uid16_fpToFxPTest_q_3_delay_1 <= '0;
|
||||
redist4_excN_x_uid16_fpToFxPTest_q_3_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist4_excN_x_uid16_fpToFxPTest_q_3_delay_0 <= excN_x_uid16_fpToFxPTest_q;
|
||||
redist4_excN_x_uid16_fpToFxPTest_q_3_delay_1 <= redist4_excN_x_uid16_fpToFxPTest_q_3_delay_0;
|
||||
redist4_excN_x_uid16_fpToFxPTest_q_3_q <= redist4_excN_x_uid16_fpToFxPTest_q_3_delay_1;
|
||||
end
|
||||
end
|
||||
|
||||
// ovfPostRnd_uid52_fpToFxPTest(LOGICAL,51)@3
|
||||
assign ovfPostRnd_uid52_fpToFxPTest_q = redist4_excN_x_uid16_fpToFxPTest_q_3_q | redist5_excI_x_uid15_fpToFxPTest_q_3_q | redist2_ovfExpRange_uid31_fpToFxPTest_n_3_q | rndOvfPos_uid51_fpToFxPTest_c;
|
||||
|
||||
// muxSelConc_uid53_fpToFxPTest(BITJOIN,52)@3
|
||||
assign muxSelConc_uid53_fpToFxPTest_q = {redist3_signX_uid29_fpToFxPTest_q_3_q, redist1_udf_uid33_fpToFxPTest_n_3_q, ovfPostRnd_uid52_fpToFxPTest_q};
|
||||
|
||||
// muxSel_uid54_fpToFxPTest(LOOKUP,53)@3
|
||||
always @(muxSelConc_uid53_fpToFxPTest_q)
|
||||
begin
|
||||
// Begin reserved scope level
|
||||
unique case (muxSelConc_uid53_fpToFxPTest_q)
|
||||
3'b000 : muxSel_uid54_fpToFxPTest_q = 2'b00;
|
||||
3'b001 : muxSel_uid54_fpToFxPTest_q = 2'b01;
|
||||
3'b010 : muxSel_uid54_fpToFxPTest_q = 2'b11;
|
||||
3'b011 : muxSel_uid54_fpToFxPTest_q = 2'b11;
|
||||
3'b100 : muxSel_uid54_fpToFxPTest_q = 2'b00;
|
||||
3'b101 : muxSel_uid54_fpToFxPTest_q = 2'b10;
|
||||
3'b110 : muxSel_uid54_fpToFxPTest_q = 2'b11;
|
||||
3'b111 : muxSel_uid54_fpToFxPTest_q = 2'b11;
|
||||
default : begin
|
||||
// unreachable
|
||||
muxSel_uid54_fpToFxPTest_q = 2'bxx;
|
||||
end
|
||||
endcase
|
||||
// End reserved scope level
|
||||
end
|
||||
|
||||
// finalOut_uid56_fpToFxPTest(MUX,55)@3
|
||||
assign finalOut_uid56_fpToFxPTest_s = muxSel_uid54_fpToFxPTest_q;
|
||||
always @(finalOut_uid56_fpToFxPTest_s or en or redist0_sPostRnd_uid49_fpToFxPTest_b_1_q or maxPosValueS_uid43_fpToFxPTest_q or maxNegValueS_uid44_fpToFxPTest_q or maxNegValueU_uid55_fpToFxPTest_q)
|
||||
begin
|
||||
unique case (finalOut_uid56_fpToFxPTest_s)
|
||||
2'b00 : finalOut_uid56_fpToFxPTest_q = redist0_sPostRnd_uid49_fpToFxPTest_b_1_q;
|
||||
2'b01 : finalOut_uid56_fpToFxPTest_q = maxPosValueS_uid43_fpToFxPTest_q;
|
||||
2'b10 : finalOut_uid56_fpToFxPTest_q = maxNegValueS_uid44_fpToFxPTest_q;
|
||||
2'b11 : finalOut_uid56_fpToFxPTest_q = maxNegValueU_uid55_fpToFxPTest_q;
|
||||
default : finalOut_uid56_fpToFxPTest_q = 32'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// xOut(GPOUT,4)@3
|
||||
assign q = finalOut_uid56_fpToFxPTest_q;
|
||||
|
||||
endmodule
|
||||
@@ -1,563 +0,0 @@
|
||||
// -------------------------------------------------------------------------
|
||||
// High Level Design Compiler for Intel(R) FPGAs Version 18.1 (Release Build #277)
|
||||
// Quartus Prime development tool and MATLAB/Simulink Interface
|
||||
//
|
||||
// Legal Notice: Copyright 2019 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly
|
||||
// subject to the terms and conditions of the Intel FPGA Software License
|
||||
// Agreement, Intel MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for
|
||||
// the sole purpose of programming logic devices manufactured by Intel
|
||||
// and sold by Intel or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
// ---------------------------------------------------------------------------
|
||||
|
||||
// SystemVerilog created from acl_ftou
|
||||
// SystemVerilog created on Sun Dec 27 09:48:58 2020
|
||||
|
||||
|
||||
(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
|
||||
module acl_ftou (
|
||||
input wire [31:0] a,
|
||||
input wire [0:0] en,
|
||||
output wire [31:0] q,
|
||||
input wire clk,
|
||||
input wire areset
|
||||
);
|
||||
|
||||
wire [0:0] GND_q;
|
||||
wire [0:0] VCC_q;
|
||||
wire [7:0] cstAllOWE_uid6_fpToFxPTest_q;
|
||||
wire [22:0] cstZeroWF_uid7_fpToFxPTest_q;
|
||||
wire [7:0] cstAllZWE_uid8_fpToFxPTest_q;
|
||||
wire [7:0] exp_x_uid9_fpToFxPTest_b;
|
||||
wire [22:0] frac_x_uid10_fpToFxPTest_b;
|
||||
wire [0:0] excZ_x_uid11_fpToFxPTest_qi;
|
||||
reg [0:0] excZ_x_uid11_fpToFxPTest_q;
|
||||
wire [0:0] expXIsMax_uid12_fpToFxPTest_qi;
|
||||
reg [0:0] expXIsMax_uid12_fpToFxPTest_q;
|
||||
wire [0:0] fracXIsZero_uid13_fpToFxPTest_q;
|
||||
wire [0:0] fracXIsNotZero_uid14_fpToFxPTest_q;
|
||||
wire [0:0] excI_x_uid15_fpToFxPTest_qi;
|
||||
reg [0:0] excI_x_uid15_fpToFxPTest_q;
|
||||
wire [0:0] excN_x_uid16_fpToFxPTest_q;
|
||||
wire [0:0] fracPostZ_uid23_fpToFxPTest_s;
|
||||
reg [22:0] fracPostZ_uid23_fpToFxPTest_q;
|
||||
wire [0:0] invExcXZ_uid24_fpToFxPTest_q;
|
||||
wire [23:0] oFracX_uid25_fpToFxPTest_q;
|
||||
wire [0:0] signX_uid27_fpToFxPTest_b;
|
||||
wire [0:0] notNan_uid28_fpToFxPTest_q;
|
||||
wire [0:0] signX_uid29_fpToFxPTest_qi;
|
||||
reg [0:0] signX_uid29_fpToFxPTest_q;
|
||||
wire [8:0] ovfExpVal_uid30_fpToFxPTest_q;
|
||||
wire [10:0] ovf_uid31_fpToFxPTest_a;
|
||||
wire [10:0] ovf_uid31_fpToFxPTest_b;
|
||||
logic [10:0] ovf_uid31_fpToFxPTest_o;
|
||||
wire [0:0] ovf_uid31_fpToFxPTest_n;
|
||||
wire [0:0] negOrOvf_uid32_fpToFxPTest_q;
|
||||
wire [7:0] udfExpVal_uid33_fpToFxPTest_q;
|
||||
wire [10:0] udf_uid34_fpToFxPTest_a;
|
||||
wire [10:0] udf_uid34_fpToFxPTest_b;
|
||||
logic [10:0] udf_uid34_fpToFxPTest_o;
|
||||
wire [0:0] udf_uid34_fpToFxPTest_n;
|
||||
wire [8:0] ovfExpVal_uid35_fpToFxPTest_q;
|
||||
wire [10:0] shiftValE_uid36_fpToFxPTest_a;
|
||||
wire [10:0] shiftValE_uid36_fpToFxPTest_b;
|
||||
logic [10:0] shiftValE_uid36_fpToFxPTest_o;
|
||||
wire [9:0] shiftValE_uid36_fpToFxPTest_q;
|
||||
wire [5:0] shiftValRaw_uid37_fpToFxPTest_in;
|
||||
wire [5:0] shiftValRaw_uid37_fpToFxPTest_b;
|
||||
wire [5:0] maxShiftCst_uid38_fpToFxPTest_q;
|
||||
wire [11:0] shiftOutOfRange_uid39_fpToFxPTest_a;
|
||||
wire [11:0] shiftOutOfRange_uid39_fpToFxPTest_b;
|
||||
logic [11:0] shiftOutOfRange_uid39_fpToFxPTest_o;
|
||||
wire [0:0] shiftOutOfRange_uid39_fpToFxPTest_n;
|
||||
wire [0:0] shiftVal_uid40_fpToFxPTest_s;
|
||||
reg [5:0] shiftVal_uid40_fpToFxPTest_q;
|
||||
wire [8:0] zPadd_uid41_fpToFxPTest_q;
|
||||
wire [32:0] shifterIn_uid42_fpToFxPTest_q;
|
||||
wire [31:0] maxPosValueU_uid44_fpToFxPTest_q;
|
||||
wire [31:0] maxNegValueU_uid45_fpToFxPTest_q;
|
||||
wire [33:0] zRightShiferNoStickyOut_uid47_fpToFxPTest_q;
|
||||
wire [34:0] sPostRndFull_uid48_fpToFxPTest_a;
|
||||
wire [34:0] sPostRndFull_uid48_fpToFxPTest_b;
|
||||
logic [34:0] sPostRndFull_uid48_fpToFxPTest_o;
|
||||
wire [34:0] sPostRndFull_uid48_fpToFxPTest_q;
|
||||
wire [32:0] sPostRnd_uid49_fpToFxPTest_in;
|
||||
wire [31:0] sPostRnd_uid49_fpToFxPTest_b;
|
||||
wire [33:0] sPostRndFullMSBU_uid50_fpToFxPTest_in;
|
||||
wire [0:0] sPostRndFullMSBU_uid50_fpToFxPTest_b;
|
||||
wire [0:0] ovfPostRnd_uid51_fpToFxPTest_q;
|
||||
wire [2:0] muxSelConc_uid52_fpToFxPTest_q;
|
||||
reg [1:0] muxSel_uid53_fpToFxPTest_q;
|
||||
wire [1:0] finalOut_uid55_fpToFxPTest_s;
|
||||
reg [31:0] finalOut_uid55_fpToFxPTest_q;
|
||||
wire [31:0] rightShiftStage0Idx1Rng1_uid59_rightShiferNoStickyOut_uid43_fpToFxPTest_b;
|
||||
wire [32:0] rightShiftStage0Idx1_uid61_rightShiferNoStickyOut_uid43_fpToFxPTest_q;
|
||||
wire [30:0] rightShiftStage0Idx2Rng2_uid62_rightShiferNoStickyOut_uid43_fpToFxPTest_b;
|
||||
wire [1:0] rightShiftStage0Idx2Pad2_uid63_rightShiferNoStickyOut_uid43_fpToFxPTest_q;
|
||||
wire [32:0] rightShiftStage0Idx2_uid64_rightShiferNoStickyOut_uid43_fpToFxPTest_q;
|
||||
wire [29:0] rightShiftStage0Idx3Rng3_uid65_rightShiferNoStickyOut_uid43_fpToFxPTest_b;
|
||||
wire [2:0] rightShiftStage0Idx3Pad3_uid66_rightShiferNoStickyOut_uid43_fpToFxPTest_q;
|
||||
wire [32:0] rightShiftStage0Idx3_uid67_rightShiferNoStickyOut_uid43_fpToFxPTest_q;
|
||||
wire [1:0] rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest_s;
|
||||
reg [32:0] rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest_q;
|
||||
wire [28:0] rightShiftStage1Idx1Rng4_uid70_rightShiferNoStickyOut_uid43_fpToFxPTest_b;
|
||||
wire [3:0] rightShiftStage1Idx1Pad4_uid71_rightShiferNoStickyOut_uid43_fpToFxPTest_q;
|
||||
wire [32:0] rightShiftStage1Idx1_uid72_rightShiferNoStickyOut_uid43_fpToFxPTest_q;
|
||||
wire [24:0] rightShiftStage1Idx2Rng8_uid73_rightShiferNoStickyOut_uid43_fpToFxPTest_b;
|
||||
wire [32:0] rightShiftStage1Idx2_uid75_rightShiferNoStickyOut_uid43_fpToFxPTest_q;
|
||||
wire [20:0] rightShiftStage1Idx3Rng12_uid76_rightShiferNoStickyOut_uid43_fpToFxPTest_b;
|
||||
wire [11:0] rightShiftStage1Idx3Pad12_uid77_rightShiferNoStickyOut_uid43_fpToFxPTest_q;
|
||||
wire [32:0] rightShiftStage1Idx3_uid78_rightShiferNoStickyOut_uid43_fpToFxPTest_q;
|
||||
wire [1:0] rightShiftStage1_uid80_rightShiferNoStickyOut_uid43_fpToFxPTest_s;
|
||||
reg [32:0] rightShiftStage1_uid80_rightShiferNoStickyOut_uid43_fpToFxPTest_q;
|
||||
wire [16:0] rightShiftStage2Idx1Rng16_uid81_rightShiferNoStickyOut_uid43_fpToFxPTest_b;
|
||||
wire [15:0] rightShiftStage2Idx1Pad16_uid82_rightShiferNoStickyOut_uid43_fpToFxPTest_q;
|
||||
wire [32:0] rightShiftStage2Idx1_uid83_rightShiferNoStickyOut_uid43_fpToFxPTest_q;
|
||||
wire [0:0] rightShiftStage2Idx2Rng32_uid84_rightShiferNoStickyOut_uid43_fpToFxPTest_b;
|
||||
wire [32:0] rightShiftStage2Idx2_uid86_rightShiferNoStickyOut_uid43_fpToFxPTest_q;
|
||||
wire [32:0] rightShiftStage2Idx3_uid87_rightShiferNoStickyOut_uid43_fpToFxPTest_q;
|
||||
wire [1:0] rightShiftStage2_uid89_rightShiferNoStickyOut_uid43_fpToFxPTest_s;
|
||||
reg [32:0] rightShiftStage2_uid89_rightShiferNoStickyOut_uid43_fpToFxPTest_q;
|
||||
wire [1:0] rightShiftStageSel0Dto0_uid68_rightShiferNoStickyOut_uid43_fpToFxPTest_merged_bit_select_b;
|
||||
wire [1:0] rightShiftStageSel0Dto0_uid68_rightShiferNoStickyOut_uid43_fpToFxPTest_merged_bit_select_c;
|
||||
wire [1:0] rightShiftStageSel0Dto0_uid68_rightShiferNoStickyOut_uid43_fpToFxPTest_merged_bit_select_d;
|
||||
reg [31:0] redist0_sPostRnd_uid49_fpToFxPTest_b_1_q;
|
||||
reg [0:0] redist1_udf_uid34_fpToFxPTest_n_2_q;
|
||||
reg [0:0] redist2_ovf_uid31_fpToFxPTest_n_2_q;
|
||||
reg [0:0] redist3_signX_uid27_fpToFxPTest_b_1_q;
|
||||
reg [0:0] redist4_excN_x_uid16_fpToFxPTest_q_1_q;
|
||||
reg [22:0] redist5_frac_x_uid10_fpToFxPTest_b_1_q;
|
||||
|
||||
|
||||
// maxNegValueU_uid45_fpToFxPTest(CONSTANT,44)
|
||||
assign maxNegValueU_uid45_fpToFxPTest_q = 32'b00000000000000000000000000000000;
|
||||
|
||||
// maxPosValueU_uid44_fpToFxPTest(CONSTANT,43)
|
||||
assign maxPosValueU_uid44_fpToFxPTest_q = 32'b11111111111111111111111111111111;
|
||||
|
||||
// VCC(CONSTANT,1)
|
||||
assign VCC_q = 1'b1;
|
||||
|
||||
// GND(CONSTANT,0)
|
||||
assign GND_q = 1'b0;
|
||||
|
||||
// rightShiftStage2Idx3_uid87_rightShiferNoStickyOut_uid43_fpToFxPTest(CONSTANT,86)
|
||||
assign rightShiftStage2Idx3_uid87_rightShiferNoStickyOut_uid43_fpToFxPTest_q = 33'b000000000000000000000000000000000;
|
||||
|
||||
// rightShiftStage2Idx2Rng32_uid84_rightShiferNoStickyOut_uid43_fpToFxPTest(BITSELECT,83)@1
|
||||
assign rightShiftStage2Idx2Rng32_uid84_rightShiferNoStickyOut_uid43_fpToFxPTest_b = rightShiftStage1_uid80_rightShiferNoStickyOut_uid43_fpToFxPTest_q[32:32];
|
||||
|
||||
// rightShiftStage2Idx2_uid86_rightShiferNoStickyOut_uid43_fpToFxPTest(BITJOIN,85)@1
|
||||
assign rightShiftStage2Idx2_uid86_rightShiferNoStickyOut_uid43_fpToFxPTest_q = {maxNegValueU_uid45_fpToFxPTest_q, rightShiftStage2Idx2Rng32_uid84_rightShiferNoStickyOut_uid43_fpToFxPTest_b};
|
||||
|
||||
// rightShiftStage2Idx1Pad16_uid82_rightShiferNoStickyOut_uid43_fpToFxPTest(CONSTANT,81)
|
||||
assign rightShiftStage2Idx1Pad16_uid82_rightShiferNoStickyOut_uid43_fpToFxPTest_q = 16'b0000000000000000;
|
||||
|
||||
// rightShiftStage2Idx1Rng16_uid81_rightShiferNoStickyOut_uid43_fpToFxPTest(BITSELECT,80)@1
|
||||
assign rightShiftStage2Idx1Rng16_uid81_rightShiferNoStickyOut_uid43_fpToFxPTest_b = rightShiftStage1_uid80_rightShiferNoStickyOut_uid43_fpToFxPTest_q[32:16];
|
||||
|
||||
// rightShiftStage2Idx1_uid83_rightShiferNoStickyOut_uid43_fpToFxPTest(BITJOIN,82)@1
|
||||
assign rightShiftStage2Idx1_uid83_rightShiferNoStickyOut_uid43_fpToFxPTest_q = {rightShiftStage2Idx1Pad16_uid82_rightShiferNoStickyOut_uid43_fpToFxPTest_q, rightShiftStage2Idx1Rng16_uid81_rightShiferNoStickyOut_uid43_fpToFxPTest_b};
|
||||
|
||||
// rightShiftStage1Idx3Pad12_uid77_rightShiferNoStickyOut_uid43_fpToFxPTest(CONSTANT,76)
|
||||
assign rightShiftStage1Idx3Pad12_uid77_rightShiferNoStickyOut_uid43_fpToFxPTest_q = 12'b000000000000;
|
||||
|
||||
// rightShiftStage1Idx3Rng12_uid76_rightShiferNoStickyOut_uid43_fpToFxPTest(BITSELECT,75)@1
|
||||
assign rightShiftStage1Idx3Rng12_uid76_rightShiferNoStickyOut_uid43_fpToFxPTest_b = rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest_q[32:12];
|
||||
|
||||
// rightShiftStage1Idx3_uid78_rightShiferNoStickyOut_uid43_fpToFxPTest(BITJOIN,77)@1
|
||||
assign rightShiftStage1Idx3_uid78_rightShiferNoStickyOut_uid43_fpToFxPTest_q = {rightShiftStage1Idx3Pad12_uid77_rightShiferNoStickyOut_uid43_fpToFxPTest_q, rightShiftStage1Idx3Rng12_uid76_rightShiferNoStickyOut_uid43_fpToFxPTest_b};
|
||||
|
||||
// cstAllZWE_uid8_fpToFxPTest(CONSTANT,7)
|
||||
assign cstAllZWE_uid8_fpToFxPTest_q = 8'b00000000;
|
||||
|
||||
// rightShiftStage1Idx2Rng8_uid73_rightShiferNoStickyOut_uid43_fpToFxPTest(BITSELECT,72)@1
|
||||
assign rightShiftStage1Idx2Rng8_uid73_rightShiferNoStickyOut_uid43_fpToFxPTest_b = rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest_q[32:8];
|
||||
|
||||
// rightShiftStage1Idx2_uid75_rightShiferNoStickyOut_uid43_fpToFxPTest(BITJOIN,74)@1
|
||||
assign rightShiftStage1Idx2_uid75_rightShiferNoStickyOut_uid43_fpToFxPTest_q = {cstAllZWE_uid8_fpToFxPTest_q, rightShiftStage1Idx2Rng8_uid73_rightShiferNoStickyOut_uid43_fpToFxPTest_b};
|
||||
|
||||
// rightShiftStage1Idx1Pad4_uid71_rightShiferNoStickyOut_uid43_fpToFxPTest(CONSTANT,70)
|
||||
assign rightShiftStage1Idx1Pad4_uid71_rightShiferNoStickyOut_uid43_fpToFxPTest_q = 4'b0000;
|
||||
|
||||
// rightShiftStage1Idx1Rng4_uid70_rightShiferNoStickyOut_uid43_fpToFxPTest(BITSELECT,69)@1
|
||||
assign rightShiftStage1Idx1Rng4_uid70_rightShiferNoStickyOut_uid43_fpToFxPTest_b = rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest_q[32:4];
|
||||
|
||||
// rightShiftStage1Idx1_uid72_rightShiferNoStickyOut_uid43_fpToFxPTest(BITJOIN,71)@1
|
||||
assign rightShiftStage1Idx1_uid72_rightShiferNoStickyOut_uid43_fpToFxPTest_q = {rightShiftStage1Idx1Pad4_uid71_rightShiferNoStickyOut_uid43_fpToFxPTest_q, rightShiftStage1Idx1Rng4_uid70_rightShiferNoStickyOut_uid43_fpToFxPTest_b};
|
||||
|
||||
// rightShiftStage0Idx3Pad3_uid66_rightShiferNoStickyOut_uid43_fpToFxPTest(CONSTANT,65)
|
||||
assign rightShiftStage0Idx3Pad3_uid66_rightShiferNoStickyOut_uid43_fpToFxPTest_q = 3'b000;
|
||||
|
||||
// rightShiftStage0Idx3Rng3_uid65_rightShiferNoStickyOut_uid43_fpToFxPTest(BITSELECT,64)@1
|
||||
assign rightShiftStage0Idx3Rng3_uid65_rightShiferNoStickyOut_uid43_fpToFxPTest_b = shifterIn_uid42_fpToFxPTest_q[32:3];
|
||||
|
||||
// rightShiftStage0Idx3_uid67_rightShiferNoStickyOut_uid43_fpToFxPTest(BITJOIN,66)@1
|
||||
assign rightShiftStage0Idx3_uid67_rightShiferNoStickyOut_uid43_fpToFxPTest_q = {rightShiftStage0Idx3Pad3_uid66_rightShiferNoStickyOut_uid43_fpToFxPTest_q, rightShiftStage0Idx3Rng3_uid65_rightShiferNoStickyOut_uid43_fpToFxPTest_b};
|
||||
|
||||
// rightShiftStage0Idx2Pad2_uid63_rightShiferNoStickyOut_uid43_fpToFxPTest(CONSTANT,62)
|
||||
assign rightShiftStage0Idx2Pad2_uid63_rightShiferNoStickyOut_uid43_fpToFxPTest_q = 2'b00;
|
||||
|
||||
// rightShiftStage0Idx2Rng2_uid62_rightShiferNoStickyOut_uid43_fpToFxPTest(BITSELECT,61)@1
|
||||
assign rightShiftStage0Idx2Rng2_uid62_rightShiferNoStickyOut_uid43_fpToFxPTest_b = shifterIn_uid42_fpToFxPTest_q[32:2];
|
||||
|
||||
// rightShiftStage0Idx2_uid64_rightShiferNoStickyOut_uid43_fpToFxPTest(BITJOIN,63)@1
|
||||
assign rightShiftStage0Idx2_uid64_rightShiferNoStickyOut_uid43_fpToFxPTest_q = {rightShiftStage0Idx2Pad2_uid63_rightShiferNoStickyOut_uid43_fpToFxPTest_q, rightShiftStage0Idx2Rng2_uid62_rightShiferNoStickyOut_uid43_fpToFxPTest_b};
|
||||
|
||||
// rightShiftStage0Idx1Rng1_uid59_rightShiferNoStickyOut_uid43_fpToFxPTest(BITSELECT,58)@1
|
||||
assign rightShiftStage0Idx1Rng1_uid59_rightShiferNoStickyOut_uid43_fpToFxPTest_b = shifterIn_uid42_fpToFxPTest_q[32:1];
|
||||
|
||||
// rightShiftStage0Idx1_uid61_rightShiferNoStickyOut_uid43_fpToFxPTest(BITJOIN,60)@1
|
||||
assign rightShiftStage0Idx1_uid61_rightShiferNoStickyOut_uid43_fpToFxPTest_q = {GND_q, rightShiftStage0Idx1Rng1_uid59_rightShiferNoStickyOut_uid43_fpToFxPTest_b};
|
||||
|
||||
// exp_x_uid9_fpToFxPTest(BITSELECT,8)@0
|
||||
assign exp_x_uid9_fpToFxPTest_b = a[30:23];
|
||||
|
||||
// excZ_x_uid11_fpToFxPTest(LOGICAL,10)@0 + 1
|
||||
assign excZ_x_uid11_fpToFxPTest_qi = exp_x_uid9_fpToFxPTest_b == cstAllZWE_uid8_fpToFxPTest_q ? 1'b1 : 1'b0;
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) )
|
||||
excZ_x_uid11_fpToFxPTest_delay ( .xin(excZ_x_uid11_fpToFxPTest_qi), .xout(excZ_x_uid11_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// invExcXZ_uid24_fpToFxPTest(LOGICAL,23)@1
|
||||
assign invExcXZ_uid24_fpToFxPTest_q = ~ (excZ_x_uid11_fpToFxPTest_q);
|
||||
|
||||
// cstZeroWF_uid7_fpToFxPTest(CONSTANT,6)
|
||||
assign cstZeroWF_uid7_fpToFxPTest_q = 23'b00000000000000000000000;
|
||||
|
||||
// frac_x_uid10_fpToFxPTest(BITSELECT,9)@0
|
||||
assign frac_x_uid10_fpToFxPTest_b = a[22:0];
|
||||
|
||||
// redist5_frac_x_uid10_fpToFxPTest_b_1(DELAY,96)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist5_frac_x_uid10_fpToFxPTest_b_1_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist5_frac_x_uid10_fpToFxPTest_b_1_q <= frac_x_uid10_fpToFxPTest_b;
|
||||
end
|
||||
end
|
||||
|
||||
// fracPostZ_uid23_fpToFxPTest(MUX,22)@1
|
||||
assign fracPostZ_uid23_fpToFxPTest_s = excZ_x_uid11_fpToFxPTest_q;
|
||||
always @(fracPostZ_uid23_fpToFxPTest_s or en or redist5_frac_x_uid10_fpToFxPTest_b_1_q or cstZeroWF_uid7_fpToFxPTest_q)
|
||||
begin
|
||||
unique case (fracPostZ_uid23_fpToFxPTest_s)
|
||||
1'b0 : fracPostZ_uid23_fpToFxPTest_q = redist5_frac_x_uid10_fpToFxPTest_b_1_q;
|
||||
1'b1 : fracPostZ_uid23_fpToFxPTest_q = cstZeroWF_uid7_fpToFxPTest_q;
|
||||
default : fracPostZ_uid23_fpToFxPTest_q = 23'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// oFracX_uid25_fpToFxPTest(BITJOIN,24)@1
|
||||
assign oFracX_uid25_fpToFxPTest_q = {invExcXZ_uid24_fpToFxPTest_q, fracPostZ_uid23_fpToFxPTest_q};
|
||||
|
||||
// zPadd_uid41_fpToFxPTest(CONSTANT,40)
|
||||
assign zPadd_uid41_fpToFxPTest_q = 9'b000000000;
|
||||
|
||||
// shifterIn_uid42_fpToFxPTest(BITJOIN,41)@1
|
||||
assign shifterIn_uid42_fpToFxPTest_q = {oFracX_uid25_fpToFxPTest_q, zPadd_uid41_fpToFxPTest_q};
|
||||
|
||||
// rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest(MUX,68)@1
|
||||
assign rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest_s = rightShiftStageSel0Dto0_uid68_rightShiferNoStickyOut_uid43_fpToFxPTest_merged_bit_select_b;
|
||||
always @(rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest_s or en or shifterIn_uid42_fpToFxPTest_q or rightShiftStage0Idx1_uid61_rightShiferNoStickyOut_uid43_fpToFxPTest_q or rightShiftStage0Idx2_uid64_rightShiferNoStickyOut_uid43_fpToFxPTest_q or rightShiftStage0Idx3_uid67_rightShiferNoStickyOut_uid43_fpToFxPTest_q)
|
||||
begin
|
||||
unique case (rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest_s)
|
||||
2'b00 : rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest_q = shifterIn_uid42_fpToFxPTest_q;
|
||||
2'b01 : rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest_q = rightShiftStage0Idx1_uid61_rightShiferNoStickyOut_uid43_fpToFxPTest_q;
|
||||
2'b10 : rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest_q = rightShiftStage0Idx2_uid64_rightShiferNoStickyOut_uid43_fpToFxPTest_q;
|
||||
2'b11 : rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest_q = rightShiftStage0Idx3_uid67_rightShiferNoStickyOut_uid43_fpToFxPTest_q;
|
||||
default : rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest_q = 33'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// rightShiftStage1_uid80_rightShiferNoStickyOut_uid43_fpToFxPTest(MUX,79)@1
|
||||
assign rightShiftStage1_uid80_rightShiferNoStickyOut_uid43_fpToFxPTest_s = rightShiftStageSel0Dto0_uid68_rightShiferNoStickyOut_uid43_fpToFxPTest_merged_bit_select_c;
|
||||
always @(rightShiftStage1_uid80_rightShiferNoStickyOut_uid43_fpToFxPTest_s or en or rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest_q or rightShiftStage1Idx1_uid72_rightShiferNoStickyOut_uid43_fpToFxPTest_q or rightShiftStage1Idx2_uid75_rightShiferNoStickyOut_uid43_fpToFxPTest_q or rightShiftStage1Idx3_uid78_rightShiferNoStickyOut_uid43_fpToFxPTest_q)
|
||||
begin
|
||||
unique case (rightShiftStage1_uid80_rightShiferNoStickyOut_uid43_fpToFxPTest_s)
|
||||
2'b00 : rightShiftStage1_uid80_rightShiferNoStickyOut_uid43_fpToFxPTest_q = rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest_q;
|
||||
2'b01 : rightShiftStage1_uid80_rightShiferNoStickyOut_uid43_fpToFxPTest_q = rightShiftStage1Idx1_uid72_rightShiferNoStickyOut_uid43_fpToFxPTest_q;
|
||||
2'b10 : rightShiftStage1_uid80_rightShiferNoStickyOut_uid43_fpToFxPTest_q = rightShiftStage1Idx2_uid75_rightShiferNoStickyOut_uid43_fpToFxPTest_q;
|
||||
2'b11 : rightShiftStage1_uid80_rightShiferNoStickyOut_uid43_fpToFxPTest_q = rightShiftStage1Idx3_uid78_rightShiferNoStickyOut_uid43_fpToFxPTest_q;
|
||||
default : rightShiftStage1_uid80_rightShiferNoStickyOut_uid43_fpToFxPTest_q = 33'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// maxShiftCst_uid38_fpToFxPTest(CONSTANT,37)
|
||||
assign maxShiftCst_uid38_fpToFxPTest_q = 6'b100001;
|
||||
|
||||
// ovfExpVal_uid35_fpToFxPTest(CONSTANT,34)
|
||||
assign ovfExpVal_uid35_fpToFxPTest_q = 9'b010011110;
|
||||
|
||||
// shiftValE_uid36_fpToFxPTest(SUB,35)@0
|
||||
assign shiftValE_uid36_fpToFxPTest_a = {{2{ovfExpVal_uid35_fpToFxPTest_q[8]}}, ovfExpVal_uid35_fpToFxPTest_q};
|
||||
assign shiftValE_uid36_fpToFxPTest_b = {3'b000, exp_x_uid9_fpToFxPTest_b};
|
||||
assign shiftValE_uid36_fpToFxPTest_o = $signed(shiftValE_uid36_fpToFxPTest_a) - $signed(shiftValE_uid36_fpToFxPTest_b);
|
||||
assign shiftValE_uid36_fpToFxPTest_q = shiftValE_uid36_fpToFxPTest_o[9:0];
|
||||
|
||||
// shiftValRaw_uid37_fpToFxPTest(BITSELECT,36)@0
|
||||
assign shiftValRaw_uid37_fpToFxPTest_in = shiftValE_uid36_fpToFxPTest_q[5:0];
|
||||
assign shiftValRaw_uid37_fpToFxPTest_b = shiftValRaw_uid37_fpToFxPTest_in[5:0];
|
||||
|
||||
// shiftOutOfRange_uid39_fpToFxPTest(COMPARE,38)@0
|
||||
assign shiftOutOfRange_uid39_fpToFxPTest_a = {{2{shiftValE_uid36_fpToFxPTest_q[9]}}, shiftValE_uid36_fpToFxPTest_q};
|
||||
assign shiftOutOfRange_uid39_fpToFxPTest_b = {6'b000000, maxShiftCst_uid38_fpToFxPTest_q};
|
||||
assign shiftOutOfRange_uid39_fpToFxPTest_o = $signed(shiftOutOfRange_uid39_fpToFxPTest_a) - $signed(shiftOutOfRange_uid39_fpToFxPTest_b);
|
||||
assign shiftOutOfRange_uid39_fpToFxPTest_n[0] = ~ (shiftOutOfRange_uid39_fpToFxPTest_o[11]);
|
||||
|
||||
// shiftVal_uid40_fpToFxPTest(MUX,39)@0 + 1
|
||||
assign shiftVal_uid40_fpToFxPTest_s = shiftOutOfRange_uid39_fpToFxPTest_n;
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
shiftVal_uid40_fpToFxPTest_q <= 6'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
unique case (shiftVal_uid40_fpToFxPTest_s)
|
||||
1'b0 : shiftVal_uid40_fpToFxPTest_q <= shiftValRaw_uid37_fpToFxPTest_b;
|
||||
1'b1 : shiftVal_uid40_fpToFxPTest_q <= maxShiftCst_uid38_fpToFxPTest_q;
|
||||
default : shiftVal_uid40_fpToFxPTest_q <= 6'b0;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// rightShiftStageSel0Dto0_uid68_rightShiferNoStickyOut_uid43_fpToFxPTest_merged_bit_select(BITSELECT,90)@1
|
||||
assign rightShiftStageSel0Dto0_uid68_rightShiferNoStickyOut_uid43_fpToFxPTest_merged_bit_select_b = shiftVal_uid40_fpToFxPTest_q[1:0];
|
||||
assign rightShiftStageSel0Dto0_uid68_rightShiferNoStickyOut_uid43_fpToFxPTest_merged_bit_select_c = shiftVal_uid40_fpToFxPTest_q[3:2];
|
||||
assign rightShiftStageSel0Dto0_uid68_rightShiferNoStickyOut_uid43_fpToFxPTest_merged_bit_select_d = shiftVal_uid40_fpToFxPTest_q[5:4];
|
||||
|
||||
// rightShiftStage2_uid89_rightShiferNoStickyOut_uid43_fpToFxPTest(MUX,88)@1 + 1
|
||||
assign rightShiftStage2_uid89_rightShiferNoStickyOut_uid43_fpToFxPTest_s = rightShiftStageSel0Dto0_uid68_rightShiferNoStickyOut_uid43_fpToFxPTest_merged_bit_select_d;
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
rightShiftStage2_uid89_rightShiferNoStickyOut_uid43_fpToFxPTest_q <= 33'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
unique case (rightShiftStage2_uid89_rightShiferNoStickyOut_uid43_fpToFxPTest_s)
|
||||
2'b00 : rightShiftStage2_uid89_rightShiferNoStickyOut_uid43_fpToFxPTest_q <= rightShiftStage1_uid80_rightShiferNoStickyOut_uid43_fpToFxPTest_q;
|
||||
2'b01 : rightShiftStage2_uid89_rightShiferNoStickyOut_uid43_fpToFxPTest_q <= rightShiftStage2Idx1_uid83_rightShiferNoStickyOut_uid43_fpToFxPTest_q;
|
||||
2'b10 : rightShiftStage2_uid89_rightShiferNoStickyOut_uid43_fpToFxPTest_q <= rightShiftStage2Idx2_uid86_rightShiferNoStickyOut_uid43_fpToFxPTest_q;
|
||||
2'b11 : rightShiftStage2_uid89_rightShiferNoStickyOut_uid43_fpToFxPTest_q <= rightShiftStage2Idx3_uid87_rightShiferNoStickyOut_uid43_fpToFxPTest_q;
|
||||
default : rightShiftStage2_uid89_rightShiferNoStickyOut_uid43_fpToFxPTest_q <= 33'b0;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// zRightShiferNoStickyOut_uid47_fpToFxPTest(BITJOIN,46)@2
|
||||
assign zRightShiferNoStickyOut_uid47_fpToFxPTest_q = {GND_q, rightShiftStage2_uid89_rightShiferNoStickyOut_uid43_fpToFxPTest_q};
|
||||
|
||||
// sPostRndFull_uid48_fpToFxPTest(ADD,47)@2
|
||||
assign sPostRndFull_uid48_fpToFxPTest_a = {1'b0, zRightShiferNoStickyOut_uid47_fpToFxPTest_q};
|
||||
assign sPostRndFull_uid48_fpToFxPTest_b = {34'b0000000000000000000000000000000000, VCC_q};
|
||||
assign sPostRndFull_uid48_fpToFxPTest_o = $unsigned(sPostRndFull_uid48_fpToFxPTest_a) + $unsigned(sPostRndFull_uid48_fpToFxPTest_b);
|
||||
assign sPostRndFull_uid48_fpToFxPTest_q = sPostRndFull_uid48_fpToFxPTest_o[34:0];
|
||||
|
||||
// sPostRnd_uid49_fpToFxPTest(BITSELECT,48)@2
|
||||
assign sPostRnd_uid49_fpToFxPTest_in = sPostRndFull_uid48_fpToFxPTest_q[32:0];
|
||||
assign sPostRnd_uid49_fpToFxPTest_b = sPostRnd_uid49_fpToFxPTest_in[32:1];
|
||||
|
||||
// redist0_sPostRnd_uid49_fpToFxPTest_b_1(DELAY,91)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist0_sPostRnd_uid49_fpToFxPTest_b_1_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist0_sPostRnd_uid49_fpToFxPTest_b_1_q <= sPostRnd_uid49_fpToFxPTest_b;
|
||||
end
|
||||
end
|
||||
|
||||
// signX_uid27_fpToFxPTest(BITSELECT,26)@0
|
||||
assign signX_uid27_fpToFxPTest_b = a[31:31];
|
||||
|
||||
// redist3_signX_uid27_fpToFxPTest_b_1(DELAY,94)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist3_signX_uid27_fpToFxPTest_b_1_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist3_signX_uid27_fpToFxPTest_b_1_q <= signX_uid27_fpToFxPTest_b;
|
||||
end
|
||||
end
|
||||
|
||||
// fracXIsZero_uid13_fpToFxPTest(LOGICAL,12)@1
|
||||
assign fracXIsZero_uid13_fpToFxPTest_q = cstZeroWF_uid7_fpToFxPTest_q == redist5_frac_x_uid10_fpToFxPTest_b_1_q ? 1'b1 : 1'b0;
|
||||
|
||||
// fracXIsNotZero_uid14_fpToFxPTest(LOGICAL,13)@1
|
||||
assign fracXIsNotZero_uid14_fpToFxPTest_q = ~ (fracXIsZero_uid13_fpToFxPTest_q);
|
||||
|
||||
// cstAllOWE_uid6_fpToFxPTest(CONSTANT,5)
|
||||
assign cstAllOWE_uid6_fpToFxPTest_q = 8'b11111111;
|
||||
|
||||
// expXIsMax_uid12_fpToFxPTest(LOGICAL,11)@0 + 1
|
||||
assign expXIsMax_uid12_fpToFxPTest_qi = exp_x_uid9_fpToFxPTest_b == cstAllOWE_uid6_fpToFxPTest_q ? 1'b1 : 1'b0;
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) )
|
||||
expXIsMax_uid12_fpToFxPTest_delay ( .xin(expXIsMax_uid12_fpToFxPTest_qi), .xout(expXIsMax_uid12_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// excN_x_uid16_fpToFxPTest(LOGICAL,15)@1
|
||||
assign excN_x_uid16_fpToFxPTest_q = expXIsMax_uid12_fpToFxPTest_q & fracXIsNotZero_uid14_fpToFxPTest_q;
|
||||
|
||||
// notNan_uid28_fpToFxPTest(LOGICAL,27)@1
|
||||
assign notNan_uid28_fpToFxPTest_q = ~ (excN_x_uid16_fpToFxPTest_q);
|
||||
|
||||
// signX_uid29_fpToFxPTest(LOGICAL,28)@1 + 1
|
||||
assign signX_uid29_fpToFxPTest_qi = notNan_uid28_fpToFxPTest_q & redist3_signX_uid27_fpToFxPTest_b_1_q;
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) )
|
||||
signX_uid29_fpToFxPTest_delay ( .xin(signX_uid29_fpToFxPTest_qi), .xout(signX_uid29_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// udfExpVal_uid33_fpToFxPTest(CONSTANT,32)
|
||||
assign udfExpVal_uid33_fpToFxPTest_q = 8'b01111101;
|
||||
|
||||
// udf_uid34_fpToFxPTest(COMPARE,33)@0 + 1
|
||||
assign udf_uid34_fpToFxPTest_a = {{3{udfExpVal_uid33_fpToFxPTest_q[7]}}, udfExpVal_uid33_fpToFxPTest_q};
|
||||
assign udf_uid34_fpToFxPTest_b = {3'b000, exp_x_uid9_fpToFxPTest_b};
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
udf_uid34_fpToFxPTest_o <= 11'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
udf_uid34_fpToFxPTest_o <= $signed(udf_uid34_fpToFxPTest_a) - $signed(udf_uid34_fpToFxPTest_b);
|
||||
end
|
||||
end
|
||||
assign udf_uid34_fpToFxPTest_n[0] = ~ (udf_uid34_fpToFxPTest_o[10]);
|
||||
|
||||
// redist1_udf_uid34_fpToFxPTest_n_2(DELAY,92)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist1_udf_uid34_fpToFxPTest_n_2_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist1_udf_uid34_fpToFxPTest_n_2_q <= udf_uid34_fpToFxPTest_n;
|
||||
end
|
||||
end
|
||||
|
||||
// sPostRndFullMSBU_uid50_fpToFxPTest(BITSELECT,49)@2
|
||||
assign sPostRndFullMSBU_uid50_fpToFxPTest_in = sPostRndFull_uid48_fpToFxPTest_q[33:0];
|
||||
assign sPostRndFullMSBU_uid50_fpToFxPTest_b = sPostRndFullMSBU_uid50_fpToFxPTest_in[33:33];
|
||||
|
||||
// ovfExpVal_uid30_fpToFxPTest(CONSTANT,29)
|
||||
assign ovfExpVal_uid30_fpToFxPTest_q = 9'b010011111;
|
||||
|
||||
// ovf_uid31_fpToFxPTest(COMPARE,30)@0 + 1
|
||||
assign ovf_uid31_fpToFxPTest_a = {3'b000, exp_x_uid9_fpToFxPTest_b};
|
||||
assign ovf_uid31_fpToFxPTest_b = {{2{ovfExpVal_uid30_fpToFxPTest_q[8]}}, ovfExpVal_uid30_fpToFxPTest_q};
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
ovf_uid31_fpToFxPTest_o <= 11'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
ovf_uid31_fpToFxPTest_o <= $signed(ovf_uid31_fpToFxPTest_a) - $signed(ovf_uid31_fpToFxPTest_b);
|
||||
end
|
||||
end
|
||||
assign ovf_uid31_fpToFxPTest_n[0] = ~ (ovf_uid31_fpToFxPTest_o[10]);
|
||||
|
||||
// redist2_ovf_uid31_fpToFxPTest_n_2(DELAY,93)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist2_ovf_uid31_fpToFxPTest_n_2_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist2_ovf_uid31_fpToFxPTest_n_2_q <= ovf_uid31_fpToFxPTest_n;
|
||||
end
|
||||
end
|
||||
|
||||
// negOrOvf_uid32_fpToFxPTest(LOGICAL,31)@2
|
||||
assign negOrOvf_uid32_fpToFxPTest_q = signX_uid29_fpToFxPTest_q | redist2_ovf_uid31_fpToFxPTest_n_2_q;
|
||||
|
||||
// excI_x_uid15_fpToFxPTest(LOGICAL,14)@1 + 1
|
||||
assign excI_x_uid15_fpToFxPTest_qi = expXIsMax_uid12_fpToFxPTest_q & fracXIsZero_uid13_fpToFxPTest_q;
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) )
|
||||
excI_x_uid15_fpToFxPTest_delay ( .xin(excI_x_uid15_fpToFxPTest_qi), .xout(excI_x_uid15_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// redist4_excN_x_uid16_fpToFxPTest_q_1(DELAY,95)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist4_excN_x_uid16_fpToFxPTest_q_1_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist4_excN_x_uid16_fpToFxPTest_q_1_q <= excN_x_uid16_fpToFxPTest_q;
|
||||
end
|
||||
end
|
||||
|
||||
// ovfPostRnd_uid51_fpToFxPTest(LOGICAL,50)@2
|
||||
assign ovfPostRnd_uid51_fpToFxPTest_q = redist4_excN_x_uid16_fpToFxPTest_q_1_q | excI_x_uid15_fpToFxPTest_q | negOrOvf_uid32_fpToFxPTest_q | sPostRndFullMSBU_uid50_fpToFxPTest_b;
|
||||
|
||||
// muxSelConc_uid52_fpToFxPTest(BITJOIN,51)@2
|
||||
assign muxSelConc_uid52_fpToFxPTest_q = {signX_uid29_fpToFxPTest_q, redist1_udf_uid34_fpToFxPTest_n_2_q, ovfPostRnd_uid51_fpToFxPTest_q};
|
||||
|
||||
// muxSel_uid53_fpToFxPTest(LOOKUP,52)@2 + 1
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
muxSel_uid53_fpToFxPTest_q <= 2'b00;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
unique case (muxSelConc_uid52_fpToFxPTest_q)
|
||||
3'b000 : muxSel_uid53_fpToFxPTest_q <= 2'b00;
|
||||
3'b001 : muxSel_uid53_fpToFxPTest_q <= 2'b01;
|
||||
3'b010 : muxSel_uid53_fpToFxPTest_q <= 2'b11;
|
||||
3'b011 : muxSel_uid53_fpToFxPTest_q <= 2'b00;
|
||||
3'b100 : muxSel_uid53_fpToFxPTest_q <= 2'b10;
|
||||
3'b101 : muxSel_uid53_fpToFxPTest_q <= 2'b10;
|
||||
3'b110 : muxSel_uid53_fpToFxPTest_q <= 2'b10;
|
||||
3'b111 : muxSel_uid53_fpToFxPTest_q <= 2'b10;
|
||||
default : begin
|
||||
// unreachable
|
||||
muxSel_uid53_fpToFxPTest_q <= 2'bxx;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// finalOut_uid55_fpToFxPTest(MUX,54)@3
|
||||
assign finalOut_uid55_fpToFxPTest_s = muxSel_uid53_fpToFxPTest_q;
|
||||
always @(finalOut_uid55_fpToFxPTest_s or en or redist0_sPostRnd_uid49_fpToFxPTest_b_1_q or maxPosValueU_uid44_fpToFxPTest_q or maxNegValueU_uid45_fpToFxPTest_q)
|
||||
begin
|
||||
unique case (finalOut_uid55_fpToFxPTest_s)
|
||||
2'b00 : finalOut_uid55_fpToFxPTest_q = redist0_sPostRnd_uid49_fpToFxPTest_b_1_q;
|
||||
2'b01 : finalOut_uid55_fpToFxPTest_q = maxPosValueU_uid44_fpToFxPTest_q;
|
||||
2'b10 : finalOut_uid55_fpToFxPTest_q = maxNegValueU_uid45_fpToFxPTest_q;
|
||||
2'b11 : finalOut_uid55_fpToFxPTest_q = maxNegValueU_uid45_fpToFxPTest_q;
|
||||
default : finalOut_uid55_fpToFxPTest_q = 32'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// xOut(GPOUT,4)@3
|
||||
assign q = finalOut_uid55_fpToFxPTest_q;
|
||||
|
||||
endmodule
|
||||
@@ -18,13 +18,16 @@ FBITS="f$(($EXP_BITS + $MAN_BITS + 1))"
|
||||
|
||||
echo Generating IP cores for $FBITS
|
||||
{
|
||||
#$CMD -name "$PREFIX"_fadd -frequency 250 FPAdd $EXP_BITS $MAN_BITS
|
||||
#$CMD -name "$PREFIX"_fsub -frequency 250 FPSub $EXP_BITS $MAN_BITS
|
||||
#$CMD -name "$PREFIX"_fmul -frequency 250 FPMul $EXP_BITS $MAN_BITS
|
||||
$CMD -name "$PREFIX"_fmadd -frequency 250 FPMultAdd $EXP_BITS $MAN_BITS
|
||||
$CMD -name "$PREFIX"_fdiv -frequency 250 FPDiv $EXP_BITS $MAN_BITS 0
|
||||
$CMD -name "$PREFIX"_fsqrt -frequency 250 FPSqrt $EXP_BITS $MAN_BITS
|
||||
$CMD -name "$PREFIX"_ftoi -frequency 250 FPToFXP $EXP_BITS $MAN_BITS 32 0 1
|
||||
$CMD -name "$PREFIX"_ftou -frequency 250 FPToFXP $EXP_BITS $MAN_BITS 32 0 0
|
||||
$CMD -name "$PREFIX"_itof -frequency 250 FXPToFP 32 0 1 $EXP_BITS $MAN_BITS
|
||||
$CMD -name "$PREFIX"_utof -frequency 300 FXPToFP 32 0 0 $EXP_BITS $MAN_BITS
|
||||
#$CMD -name "$PREFIX"_ftoi -frequency 250 FPToFXP $EXP_BITS $MAN_BITS 32 0 1
|
||||
#$CMD -name "$PREFIX"_ftou -frequency 250 FPToFXP $EXP_BITS $MAN_BITS 32 0 0
|
||||
#$CMD -name "$PREFIX"_itof -frequency 250 FXPToFP 32 0 1 $EXP_BITS $MAN_BITS
|
||||
#$CMD -name "$PREFIX"_utof -frequency 300 FXPToFP 32 0 0 $EXP_BITS $MAN_BITS
|
||||
} > acl_gen.log 2>&1
|
||||
|
||||
#cp $QUARTUS_HOME/dspba/backend/Libraries/sv/base/dspba_library_ver.sv .
|
||||
@@ -1,631 +0,0 @@
|
||||
// -------------------------------------------------------------------------
|
||||
// High Level Design Compiler for Intel(R) FPGAs Version 18.1 (Release Build #277)
|
||||
// Quartus Prime development tool and MATLAB/Simulink Interface
|
||||
//
|
||||
// Legal Notice: Copyright 2019 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly
|
||||
// subject to the terms and conditions of the Intel FPGA Software License
|
||||
// Agreement, Intel MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for
|
||||
// the sole purpose of programming logic devices manufactured by Intel
|
||||
// and sold by Intel or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
// ---------------------------------------------------------------------------
|
||||
|
||||
// SystemVerilog created from acl_itof
|
||||
// SystemVerilog created on Sun Dec 27 09:48:58 2020
|
||||
|
||||
|
||||
(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
|
||||
module acl_itof (
|
||||
input wire [31:0] a,
|
||||
input wire [0:0] en,
|
||||
output wire [31:0] q,
|
||||
input wire clk,
|
||||
input wire areset
|
||||
);
|
||||
|
||||
wire [0:0] GND_q;
|
||||
wire [0:0] signX_uid6_fxpToFPTest_b;
|
||||
wire [31:0] xXorSign_uid7_fxpToFPTest_b;
|
||||
wire [31:0] xXorSign_uid7_fxpToFPTest_q;
|
||||
wire [32:0] yE_uid8_fxpToFPTest_a;
|
||||
wire [32:0] yE_uid8_fxpToFPTest_b;
|
||||
logic [32:0] yE_uid8_fxpToFPTest_o;
|
||||
wire [32:0] yE_uid8_fxpToFPTest_q;
|
||||
wire [31:0] y_uid9_fxpToFPTest_in;
|
||||
wire [31:0] y_uid9_fxpToFPTest_b;
|
||||
wire [5:0] maxCount_uid11_fxpToFPTest_q;
|
||||
wire [0:0] inIsZero_uid12_fxpToFPTest_qi;
|
||||
reg [0:0] inIsZero_uid12_fxpToFPTest_q;
|
||||
wire [7:0] msbIn_uid13_fxpToFPTest_q;
|
||||
wire [8:0] expPreRnd_uid14_fxpToFPTest_a;
|
||||
wire [8:0] expPreRnd_uid14_fxpToFPTest_b;
|
||||
logic [8:0] expPreRnd_uid14_fxpToFPTest_o;
|
||||
wire [8:0] expPreRnd_uid14_fxpToFPTest_q;
|
||||
wire [32:0] expFracRnd_uid16_fxpToFPTest_q;
|
||||
wire [0:0] sticky_uid20_fxpToFPTest_qi;
|
||||
reg [0:0] sticky_uid20_fxpToFPTest_q;
|
||||
wire [0:0] nr_uid21_fxpToFPTest_q;
|
||||
wire [0:0] rnd_uid22_fxpToFPTest_q;
|
||||
wire [34:0] expFracR_uid24_fxpToFPTest_a;
|
||||
wire [34:0] expFracR_uid24_fxpToFPTest_b;
|
||||
logic [34:0] expFracR_uid24_fxpToFPTest_o;
|
||||
wire [33:0] expFracR_uid24_fxpToFPTest_q;
|
||||
wire [23:0] fracR_uid25_fxpToFPTest_in;
|
||||
wire [22:0] fracR_uid25_fxpToFPTest_b;
|
||||
wire [9:0] expR_uid26_fxpToFPTest_b;
|
||||
wire [11:0] udf_uid27_fxpToFPTest_a;
|
||||
wire [11:0] udf_uid27_fxpToFPTest_b;
|
||||
logic [11:0] udf_uid27_fxpToFPTest_o;
|
||||
wire [0:0] udf_uid27_fxpToFPTest_n;
|
||||
wire [7:0] expInf_uid28_fxpToFPTest_q;
|
||||
wire [11:0] ovf_uid29_fxpToFPTest_a;
|
||||
wire [11:0] ovf_uid29_fxpToFPTest_b;
|
||||
logic [11:0] ovf_uid29_fxpToFPTest_o;
|
||||
wire [0:0] ovf_uid29_fxpToFPTest_n;
|
||||
wire [0:0] excSelector_uid30_fxpToFPTest_q;
|
||||
wire [22:0] fracZ_uid31_fxpToFPTest_q;
|
||||
wire [0:0] fracRPostExc_uid32_fxpToFPTest_s;
|
||||
reg [22:0] fracRPostExc_uid32_fxpToFPTest_q;
|
||||
wire [0:0] udfOrInZero_uid33_fxpToFPTest_q;
|
||||
wire [1:0] excSelector_uid34_fxpToFPTest_q;
|
||||
wire [7:0] expZ_uid37_fxpToFPTest_q;
|
||||
wire [7:0] expR_uid38_fxpToFPTest_in;
|
||||
wire [7:0] expR_uid38_fxpToFPTest_b;
|
||||
wire [1:0] expRPostExc_uid39_fxpToFPTest_s;
|
||||
reg [7:0] expRPostExc_uid39_fxpToFPTest_q;
|
||||
wire [31:0] outRes_uid40_fxpToFPTest_q;
|
||||
wire [31:0] zs_uid42_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [0:0] vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_qi;
|
||||
reg [0:0] vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [0:0] vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_s;
|
||||
reg [31:0] vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [15:0] zs_uid47_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [0:0] vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [31:0] cStage_uid52_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [0:0] vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_s;
|
||||
reg [31:0] vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [0:0] vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [31:0] cStage_uid59_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [0:0] vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_s;
|
||||
reg [31:0] vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [3:0] zs_uid61_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [0:0] vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [31:0] cStage_uid66_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [0:0] vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_s;
|
||||
reg [31:0] vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [1:0] zs_uid68_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [0:0] vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [31:0] cStage_uid73_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [0:0] vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_s;
|
||||
reg [31:0] vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [0:0] vCount_uid77_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [31:0] cStage_uid80_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [0:0] vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_s;
|
||||
reg [31:0] vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [5:0] vCount_uid82_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [7:0] vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_a;
|
||||
wire [7:0] vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_b;
|
||||
logic [7:0] vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_o;
|
||||
wire [0:0] vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_c;
|
||||
wire [0:0] vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_s;
|
||||
reg [5:0] vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
wire [1:0] l_uid17_fxpToFPTest_merged_bit_select_in;
|
||||
wire [0:0] l_uid17_fxpToFPTest_merged_bit_select_b;
|
||||
wire [0:0] l_uid17_fxpToFPTest_merged_bit_select_c;
|
||||
wire [15:0] rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b;
|
||||
wire [15:0] rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c;
|
||||
wire [7:0] rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b;
|
||||
wire [23:0] rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c;
|
||||
wire [3:0] rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b;
|
||||
wire [27:0] rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c;
|
||||
wire [1:0] rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b;
|
||||
wire [29:0] rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c;
|
||||
wire [0:0] rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b;
|
||||
wire [30:0] rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c;
|
||||
wire [30:0] fracRnd_uid15_fxpToFPTest_merged_bit_select_in;
|
||||
wire [23:0] fracRnd_uid15_fxpToFPTest_merged_bit_select_b;
|
||||
wire [6:0] fracRnd_uid15_fxpToFPTest_merged_bit_select_c;
|
||||
reg [23:0] redist0_fracRnd_uid15_fxpToFPTest_merged_bit_select_b_1_q;
|
||||
reg [0:0] redist1_vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q_1_q;
|
||||
reg [0:0] redist2_vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q_1_q;
|
||||
reg [0:0] redist3_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_2_q;
|
||||
reg [0:0] redist3_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_2_delay_0;
|
||||
reg [0:0] redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3_q;
|
||||
reg [0:0] redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3_delay_0;
|
||||
reg [0:0] redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3_delay_1;
|
||||
reg [0:0] redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4_q;
|
||||
reg [0:0] redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4_delay_0;
|
||||
reg [0:0] redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4_delay_1;
|
||||
reg [9:0] redist6_expR_uid26_fxpToFPTest_b_1_q;
|
||||
reg [22:0] redist7_fracR_uid25_fxpToFPTest_b_1_q;
|
||||
reg [0:0] redist8_inIsZero_uid12_fxpToFPTest_q_2_q;
|
||||
reg [31:0] redist9_y_uid9_fxpToFPTest_b_1_q;
|
||||
reg [31:0] redist10_y_uid9_fxpToFPTest_b_2_q;
|
||||
reg [0:0] redist11_signX_uid6_fxpToFPTest_b_7_q;
|
||||
|
||||
|
||||
// signX_uid6_fxpToFPTest(BITSELECT,5)@0
|
||||
assign signX_uid6_fxpToFPTest_b = a[31:31];
|
||||
|
||||
// redist11_signX_uid6_fxpToFPTest_b_7(DELAY,106)
|
||||
dspba_delay_ver #( .width(1), .depth(7), .reset_kind("SYNC"), .phase(0), .modulus(1) )
|
||||
redist11_signX_uid6_fxpToFPTest_b_7 ( .xin(signX_uid6_fxpToFPTest_b), .xout(redist11_signX_uid6_fxpToFPTest_b_7_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// expInf_uid28_fxpToFPTest(CONSTANT,27)
|
||||
assign expInf_uid28_fxpToFPTest_q = 8'b11111111;
|
||||
|
||||
// expZ_uid37_fxpToFPTest(CONSTANT,36)
|
||||
assign expZ_uid37_fxpToFPTest_q = 8'b00000000;
|
||||
|
||||
// rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select(BITSELECT,93)@5
|
||||
assign rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b = vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q[31:31];
|
||||
assign rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c = vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q[30:0];
|
||||
|
||||
// GND(CONSTANT,0)
|
||||
assign GND_q = 1'b0;
|
||||
|
||||
// cStage_uid80_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,79)@5
|
||||
assign cStage_uid80_lzcShifterZ1_uid10_fxpToFPTest_q = {rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c, GND_q};
|
||||
|
||||
// rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select(BITSELECT,92)@4
|
||||
assign rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b = vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q[31:30];
|
||||
assign rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c = vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q[29:0];
|
||||
|
||||
// zs_uid68_lzcShifterZ1_uid10_fxpToFPTest(CONSTANT,67)
|
||||
assign zs_uid68_lzcShifterZ1_uid10_fxpToFPTest_q = 2'b00;
|
||||
|
||||
// cStage_uid73_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,72)@4
|
||||
assign cStage_uid73_lzcShifterZ1_uid10_fxpToFPTest_q = {rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c, zs_uid68_lzcShifterZ1_uid10_fxpToFPTest_q};
|
||||
|
||||
// rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select(BITSELECT,91)@4
|
||||
assign rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b = vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q[31:28];
|
||||
assign rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c = vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q[27:0];
|
||||
|
||||
// zs_uid61_lzcShifterZ1_uid10_fxpToFPTest(CONSTANT,60)
|
||||
assign zs_uid61_lzcShifterZ1_uid10_fxpToFPTest_q = 4'b0000;
|
||||
|
||||
// cStage_uid66_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,65)@4
|
||||
assign cStage_uid66_lzcShifterZ1_uid10_fxpToFPTest_q = {rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c, zs_uid61_lzcShifterZ1_uid10_fxpToFPTest_q};
|
||||
|
||||
// rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select(BITSELECT,90)@3
|
||||
assign rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b = vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q[31:24];
|
||||
assign rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c = vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q[23:0];
|
||||
|
||||
// cStage_uid59_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,58)@3
|
||||
assign cStage_uid59_lzcShifterZ1_uid10_fxpToFPTest_q = {rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c, expZ_uid37_fxpToFPTest_q};
|
||||
|
||||
// rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select(BITSELECT,89)@2
|
||||
assign rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b = vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q[31:16];
|
||||
assign rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c = vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q[15:0];
|
||||
|
||||
// zs_uid47_lzcShifterZ1_uid10_fxpToFPTest(CONSTANT,46)
|
||||
assign zs_uid47_lzcShifterZ1_uid10_fxpToFPTest_q = 16'b0000000000000000;
|
||||
|
||||
// cStage_uid52_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,51)@2
|
||||
assign cStage_uid52_lzcShifterZ1_uid10_fxpToFPTest_q = {rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c, zs_uid47_lzcShifterZ1_uid10_fxpToFPTest_q};
|
||||
|
||||
// zs_uid42_lzcShifterZ1_uid10_fxpToFPTest(CONSTANT,41)
|
||||
assign zs_uid42_lzcShifterZ1_uid10_fxpToFPTest_q = 32'b00000000000000000000000000000000;
|
||||
|
||||
// xXorSign_uid7_fxpToFPTest(LOGICAL,6)@0
|
||||
assign xXorSign_uid7_fxpToFPTest_b = {{31{signX_uid6_fxpToFPTest_b[0]}}, signX_uid6_fxpToFPTest_b};
|
||||
assign xXorSign_uid7_fxpToFPTest_q = a ^ xXorSign_uid7_fxpToFPTest_b;
|
||||
|
||||
// yE_uid8_fxpToFPTest(ADD,7)@0
|
||||
assign yE_uid8_fxpToFPTest_a = {1'b0, xXorSign_uid7_fxpToFPTest_q};
|
||||
assign yE_uid8_fxpToFPTest_b = {32'b00000000000000000000000000000000, signX_uid6_fxpToFPTest_b};
|
||||
assign yE_uid8_fxpToFPTest_o = $unsigned(yE_uid8_fxpToFPTest_a) + $unsigned(yE_uid8_fxpToFPTest_b);
|
||||
assign yE_uid8_fxpToFPTest_q = yE_uid8_fxpToFPTest_o[32:0];
|
||||
|
||||
// y_uid9_fxpToFPTest(BITSELECT,8)@0
|
||||
assign y_uid9_fxpToFPTest_in = yE_uid8_fxpToFPTest_q[31:0];
|
||||
assign y_uid9_fxpToFPTest_b = y_uid9_fxpToFPTest_in[31:0];
|
||||
|
||||
// redist9_y_uid9_fxpToFPTest_b_1(DELAY,104)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist9_y_uid9_fxpToFPTest_b_1_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist9_y_uid9_fxpToFPTest_b_1_q <= y_uid9_fxpToFPTest_b;
|
||||
end
|
||||
end
|
||||
|
||||
// redist10_y_uid9_fxpToFPTest_b_2(DELAY,105)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist10_y_uid9_fxpToFPTest_b_2_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist10_y_uid9_fxpToFPTest_b_2_q <= redist9_y_uid9_fxpToFPTest_b_1_q;
|
||||
end
|
||||
end
|
||||
|
||||
// vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,43)@1 + 1
|
||||
assign vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_qi = redist9_y_uid9_fxpToFPTest_b_1_q == zs_uid42_lzcShifterZ1_uid10_fxpToFPTest_q ? 1'b1 : 1'b0;
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) )
|
||||
vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_delay ( .xin(vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_qi), .xout(vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest(MUX,45)@2
|
||||
assign vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_s = vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
always @(vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_s or en or redist10_y_uid9_fxpToFPTest_b_2_q or zs_uid42_lzcShifterZ1_uid10_fxpToFPTest_q)
|
||||
begin
|
||||
unique case (vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_s)
|
||||
1'b0 : vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q = redist10_y_uid9_fxpToFPTest_b_2_q;
|
||||
1'b1 : vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q = zs_uid42_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
default : vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q = 32'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,48)@2
|
||||
assign vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q = rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b == zs_uid47_lzcShifterZ1_uid10_fxpToFPTest_q ? 1'b1 : 1'b0;
|
||||
|
||||
// vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest(MUX,52)@2 + 1
|
||||
assign vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_s = vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q <= 32'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
unique case (vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_s)
|
||||
1'b0 : vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q <= vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
1'b1 : vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q <= cStage_uid52_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
default : vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q <= 32'b0;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,55)@3
|
||||
assign vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q = rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b == expZ_uid37_fxpToFPTest_q ? 1'b1 : 1'b0;
|
||||
|
||||
// vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest(MUX,59)@3 + 1
|
||||
assign vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_s = vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q <= 32'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
unique case (vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_s)
|
||||
1'b0 : vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q <= vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
1'b1 : vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q <= cStage_uid59_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
default : vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q <= 32'b0;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,62)@4
|
||||
assign vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q = rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b == zs_uid61_lzcShifterZ1_uid10_fxpToFPTest_q ? 1'b1 : 1'b0;
|
||||
|
||||
// vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest(MUX,66)@4
|
||||
assign vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_s = vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
always @(vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_s or en or vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q or cStage_uid66_lzcShifterZ1_uid10_fxpToFPTest_q)
|
||||
begin
|
||||
unique case (vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_s)
|
||||
1'b0 : vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q = vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
1'b1 : vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q = cStage_uid66_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
default : vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q = 32'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,69)@4
|
||||
assign vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q = rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b == zs_uid68_lzcShifterZ1_uid10_fxpToFPTest_q ? 1'b1 : 1'b0;
|
||||
|
||||
// vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest(MUX,73)@4 + 1
|
||||
assign vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_s = vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q <= 32'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
unique case (vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_s)
|
||||
1'b0 : vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q <= vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
1'b1 : vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q <= cStage_uid73_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
default : vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q <= 32'b0;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// vCount_uid77_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,76)@5
|
||||
assign vCount_uid77_lzcShifterZ1_uid10_fxpToFPTest_q = rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b == GND_q ? 1'b1 : 1'b0;
|
||||
|
||||
// vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest(MUX,80)@5
|
||||
assign vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_s = vCount_uid77_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
always @(vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_s or en or vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q or cStage_uid80_lzcShifterZ1_uid10_fxpToFPTest_q)
|
||||
begin
|
||||
unique case (vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_s)
|
||||
1'b0 : vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_q = vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
1'b1 : vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_q = cStage_uid80_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
default : vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_q = 32'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// fracRnd_uid15_fxpToFPTest_merged_bit_select(BITSELECT,94)@5
|
||||
assign fracRnd_uid15_fxpToFPTest_merged_bit_select_in = vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_q[30:0];
|
||||
assign fracRnd_uid15_fxpToFPTest_merged_bit_select_b = fracRnd_uid15_fxpToFPTest_merged_bit_select_in[30:7];
|
||||
assign fracRnd_uid15_fxpToFPTest_merged_bit_select_c = fracRnd_uid15_fxpToFPTest_merged_bit_select_in[6:0];
|
||||
|
||||
// sticky_uid20_fxpToFPTest(LOGICAL,19)@5 + 1
|
||||
assign sticky_uid20_fxpToFPTest_qi = fracRnd_uid15_fxpToFPTest_merged_bit_select_c != 7'b0000000 ? 1'b1 : 1'b0;
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) )
|
||||
sticky_uid20_fxpToFPTest_delay ( .xin(sticky_uid20_fxpToFPTest_qi), .xout(sticky_uid20_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// nr_uid21_fxpToFPTest(LOGICAL,20)@6
|
||||
assign nr_uid21_fxpToFPTest_q = ~ (l_uid17_fxpToFPTest_merged_bit_select_c);
|
||||
|
||||
// l_uid17_fxpToFPTest_merged_bit_select(BITSELECT,88)@6
|
||||
assign l_uid17_fxpToFPTest_merged_bit_select_in = expFracRnd_uid16_fxpToFPTest_q[1:0];
|
||||
assign l_uid17_fxpToFPTest_merged_bit_select_b = l_uid17_fxpToFPTest_merged_bit_select_in[1:1];
|
||||
assign l_uid17_fxpToFPTest_merged_bit_select_c = l_uid17_fxpToFPTest_merged_bit_select_in[0:0];
|
||||
|
||||
// rnd_uid22_fxpToFPTest(LOGICAL,21)@6
|
||||
assign rnd_uid22_fxpToFPTest_q = l_uid17_fxpToFPTest_merged_bit_select_b | nr_uid21_fxpToFPTest_q | sticky_uid20_fxpToFPTest_q;
|
||||
|
||||
// maxCount_uid11_fxpToFPTest(CONSTANT,10)
|
||||
assign maxCount_uid11_fxpToFPTest_q = 6'b100000;
|
||||
|
||||
// redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4(DELAY,100)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4_delay_0 <= '0;
|
||||
redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4_delay_1 <= '0;
|
||||
redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4_delay_0 <= vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4_delay_1 <= redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4_delay_0;
|
||||
redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4_q <= redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4_delay_1;
|
||||
end
|
||||
end
|
||||
|
||||
// redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3(DELAY,99)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3_delay_0 <= '0;
|
||||
redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3_delay_1 <= '0;
|
||||
redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3_delay_0 <= vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3_delay_1 <= redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3_delay_0;
|
||||
redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3_q <= redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3_delay_1;
|
||||
end
|
||||
end
|
||||
|
||||
// redist3_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_2(DELAY,98)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist3_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_2_delay_0 <= '0;
|
||||
redist3_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_2_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist3_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_2_delay_0 <= vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
redist3_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_2_q <= redist3_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_2_delay_0;
|
||||
end
|
||||
end
|
||||
|
||||
// redist2_vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q_1(DELAY,97)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist2_vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q_1_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist2_vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q_1_q <= vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
end
|
||||
end
|
||||
|
||||
// redist1_vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q_1(DELAY,96)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist1_vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q_1_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist1_vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q_1_q <= vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
end
|
||||
end
|
||||
|
||||
// vCount_uid82_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,81)@5
|
||||
assign vCount_uid82_lzcShifterZ1_uid10_fxpToFPTest_q = {redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4_q, redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3_q, redist3_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_2_q, redist2_vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q_1_q, redist1_vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q_1_q, vCount_uid77_lzcShifterZ1_uid10_fxpToFPTest_q};
|
||||
|
||||
// vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest(COMPARE,83)@5
|
||||
assign vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_a = {2'b00, maxCount_uid11_fxpToFPTest_q};
|
||||
assign vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_b = {2'b00, vCount_uid82_lzcShifterZ1_uid10_fxpToFPTest_q};
|
||||
assign vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_o = $unsigned(vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_a) - $unsigned(vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_b);
|
||||
assign vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_c[0] = vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_o[7];
|
||||
|
||||
// vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest(MUX,85)@5
|
||||
assign vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_s = vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_c;
|
||||
always @(vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_s or en or vCount_uid82_lzcShifterZ1_uid10_fxpToFPTest_q or maxCount_uid11_fxpToFPTest_q)
|
||||
begin
|
||||
unique case (vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_s)
|
||||
1'b0 : vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q = vCount_uid82_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
1'b1 : vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q = maxCount_uid11_fxpToFPTest_q;
|
||||
default : vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q = 6'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// msbIn_uid13_fxpToFPTest(CONSTANT,12)
|
||||
assign msbIn_uid13_fxpToFPTest_q = 8'b10011110;
|
||||
|
||||
// expPreRnd_uid14_fxpToFPTest(SUB,13)@5 + 1
|
||||
assign expPreRnd_uid14_fxpToFPTest_a = {1'b0, msbIn_uid13_fxpToFPTest_q};
|
||||
assign expPreRnd_uid14_fxpToFPTest_b = {3'b000, vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q};
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
expPreRnd_uid14_fxpToFPTest_o <= 9'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
expPreRnd_uid14_fxpToFPTest_o <= $unsigned(expPreRnd_uid14_fxpToFPTest_a) - $unsigned(expPreRnd_uid14_fxpToFPTest_b);
|
||||
end
|
||||
end
|
||||
assign expPreRnd_uid14_fxpToFPTest_q = expPreRnd_uid14_fxpToFPTest_o[8:0];
|
||||
|
||||
// redist0_fracRnd_uid15_fxpToFPTest_merged_bit_select_b_1(DELAY,95)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist0_fracRnd_uid15_fxpToFPTest_merged_bit_select_b_1_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist0_fracRnd_uid15_fxpToFPTest_merged_bit_select_b_1_q <= fracRnd_uid15_fxpToFPTest_merged_bit_select_b;
|
||||
end
|
||||
end
|
||||
|
||||
// expFracRnd_uid16_fxpToFPTest(BITJOIN,15)@6
|
||||
assign expFracRnd_uid16_fxpToFPTest_q = {expPreRnd_uid14_fxpToFPTest_q, redist0_fracRnd_uid15_fxpToFPTest_merged_bit_select_b_1_q};
|
||||
|
||||
// expFracR_uid24_fxpToFPTest(ADD,23)@6
|
||||
assign expFracR_uid24_fxpToFPTest_a = {{2{expFracRnd_uid16_fxpToFPTest_q[32]}}, expFracRnd_uid16_fxpToFPTest_q};
|
||||
assign expFracR_uid24_fxpToFPTest_b = {34'b0000000000000000000000000000000000, rnd_uid22_fxpToFPTest_q};
|
||||
assign expFracR_uid24_fxpToFPTest_o = $signed(expFracR_uid24_fxpToFPTest_a) + $signed(expFracR_uid24_fxpToFPTest_b);
|
||||
assign expFracR_uid24_fxpToFPTest_q = expFracR_uid24_fxpToFPTest_o[33:0];
|
||||
|
||||
// expR_uid26_fxpToFPTest(BITSELECT,25)@6
|
||||
assign expR_uid26_fxpToFPTest_b = expFracR_uid24_fxpToFPTest_q[33:24];
|
||||
|
||||
// redist6_expR_uid26_fxpToFPTest_b_1(DELAY,101)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist6_expR_uid26_fxpToFPTest_b_1_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist6_expR_uid26_fxpToFPTest_b_1_q <= expR_uid26_fxpToFPTest_b;
|
||||
end
|
||||
end
|
||||
|
||||
// expR_uid38_fxpToFPTest(BITSELECT,37)@7
|
||||
assign expR_uid38_fxpToFPTest_in = redist6_expR_uid26_fxpToFPTest_b_1_q[7:0];
|
||||
assign expR_uid38_fxpToFPTest_b = expR_uid38_fxpToFPTest_in[7:0];
|
||||
|
||||
// ovf_uid29_fxpToFPTest(COMPARE,28)@7
|
||||
assign ovf_uid29_fxpToFPTest_a = {{2{redist6_expR_uid26_fxpToFPTest_b_1_q[9]}}, redist6_expR_uid26_fxpToFPTest_b_1_q};
|
||||
assign ovf_uid29_fxpToFPTest_b = {4'b0000, expInf_uid28_fxpToFPTest_q};
|
||||
assign ovf_uid29_fxpToFPTest_o = $signed(ovf_uid29_fxpToFPTest_a) - $signed(ovf_uid29_fxpToFPTest_b);
|
||||
assign ovf_uid29_fxpToFPTest_n[0] = ~ (ovf_uid29_fxpToFPTest_o[11]);
|
||||
|
||||
// inIsZero_uid12_fxpToFPTest(LOGICAL,11)@5 + 1
|
||||
assign inIsZero_uid12_fxpToFPTest_qi = vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q == maxCount_uid11_fxpToFPTest_q ? 1'b1 : 1'b0;
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) )
|
||||
inIsZero_uid12_fxpToFPTest_delay ( .xin(inIsZero_uid12_fxpToFPTest_qi), .xout(inIsZero_uid12_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// redist8_inIsZero_uid12_fxpToFPTest_q_2(DELAY,103)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist8_inIsZero_uid12_fxpToFPTest_q_2_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist8_inIsZero_uid12_fxpToFPTest_q_2_q <= inIsZero_uid12_fxpToFPTest_q;
|
||||
end
|
||||
end
|
||||
|
||||
// udf_uid27_fxpToFPTest(COMPARE,26)@7
|
||||
assign udf_uid27_fxpToFPTest_a = {11'b00000000000, GND_q};
|
||||
assign udf_uid27_fxpToFPTest_b = {{2{redist6_expR_uid26_fxpToFPTest_b_1_q[9]}}, redist6_expR_uid26_fxpToFPTest_b_1_q};
|
||||
assign udf_uid27_fxpToFPTest_o = $signed(udf_uid27_fxpToFPTest_a) - $signed(udf_uid27_fxpToFPTest_b);
|
||||
assign udf_uid27_fxpToFPTest_n[0] = ~ (udf_uid27_fxpToFPTest_o[11]);
|
||||
|
||||
// udfOrInZero_uid33_fxpToFPTest(LOGICAL,32)@7
|
||||
assign udfOrInZero_uid33_fxpToFPTest_q = udf_uid27_fxpToFPTest_n | redist8_inIsZero_uid12_fxpToFPTest_q_2_q;
|
||||
|
||||
// excSelector_uid34_fxpToFPTest(BITJOIN,33)@7
|
||||
assign excSelector_uid34_fxpToFPTest_q = {ovf_uid29_fxpToFPTest_n, udfOrInZero_uid33_fxpToFPTest_q};
|
||||
|
||||
// expRPostExc_uid39_fxpToFPTest(MUX,38)@7
|
||||
assign expRPostExc_uid39_fxpToFPTest_s = excSelector_uid34_fxpToFPTest_q;
|
||||
always @(expRPostExc_uid39_fxpToFPTest_s or en or expR_uid38_fxpToFPTest_b or expZ_uid37_fxpToFPTest_q or expInf_uid28_fxpToFPTest_q)
|
||||
begin
|
||||
unique case (expRPostExc_uid39_fxpToFPTest_s)
|
||||
2'b00 : expRPostExc_uid39_fxpToFPTest_q = expR_uid38_fxpToFPTest_b;
|
||||
2'b01 : expRPostExc_uid39_fxpToFPTest_q = expZ_uid37_fxpToFPTest_q;
|
||||
2'b10 : expRPostExc_uid39_fxpToFPTest_q = expInf_uid28_fxpToFPTest_q;
|
||||
2'b11 : expRPostExc_uid39_fxpToFPTest_q = expInf_uid28_fxpToFPTest_q;
|
||||
default : expRPostExc_uid39_fxpToFPTest_q = 8'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// fracZ_uid31_fxpToFPTest(CONSTANT,30)
|
||||
assign fracZ_uid31_fxpToFPTest_q = 23'b00000000000000000000000;
|
||||
|
||||
// fracR_uid25_fxpToFPTest(BITSELECT,24)@6
|
||||
assign fracR_uid25_fxpToFPTest_in = expFracR_uid24_fxpToFPTest_q[23:0];
|
||||
assign fracR_uid25_fxpToFPTest_b = fracR_uid25_fxpToFPTest_in[23:1];
|
||||
|
||||
// redist7_fracR_uid25_fxpToFPTest_b_1(DELAY,102)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist7_fracR_uid25_fxpToFPTest_b_1_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist7_fracR_uid25_fxpToFPTest_b_1_q <= fracR_uid25_fxpToFPTest_b;
|
||||
end
|
||||
end
|
||||
|
||||
// excSelector_uid30_fxpToFPTest(LOGICAL,29)@7
|
||||
assign excSelector_uid30_fxpToFPTest_q = redist8_inIsZero_uid12_fxpToFPTest_q_2_q | ovf_uid29_fxpToFPTest_n | udf_uid27_fxpToFPTest_n;
|
||||
|
||||
// fracRPostExc_uid32_fxpToFPTest(MUX,31)@7
|
||||
assign fracRPostExc_uid32_fxpToFPTest_s = excSelector_uid30_fxpToFPTest_q;
|
||||
always @(fracRPostExc_uid32_fxpToFPTest_s or en or redist7_fracR_uid25_fxpToFPTest_b_1_q or fracZ_uid31_fxpToFPTest_q)
|
||||
begin
|
||||
unique case (fracRPostExc_uid32_fxpToFPTest_s)
|
||||
1'b0 : fracRPostExc_uid32_fxpToFPTest_q = redist7_fracR_uid25_fxpToFPTest_b_1_q;
|
||||
1'b1 : fracRPostExc_uid32_fxpToFPTest_q = fracZ_uid31_fxpToFPTest_q;
|
||||
default : fracRPostExc_uid32_fxpToFPTest_q = 23'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// outRes_uid40_fxpToFPTest(BITJOIN,39)@7
|
||||
assign outRes_uid40_fxpToFPTest_q = {redist11_signX_uid6_fxpToFPTest_b_7_q, expRPostExc_uid39_fxpToFPTest_q, fracRPostExc_uid32_fxpToFPTest_q};
|
||||
|
||||
// xOut(GPOUT,4)@7
|
||||
assign q = outRes_uid40_fxpToFPTest_q;
|
||||
|
||||
endmodule
|
||||
@@ -1,607 +0,0 @@
|
||||
// -------------------------------------------------------------------------
|
||||
// High Level Design Compiler for Intel(R) FPGAs Version 18.1 (Release Build #277)
|
||||
// Quartus Prime development tool and MATLAB/Simulink Interface
|
||||
//
|
||||
// Legal Notice: Copyright 2019 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly
|
||||
// subject to the terms and conditions of the Intel FPGA Software License
|
||||
// Agreement, Intel MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for
|
||||
// the sole purpose of programming logic devices manufactured by Intel
|
||||
// and sold by Intel or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
// ---------------------------------------------------------------------------
|
||||
|
||||
// SystemVerilog created from acl_utof
|
||||
// SystemVerilog created on Sun Dec 27 09:48:58 2020
|
||||
|
||||
|
||||
(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
|
||||
module acl_utof (
|
||||
input wire [31:0] a,
|
||||
input wire [0:0] en,
|
||||
output wire [31:0] q,
|
||||
input wire clk,
|
||||
input wire areset
|
||||
);
|
||||
|
||||
wire [0:0] GND_q;
|
||||
wire [5:0] maxCount_uid7_fxpToFPTest_q;
|
||||
wire [0:0] inIsZero_uid8_fxpToFPTest_qi;
|
||||
reg [0:0] inIsZero_uid8_fxpToFPTest_q;
|
||||
wire [7:0] msbIn_uid9_fxpToFPTest_q;
|
||||
wire [8:0] expPreRnd_uid10_fxpToFPTest_a;
|
||||
wire [8:0] expPreRnd_uid10_fxpToFPTest_b;
|
||||
logic [8:0] expPreRnd_uid10_fxpToFPTest_o;
|
||||
wire [8:0] expPreRnd_uid10_fxpToFPTest_q;
|
||||
wire [32:0] expFracRnd_uid12_fxpToFPTest_q;
|
||||
wire [0:0] sticky_uid16_fxpToFPTest_q;
|
||||
wire [0:0] nr_uid17_fxpToFPTest_q;
|
||||
wire [0:0] rnd_uid18_fxpToFPTest_qi;
|
||||
reg [0:0] rnd_uid18_fxpToFPTest_q;
|
||||
wire [34:0] expFracR_uid20_fxpToFPTest_a;
|
||||
wire [34:0] expFracR_uid20_fxpToFPTest_b;
|
||||
logic [34:0] expFracR_uid20_fxpToFPTest_o;
|
||||
wire [33:0] expFracR_uid20_fxpToFPTest_q;
|
||||
wire [23:0] fracR_uid21_fxpToFPTest_in;
|
||||
wire [22:0] fracR_uid21_fxpToFPTest_b;
|
||||
wire [9:0] expR_uid22_fxpToFPTest_b;
|
||||
wire [11:0] udf_uid23_fxpToFPTest_a;
|
||||
wire [11:0] udf_uid23_fxpToFPTest_b;
|
||||
logic [11:0] udf_uid23_fxpToFPTest_o;
|
||||
wire [0:0] udf_uid23_fxpToFPTest_n;
|
||||
wire [7:0] expInf_uid24_fxpToFPTest_q;
|
||||
wire [11:0] ovf_uid25_fxpToFPTest_a;
|
||||
wire [11:0] ovf_uid25_fxpToFPTest_b;
|
||||
logic [11:0] ovf_uid25_fxpToFPTest_o;
|
||||
wire [0:0] ovf_uid25_fxpToFPTest_n;
|
||||
wire [0:0] excSelector_uid26_fxpToFPTest_q;
|
||||
wire [22:0] fracZ_uid27_fxpToFPTest_q;
|
||||
wire [0:0] fracRPostExc_uid28_fxpToFPTest_s;
|
||||
reg [22:0] fracRPostExc_uid28_fxpToFPTest_q;
|
||||
wire [0:0] udfOrInZero_uid29_fxpToFPTest_q;
|
||||
wire [1:0] excSelector_uid30_fxpToFPTest_q;
|
||||
wire [7:0] expZ_uid33_fxpToFPTest_q;
|
||||
wire [7:0] expR_uid34_fxpToFPTest_in;
|
||||
wire [7:0] expR_uid34_fxpToFPTest_b;
|
||||
wire [1:0] expRPostExc_uid35_fxpToFPTest_s;
|
||||
reg [7:0] expRPostExc_uid35_fxpToFPTest_q;
|
||||
wire [31:0] outRes_uid36_fxpToFPTest_q;
|
||||
wire [31:0] zs_uid38_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [0:0] vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [0:0] vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_s;
|
||||
reg [31:0] vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [15:0] zs_uid43_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [0:0] vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [31:0] cStage_uid48_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [0:0] vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_s;
|
||||
reg [31:0] vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [0:0] vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [31:0] cStage_uid55_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [0:0] vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_s;
|
||||
reg [31:0] vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [3:0] zs_uid57_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [0:0] vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [31:0] cStage_uid62_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [0:0] vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_s;
|
||||
reg [31:0] vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [1:0] zs_uid64_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [0:0] vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [31:0] cStage_uid69_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [0:0] vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_s;
|
||||
reg [31:0] vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [0:0] vCount_uid73_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [31:0] cStage_uid76_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [0:0] vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_s;
|
||||
reg [31:0] vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [5:0] vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [7:0] vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_a;
|
||||
wire [7:0] vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_b;
|
||||
logic [7:0] vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_o;
|
||||
wire [0:0] vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_c;
|
||||
wire [0:0] vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_s;
|
||||
reg [5:0] vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
wire [1:0] l_uid13_fxpToFPTest_merged_bit_select_in;
|
||||
wire [0:0] l_uid13_fxpToFPTest_merged_bit_select_b;
|
||||
wire [0:0] l_uid13_fxpToFPTest_merged_bit_select_c;
|
||||
wire [15:0] rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b;
|
||||
wire [15:0] rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c;
|
||||
wire [7:0] rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b;
|
||||
wire [23:0] rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c;
|
||||
wire [3:0] rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b;
|
||||
wire [27:0] rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c;
|
||||
wire [1:0] rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b;
|
||||
wire [29:0] rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c;
|
||||
wire [0:0] rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b;
|
||||
wire [30:0] rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c;
|
||||
wire [30:0] fracRnd_uid11_fxpToFPTest_merged_bit_select_in;
|
||||
wire [23:0] fracRnd_uid11_fxpToFPTest_merged_bit_select_b;
|
||||
wire [6:0] fracRnd_uid11_fxpToFPTest_merged_bit_select_c;
|
||||
reg [23:0] redist0_fracRnd_uid11_fxpToFPTest_merged_bit_select_b_1_q;
|
||||
reg [6:0] redist1_fracRnd_uid11_fxpToFPTest_merged_bit_select_c_1_q;
|
||||
reg [5:0] redist2_vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest_q_1_q;
|
||||
reg [0:0] redist3_vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q_1_q;
|
||||
reg [0:0] redist4_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2_q;
|
||||
reg [0:0] redist4_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2_delay_0;
|
||||
reg [0:0] redist5_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_q;
|
||||
reg [0:0] redist5_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_delay_0;
|
||||
reg [0:0] redist5_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_delay_1;
|
||||
reg [0:0] redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_q;
|
||||
reg [0:0] redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_delay_0;
|
||||
reg [0:0] redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_delay_1;
|
||||
reg [0:0] redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_delay_2;
|
||||
reg [9:0] redist7_expR_uid22_fxpToFPTest_b_1_q;
|
||||
reg [22:0] redist8_fracR_uid21_fxpToFPTest_b_1_q;
|
||||
reg [32:0] redist9_expFracRnd_uid12_fxpToFPTest_q_1_q;
|
||||
reg [0:0] redist10_inIsZero_uid8_fxpToFPTest_q_2_q;
|
||||
|
||||
|
||||
// GND(CONSTANT,0)
|
||||
assign GND_q = 1'b0;
|
||||
|
||||
// expInf_uid24_fxpToFPTest(CONSTANT,23)
|
||||
assign expInf_uid24_fxpToFPTest_q = 8'b11111111;
|
||||
|
||||
// expZ_uid33_fxpToFPTest(CONSTANT,32)
|
||||
assign expZ_uid33_fxpToFPTest_q = 8'b00000000;
|
||||
|
||||
// rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select(BITSELECT,89)@4
|
||||
assign rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b = vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q[31:31];
|
||||
assign rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c = vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q[30:0];
|
||||
|
||||
// cStage_uid76_lzcShifterZ1_uid6_fxpToFPTest(BITJOIN,75)@4
|
||||
assign cStage_uid76_lzcShifterZ1_uid6_fxpToFPTest_q = {rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c, GND_q};
|
||||
|
||||
// rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select(BITSELECT,88)@4
|
||||
assign rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b = vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q[31:30];
|
||||
assign rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c = vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q[29:0];
|
||||
|
||||
// zs_uid64_lzcShifterZ1_uid6_fxpToFPTest(CONSTANT,63)
|
||||
assign zs_uid64_lzcShifterZ1_uid6_fxpToFPTest_q = 2'b00;
|
||||
|
||||
// cStage_uid69_lzcShifterZ1_uid6_fxpToFPTest(BITJOIN,68)@4
|
||||
assign cStage_uid69_lzcShifterZ1_uid6_fxpToFPTest_q = {rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c, zs_uid64_lzcShifterZ1_uid6_fxpToFPTest_q};
|
||||
|
||||
// rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select(BITSELECT,87)@3
|
||||
assign rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b = vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q[31:28];
|
||||
assign rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c = vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q[27:0];
|
||||
|
||||
// zs_uid57_lzcShifterZ1_uid6_fxpToFPTest(CONSTANT,56)
|
||||
assign zs_uid57_lzcShifterZ1_uid6_fxpToFPTest_q = 4'b0000;
|
||||
|
||||
// cStage_uid62_lzcShifterZ1_uid6_fxpToFPTest(BITJOIN,61)@3
|
||||
assign cStage_uid62_lzcShifterZ1_uid6_fxpToFPTest_q = {rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c, zs_uid57_lzcShifterZ1_uid6_fxpToFPTest_q};
|
||||
|
||||
// rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select(BITSELECT,86)@2
|
||||
assign rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b = vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q[31:24];
|
||||
assign rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c = vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q[23:0];
|
||||
|
||||
// cStage_uid55_lzcShifterZ1_uid6_fxpToFPTest(BITJOIN,54)@2
|
||||
assign cStage_uid55_lzcShifterZ1_uid6_fxpToFPTest_q = {rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c, expZ_uid33_fxpToFPTest_q};
|
||||
|
||||
// rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select(BITSELECT,85)@1
|
||||
assign rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b = vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q[31:16];
|
||||
assign rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c = vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q[15:0];
|
||||
|
||||
// zs_uid43_lzcShifterZ1_uid6_fxpToFPTest(CONSTANT,42)
|
||||
assign zs_uid43_lzcShifterZ1_uid6_fxpToFPTest_q = 16'b0000000000000000;
|
||||
|
||||
// cStage_uid48_lzcShifterZ1_uid6_fxpToFPTest(BITJOIN,47)@1
|
||||
assign cStage_uid48_lzcShifterZ1_uid6_fxpToFPTest_q = {rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c, zs_uid43_lzcShifterZ1_uid6_fxpToFPTest_q};
|
||||
|
||||
// zs_uid38_lzcShifterZ1_uid6_fxpToFPTest(CONSTANT,37)
|
||||
assign zs_uid38_lzcShifterZ1_uid6_fxpToFPTest_q = 32'b00000000000000000000000000000000;
|
||||
|
||||
// vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest(LOGICAL,39)@0
|
||||
assign vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q = a == zs_uid38_lzcShifterZ1_uid6_fxpToFPTest_q ? 1'b1 : 1'b0;
|
||||
|
||||
// vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest(MUX,41)@0 + 1
|
||||
assign vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_s = vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
unique case (vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_s)
|
||||
1'b0 : vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q <= a;
|
||||
1'b1 : vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q <= zs_uid38_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
default : vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest(LOGICAL,44)@1
|
||||
assign vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q = rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b == zs_uid43_lzcShifterZ1_uid6_fxpToFPTest_q ? 1'b1 : 1'b0;
|
||||
|
||||
// vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest(MUX,48)@1 + 1
|
||||
assign vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_s = vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
unique case (vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_s)
|
||||
1'b0 : vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q <= vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
1'b1 : vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q <= cStage_uid48_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
default : vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest(LOGICAL,51)@2
|
||||
assign vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q = rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b == expZ_uid33_fxpToFPTest_q ? 1'b1 : 1'b0;
|
||||
|
||||
// vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest(MUX,55)@2 + 1
|
||||
assign vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_s = vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
unique case (vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_s)
|
||||
1'b0 : vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q <= vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
1'b1 : vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q <= cStage_uid55_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
default : vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest(LOGICAL,58)@3
|
||||
assign vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q = rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b == zs_uid57_lzcShifterZ1_uid6_fxpToFPTest_q ? 1'b1 : 1'b0;
|
||||
|
||||
// vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest(MUX,62)@3 + 1
|
||||
assign vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_s = vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
unique case (vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_s)
|
||||
1'b0 : vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q <= vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
1'b1 : vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q <= cStage_uid62_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
default : vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest(LOGICAL,65)@4
|
||||
assign vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q = rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b == zs_uid64_lzcShifterZ1_uid6_fxpToFPTest_q ? 1'b1 : 1'b0;
|
||||
|
||||
// vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest(MUX,69)@4
|
||||
assign vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_s = vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
always @(vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_s or en or vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q or cStage_uid69_lzcShifterZ1_uid6_fxpToFPTest_q)
|
||||
begin
|
||||
unique case (vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_s)
|
||||
1'b0 : vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q = vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
1'b1 : vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q = cStage_uid69_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
default : vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q = 32'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// vCount_uid73_lzcShifterZ1_uid6_fxpToFPTest(LOGICAL,72)@4
|
||||
assign vCount_uid73_lzcShifterZ1_uid6_fxpToFPTest_q = rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b == GND_q ? 1'b1 : 1'b0;
|
||||
|
||||
// vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest(MUX,76)@4
|
||||
assign vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_s = vCount_uid73_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
always @(vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_s or en or vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q or cStage_uid76_lzcShifterZ1_uid6_fxpToFPTest_q)
|
||||
begin
|
||||
unique case (vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_s)
|
||||
1'b0 : vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_q = vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
1'b1 : vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_q = cStage_uid76_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
default : vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_q = 32'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// fracRnd_uid11_fxpToFPTest_merged_bit_select(BITSELECT,90)@4
|
||||
assign fracRnd_uid11_fxpToFPTest_merged_bit_select_in = vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_q[30:0];
|
||||
assign fracRnd_uid11_fxpToFPTest_merged_bit_select_b = fracRnd_uid11_fxpToFPTest_merged_bit_select_in[30:7];
|
||||
assign fracRnd_uid11_fxpToFPTest_merged_bit_select_c = fracRnd_uid11_fxpToFPTest_merged_bit_select_in[6:0];
|
||||
|
||||
// redist1_fracRnd_uid11_fxpToFPTest_merged_bit_select_c_1(DELAY,92)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist1_fracRnd_uid11_fxpToFPTest_merged_bit_select_c_1_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist1_fracRnd_uid11_fxpToFPTest_merged_bit_select_c_1_q <= fracRnd_uid11_fxpToFPTest_merged_bit_select_c;
|
||||
end
|
||||
end
|
||||
|
||||
// sticky_uid16_fxpToFPTest(LOGICAL,15)@5
|
||||
assign sticky_uid16_fxpToFPTest_q = redist1_fracRnd_uid11_fxpToFPTest_merged_bit_select_c_1_q != 7'b0000000 ? 1'b1 : 1'b0;
|
||||
|
||||
// nr_uid17_fxpToFPTest(LOGICAL,16)@5
|
||||
assign nr_uid17_fxpToFPTest_q = ~ (l_uid13_fxpToFPTest_merged_bit_select_c);
|
||||
|
||||
// maxCount_uid7_fxpToFPTest(CONSTANT,6)
|
||||
assign maxCount_uid7_fxpToFPTest_q = 6'b100000;
|
||||
|
||||
// redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4(DELAY,97)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_delay_0 <= '0;
|
||||
redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_delay_1 <= '0;
|
||||
redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_delay_2 <= '0;
|
||||
redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_delay_0 <= vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_delay_1 <= redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_delay_0;
|
||||
redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_delay_2 <= redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_delay_1;
|
||||
redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_q <= redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_delay_2;
|
||||
end
|
||||
end
|
||||
|
||||
// redist5_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3(DELAY,96)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist5_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_delay_0 <= '0;
|
||||
redist5_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_delay_1 <= '0;
|
||||
redist5_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist5_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_delay_0 <= vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
redist5_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_delay_1 <= redist5_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_delay_0;
|
||||
redist5_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_q <= redist5_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_delay_1;
|
||||
end
|
||||
end
|
||||
|
||||
// redist4_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2(DELAY,95)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist4_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2_delay_0 <= '0;
|
||||
redist4_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist4_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2_delay_0 <= vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
redist4_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2_q <= redist4_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2_delay_0;
|
||||
end
|
||||
end
|
||||
|
||||
// redist3_vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q_1(DELAY,94)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist3_vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q_1_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist3_vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q_1_q <= vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
end
|
||||
end
|
||||
|
||||
// vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest(BITJOIN,77)@4
|
||||
assign vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest_q = {redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_q, redist5_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_q, redist4_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2_q, redist3_vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q_1_q, vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q, vCount_uid73_lzcShifterZ1_uid6_fxpToFPTest_q};
|
||||
|
||||
// redist2_vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest_q_1(DELAY,93)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist2_vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest_q_1_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist2_vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest_q_1_q <= vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest_q;
|
||||
end
|
||||
end
|
||||
|
||||
// vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest(COMPARE,79)@4 + 1
|
||||
assign vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_a = {2'b00, maxCount_uid7_fxpToFPTest_q};
|
||||
assign vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_b = {2'b00, vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest_q};
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_o <= 8'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_o <= $unsigned(vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_a) - $unsigned(vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_b);
|
||||
end
|
||||
end
|
||||
assign vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_c[0] = vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_o[7];
|
||||
|
||||
// vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest(MUX,81)@5
|
||||
assign vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_s = vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_c;
|
||||
always @(vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_s or en or redist2_vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest_q_1_q or maxCount_uid7_fxpToFPTest_q)
|
||||
begin
|
||||
unique case (vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_s)
|
||||
1'b0 : vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_q = redist2_vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest_q_1_q;
|
||||
1'b1 : vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_q = maxCount_uid7_fxpToFPTest_q;
|
||||
default : vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_q = 6'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// msbIn_uid9_fxpToFPTest(CONSTANT,8)
|
||||
assign msbIn_uid9_fxpToFPTest_q = 8'b10011110;
|
||||
|
||||
// expPreRnd_uid10_fxpToFPTest(SUB,9)@5
|
||||
assign expPreRnd_uid10_fxpToFPTest_a = {1'b0, msbIn_uid9_fxpToFPTest_q};
|
||||
assign expPreRnd_uid10_fxpToFPTest_b = {3'b000, vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_q};
|
||||
assign expPreRnd_uid10_fxpToFPTest_o = $unsigned(expPreRnd_uid10_fxpToFPTest_a) - $unsigned(expPreRnd_uid10_fxpToFPTest_b);
|
||||
assign expPreRnd_uid10_fxpToFPTest_q = expPreRnd_uid10_fxpToFPTest_o[8:0];
|
||||
|
||||
// redist0_fracRnd_uid11_fxpToFPTest_merged_bit_select_b_1(DELAY,91)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist0_fracRnd_uid11_fxpToFPTest_merged_bit_select_b_1_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist0_fracRnd_uid11_fxpToFPTest_merged_bit_select_b_1_q <= fracRnd_uid11_fxpToFPTest_merged_bit_select_b;
|
||||
end
|
||||
end
|
||||
|
||||
// expFracRnd_uid12_fxpToFPTest(BITJOIN,11)@5
|
||||
assign expFracRnd_uid12_fxpToFPTest_q = {expPreRnd_uid10_fxpToFPTest_q, redist0_fracRnd_uid11_fxpToFPTest_merged_bit_select_b_1_q};
|
||||
|
||||
// l_uid13_fxpToFPTest_merged_bit_select(BITSELECT,84)@5
|
||||
assign l_uid13_fxpToFPTest_merged_bit_select_in = expFracRnd_uid12_fxpToFPTest_q[1:0];
|
||||
assign l_uid13_fxpToFPTest_merged_bit_select_b = l_uid13_fxpToFPTest_merged_bit_select_in[1:1];
|
||||
assign l_uid13_fxpToFPTest_merged_bit_select_c = l_uid13_fxpToFPTest_merged_bit_select_in[0:0];
|
||||
|
||||
// rnd_uid18_fxpToFPTest(LOGICAL,17)@5 + 1
|
||||
assign rnd_uid18_fxpToFPTest_qi = l_uid13_fxpToFPTest_merged_bit_select_b | nr_uid17_fxpToFPTest_q | sticky_uid16_fxpToFPTest_q;
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) )
|
||||
rnd_uid18_fxpToFPTest_delay ( .xin(rnd_uid18_fxpToFPTest_qi), .xout(rnd_uid18_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// redist9_expFracRnd_uid12_fxpToFPTest_q_1(DELAY,100)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist9_expFracRnd_uid12_fxpToFPTest_q_1_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist9_expFracRnd_uid12_fxpToFPTest_q_1_q <= expFracRnd_uid12_fxpToFPTest_q;
|
||||
end
|
||||
end
|
||||
|
||||
// expFracR_uid20_fxpToFPTest(ADD,19)@6
|
||||
assign expFracR_uid20_fxpToFPTest_a = {{2{redist9_expFracRnd_uid12_fxpToFPTest_q_1_q[32]}}, redist9_expFracRnd_uid12_fxpToFPTest_q_1_q};
|
||||
assign expFracR_uid20_fxpToFPTest_b = {34'b0000000000000000000000000000000000, rnd_uid18_fxpToFPTest_q};
|
||||
assign expFracR_uid20_fxpToFPTest_o = $signed(expFracR_uid20_fxpToFPTest_a) + $signed(expFracR_uid20_fxpToFPTest_b);
|
||||
assign expFracR_uid20_fxpToFPTest_q = expFracR_uid20_fxpToFPTest_o[33:0];
|
||||
|
||||
// expR_uid22_fxpToFPTest(BITSELECT,21)@6
|
||||
assign expR_uid22_fxpToFPTest_b = expFracR_uid20_fxpToFPTest_q[33:24];
|
||||
|
||||
// redist7_expR_uid22_fxpToFPTest_b_1(DELAY,98)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist7_expR_uid22_fxpToFPTest_b_1_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist7_expR_uid22_fxpToFPTest_b_1_q <= expR_uid22_fxpToFPTest_b;
|
||||
end
|
||||
end
|
||||
|
||||
// expR_uid34_fxpToFPTest(BITSELECT,33)@7
|
||||
assign expR_uid34_fxpToFPTest_in = redist7_expR_uid22_fxpToFPTest_b_1_q[7:0];
|
||||
assign expR_uid34_fxpToFPTest_b = expR_uid34_fxpToFPTest_in[7:0];
|
||||
|
||||
// ovf_uid25_fxpToFPTest(COMPARE,24)@7
|
||||
assign ovf_uid25_fxpToFPTest_a = {{2{redist7_expR_uid22_fxpToFPTest_b_1_q[9]}}, redist7_expR_uid22_fxpToFPTest_b_1_q};
|
||||
assign ovf_uid25_fxpToFPTest_b = {4'b0000, expInf_uid24_fxpToFPTest_q};
|
||||
assign ovf_uid25_fxpToFPTest_o = $signed(ovf_uid25_fxpToFPTest_a) - $signed(ovf_uid25_fxpToFPTest_b);
|
||||
assign ovf_uid25_fxpToFPTest_n[0] = ~ (ovf_uid25_fxpToFPTest_o[11]);
|
||||
|
||||
// inIsZero_uid8_fxpToFPTest(LOGICAL,7)@5 + 1
|
||||
assign inIsZero_uid8_fxpToFPTest_qi = vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_q == maxCount_uid7_fxpToFPTest_q ? 1'b1 : 1'b0;
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) )
|
||||
inIsZero_uid8_fxpToFPTest_delay ( .xin(inIsZero_uid8_fxpToFPTest_qi), .xout(inIsZero_uid8_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// redist10_inIsZero_uid8_fxpToFPTest_q_2(DELAY,101)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist10_inIsZero_uid8_fxpToFPTest_q_2_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist10_inIsZero_uid8_fxpToFPTest_q_2_q <= inIsZero_uid8_fxpToFPTest_q;
|
||||
end
|
||||
end
|
||||
|
||||
// udf_uid23_fxpToFPTest(COMPARE,22)@7
|
||||
assign udf_uid23_fxpToFPTest_a = {11'b00000000000, GND_q};
|
||||
assign udf_uid23_fxpToFPTest_b = {{2{redist7_expR_uid22_fxpToFPTest_b_1_q[9]}}, redist7_expR_uid22_fxpToFPTest_b_1_q};
|
||||
assign udf_uid23_fxpToFPTest_o = $signed(udf_uid23_fxpToFPTest_a) - $signed(udf_uid23_fxpToFPTest_b);
|
||||
assign udf_uid23_fxpToFPTest_n[0] = ~ (udf_uid23_fxpToFPTest_o[11]);
|
||||
|
||||
// udfOrInZero_uid29_fxpToFPTest(LOGICAL,28)@7
|
||||
assign udfOrInZero_uid29_fxpToFPTest_q = udf_uid23_fxpToFPTest_n | redist10_inIsZero_uid8_fxpToFPTest_q_2_q;
|
||||
|
||||
// excSelector_uid30_fxpToFPTest(BITJOIN,29)@7
|
||||
assign excSelector_uid30_fxpToFPTest_q = {ovf_uid25_fxpToFPTest_n, udfOrInZero_uid29_fxpToFPTest_q};
|
||||
|
||||
// expRPostExc_uid35_fxpToFPTest(MUX,34)@7
|
||||
assign expRPostExc_uid35_fxpToFPTest_s = excSelector_uid30_fxpToFPTest_q;
|
||||
always @(expRPostExc_uid35_fxpToFPTest_s or en or expR_uid34_fxpToFPTest_b or expZ_uid33_fxpToFPTest_q or expInf_uid24_fxpToFPTest_q)
|
||||
begin
|
||||
unique case (expRPostExc_uid35_fxpToFPTest_s)
|
||||
2'b00 : expRPostExc_uid35_fxpToFPTest_q = expR_uid34_fxpToFPTest_b;
|
||||
2'b01 : expRPostExc_uid35_fxpToFPTest_q = expZ_uid33_fxpToFPTest_q;
|
||||
2'b10 : expRPostExc_uid35_fxpToFPTest_q = expInf_uid24_fxpToFPTest_q;
|
||||
2'b11 : expRPostExc_uid35_fxpToFPTest_q = expInf_uid24_fxpToFPTest_q;
|
||||
default : expRPostExc_uid35_fxpToFPTest_q = 8'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// fracZ_uid27_fxpToFPTest(CONSTANT,26)
|
||||
assign fracZ_uid27_fxpToFPTest_q = 23'b00000000000000000000000;
|
||||
|
||||
// fracR_uid21_fxpToFPTest(BITSELECT,20)@6
|
||||
assign fracR_uid21_fxpToFPTest_in = expFracR_uid20_fxpToFPTest_q[23:0];
|
||||
assign fracR_uid21_fxpToFPTest_b = fracR_uid21_fxpToFPTest_in[23:1];
|
||||
|
||||
// redist8_fracR_uid21_fxpToFPTest_b_1(DELAY,99)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
redist8_fracR_uid21_fxpToFPTest_b_1_q <= '0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
redist8_fracR_uid21_fxpToFPTest_b_1_q <= fracR_uid21_fxpToFPTest_b;
|
||||
end
|
||||
end
|
||||
|
||||
// excSelector_uid26_fxpToFPTest(LOGICAL,25)@7
|
||||
assign excSelector_uid26_fxpToFPTest_q = redist10_inIsZero_uid8_fxpToFPTest_q_2_q | ovf_uid25_fxpToFPTest_n | udf_uid23_fxpToFPTest_n;
|
||||
|
||||
// fracRPostExc_uid28_fxpToFPTest(MUX,27)@7
|
||||
assign fracRPostExc_uid28_fxpToFPTest_s = excSelector_uid26_fxpToFPTest_q;
|
||||
always @(fracRPostExc_uid28_fxpToFPTest_s or en or redist8_fracR_uid21_fxpToFPTest_b_1_q or fracZ_uid27_fxpToFPTest_q)
|
||||
begin
|
||||
unique case (fracRPostExc_uid28_fxpToFPTest_s)
|
||||
1'b0 : fracRPostExc_uid28_fxpToFPTest_q = redist8_fracR_uid21_fxpToFPTest_b_1_q;
|
||||
1'b1 : fracRPostExc_uid28_fxpToFPTest_q = fracZ_uid27_fxpToFPTest_q;
|
||||
default : fracRPostExc_uid28_fxpToFPTest_q = 23'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// outRes_uid36_fxpToFPTest(BITJOIN,35)@7
|
||||
assign outRes_uid36_fxpToFPTest_q = {GND_q, expRPostExc_uid35_fxpToFPTest_q, fracRPostExc_uid28_fxpToFPTest_q};
|
||||
|
||||
// xOut(GPOUT,4)@7
|
||||
assign q = outRes_uid36_fxpToFPTest_q;
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user