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Merge branch 'master' into graphics

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This commit is contained in:
Blaise Tine
2021-05-26 23:33:06 -07:00
parent f4c52a41fa 321a2c5e1b
commit d42171d2ed
120 changed files with 4269 additions and 2329 deletions
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72
hw/rtl/VX_core.v
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@@ -9,20 +9,20 @@ module VX_core #(
input wire clk,
input wire reset,
// DRAM request
output wire dram_req_valid,
output wire dram_req_rw,
output wire [`DDRAM_BYTEEN_WIDTH-1:0] dram_req_byteen,
output wire [`DDRAM_ADDR_WIDTH-1:0] dram_req_addr,
output wire [`DDRAM_LINE_WIDTH-1:0] dram_req_data,
output wire [`XDRAM_TAG_WIDTH-1:0] dram_req_tag,
input wire dram_req_ready,
// Memory request
output wire mem_req_valid,
output wire mem_req_rw,
output wire [`DMEM_BYTEEN_WIDTH-1:0] mem_req_byteen,
output wire [`DMEM_ADDR_WIDTH-1:0] mem_req_addr,
output wire [`DMEM_LINE_WIDTH-1:0] mem_req_data,
output wire [`XMEM_TAG_WIDTH-1:0] mem_req_tag,
input wire mem_req_ready,
// DRAM reponse
input wire dram_rsp_valid,
input wire [`DDRAM_LINE_WIDTH-1:0] dram_rsp_data,
input wire [`XDRAM_TAG_WIDTH-1:0] dram_rsp_tag,
output wire dram_rsp_ready,
// Memory reponse
input wire mem_rsp_valid,
input wire [`DMEM_LINE_WIDTH-1:0] mem_rsp_data,
input wire [`XMEM_TAG_WIDTH-1:0] mem_rsp_tag,
output wire mem_rsp_ready,
// CSR request
input wire csr_req_valid,
@@ -44,29 +44,29 @@ module VX_core #(
VX_perf_memsys_if perf_memsys_if();
`endif
VX_cache_dram_req_if #(
.DRAM_LINE_WIDTH(`DDRAM_LINE_WIDTH),
.DRAM_ADDR_WIDTH(`DDRAM_ADDR_WIDTH),
.DRAM_TAG_WIDTH(`XDRAM_TAG_WIDTH)
) dram_req_if();
VX_cache_mem_req_if #(
.MEM_LINE_WIDTH(`DMEM_LINE_WIDTH),
.MEM_ADDR_WIDTH(`DMEM_ADDR_WIDTH),
.MEM_TAG_WIDTH(`XMEM_TAG_WIDTH)
) mem_req_if();
VX_cache_dram_rsp_if #(
.DRAM_LINE_WIDTH(`DDRAM_LINE_WIDTH),
.DRAM_TAG_WIDTH(`XDRAM_TAG_WIDTH)
) dram_rsp_if();
VX_cache_mem_rsp_if #(
.MEM_LINE_WIDTH(`DMEM_LINE_WIDTH),
.MEM_TAG_WIDTH(`XMEM_TAG_WIDTH)
) mem_rsp_if();
assign dram_req_valid = dram_req_if.valid;
assign dram_req_rw = dram_req_if.rw;
assign dram_req_byteen= dram_req_if.byteen;
assign dram_req_addr = dram_req_if.addr;
assign dram_req_data = dram_req_if.data;
assign dram_req_tag = dram_req_if.tag;
assign dram_req_if.ready = dram_req_ready;
assign mem_req_valid = mem_req_if.valid;
assign mem_req_rw = mem_req_if.rw;
assign mem_req_byteen= mem_req_if.byteen;
assign mem_req_addr = mem_req_if.addr;
assign mem_req_data = mem_req_if.data;
assign mem_req_tag = mem_req_if.tag;
assign mem_req_if.ready = mem_req_ready;
assign dram_rsp_if.valid = dram_rsp_valid;
assign dram_rsp_if.data = dram_rsp_data;
assign dram_rsp_if.tag = dram_rsp_tag;
assign dram_rsp_ready = dram_rsp_if.ready;
assign mem_rsp_if.valid = mem_rsp_valid;
assign mem_rsp_if.data = mem_rsp_data;
assign mem_rsp_if.tag = mem_rsp_tag;
assign mem_rsp_ready = mem_rsp_if.ready;
//--
@@ -168,9 +168,9 @@ module VX_core #(
.icache_core_req_if (icache_core_req_if),
.icache_core_rsp_if (icache_core_rsp_if),
// DRAM
.dram_req_if (dram_req_if),
.dram_rsp_if (dram_rsp_if)
// Memory
.mem_req_if (mem_req_if),
.mem_rsp_if (mem_rsp_if)
);
endmodule