memory interface refactoring

2021-07-20 21:06:55 -07:00
parent 80cf1f26f9
commit d3b788784a
14 changed files with 144 additions and 144 deletions
--- a/hw/rtl/interfaces/VX_icache_req_if.v
+++ b/hw/rtl/interfaces/VX_icache_req_if.v
@@ -0,0 +1,18 @@
+`ifndef VX_ICACHE_CORE_REQ_IF
+`define VX_ICACHE_CORE_REQ_IF
+
+`include "../cache/VX_cache_define.vh"
+
+interface VX_icache_core_req_if #(
+    parameter WORD_SIZE      = 1,
+    parameter CORE_TAG_WIDTH = 1
+) ();
+
+    wire                        valid;
+    wire [`WORD_ADDR_WIDTH-1:0] addr;
+    wire [CORE_TAG_WIDTH-1:0]   tag;    
+    wire                        ready;
+
+endinterface
+
+`endif