memory interface refactoring

2021-07-20 21:06:55 -07:00
parent 80cf1f26f9
commit d3b788784a
14 changed files with 144 additions and 144 deletions
--- a/hw/rtl/interfaces/VX_dcache_rsp_if.v
+++ b/hw/rtl/interfaces/VX_dcache_rsp_if.v
@@ -0,0 +1,20 @@
+`ifndef VX_DCACHE_CORE_RSP_IF
+`define VX_DCACHE_CORE_RSP_IF
+
+`include "../cache/VX_cache_define.vh"
+
+interface VX_dcache_core_rsp_if #(
+    parameter NUM_REQS       = 1,
+    parameter WORD_SIZE      = 1,
+    parameter CORE_TAG_WIDTH = 1
+) ();
+
+    wire                                    valid;
+    wire [NUM_REQS-1:0]                     tmask;
+    wire [NUM_REQS-1:0][`WORD_WIDTH-1:0]    data;
+    wire [CORE_TAG_WIDTH-1:0]               tag;
+    wire                                    ready;
+
+endinterface
+
+`endif