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memory interface refactoring

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This commit is contained in:
Blaise Tine
2021-07-20 21:06:55 -07:00
parent 80cf1f26f9
commit d3b788784a
14 changed files with 144 additions and 144 deletions
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64
hw/rtl/VX_pipeline.v
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@@ -48,63 +48,63 @@ module VX_pipeline #(
// Dcache request
//
VX_dcache_core_req_if #(
VX_dcache_req_if #(
.NUM_REQS(`NUM_THREADS),
.WORD_SIZE(4),
.CORE_TAG_WIDTH(`DCORE_TAG_WIDTH)
) dcache_core_req_if();
) dcache_req_if();
assign dcache_req_valid = dcache_core_req_if.valid;
assign dcache_req_rw = dcache_core_req_if.rw;
assign dcache_req_byteen = dcache_core_req_if.byteen;
assign dcache_req_addr = dcache_core_req_if.addr;
assign dcache_req_data = dcache_core_req_if.data;
assign dcache_req_tag = dcache_core_req_if.tag;
assign dcache_core_req_if.ready = dcache_req_ready;
assign dcache_req_valid = dcache_req_if.valid;
assign dcache_req_rw = dcache_req_if.rw;
assign dcache_req_byteen = dcache_req_if.byteen;
assign dcache_req_addr = dcache_req_if.addr;
assign dcache_req_data = dcache_req_if.data;
assign dcache_req_tag = dcache_req_if.tag;
assign dcache_req_if.ready = dcache_req_ready;
//
// Dcache response
//
VX_dcache_core_rsp_if #(
VX_dcache_rsp_if #(
.NUM_REQS(`NUM_THREADS),
.WORD_SIZE(4),
.CORE_TAG_WIDTH(`DCORE_TAG_WIDTH)
) dcache_core_rsp_if();
) dcache_rsp_if();
assign dcache_core_rsp_if.valid = dcache_rsp_valid;
assign dcache_core_rsp_if.tmask = dcache_rsp_tmask;
assign dcache_core_rsp_if.data = dcache_rsp_data;
assign dcache_core_rsp_if.tag = dcache_rsp_tag;
assign dcache_rsp_ready = dcache_core_rsp_if.ready;
assign dcache_rsp_if.valid = dcache_rsp_valid;
assign dcache_rsp_if.tmask = dcache_rsp_tmask;
assign dcache_rsp_if.data = dcache_rsp_data;
assign dcache_rsp_if.tag = dcache_rsp_tag;
assign dcache_rsp_ready = dcache_rsp_if.ready;
//
// Icache request
//
VX_icache_core_req_if #(
VX_icache_req_if #(
.WORD_SIZE(4),
.CORE_TAG_WIDTH(`ICORE_TAG_WIDTH)
) icache_core_req_if();
) icache_req_if();
assign icache_req_valid = icache_core_req_if.valid;
assign icache_req_addr = icache_core_req_if.addr;
assign icache_req_tag = icache_core_req_if.tag;
assign icache_core_req_if.ready = icache_req_ready;
assign icache_req_valid = icache_req_if.valid;
assign icache_req_addr = icache_req_if.addr;
assign icache_req_tag = icache_req_if.tag;
assign icache_req_if.ready = icache_req_ready;
//
// Icache response
//
VX_icache_core_rsp_if #(
VX_icache_rsp_if #(
.WORD_SIZE(4),
.CORE_TAG_WIDTH(`ICORE_TAG_WIDTH)
) icache_core_rsp_if();
) icache_rsp_if();
assign icache_core_rsp_if.valid = icache_rsp_valid;
assign icache_core_rsp_if.data = icache_rsp_data;
assign icache_core_rsp_if.tag = icache_rsp_tag;
assign icache_rsp_ready = icache_core_rsp_if.ready;
assign icache_rsp_if.valid = icache_rsp_valid;
assign icache_rsp_if.data = icache_rsp_data;
assign icache_rsp_if.tag = icache_rsp_tag;
assign icache_rsp_ready = icache_rsp_if.ready;
///////////////////////////////////////////////////////////////////////////
@@ -144,8 +144,8 @@ module VX_pipeline #(
`SCOPE_BIND_VX_pipeline_fetch
.clk (clk),
.reset (fetch_reset),
.icache_req_if (icache_core_req_if),
.icache_rsp_if (icache_core_rsp_if),
.icache_req_if (icache_req_if),
.icache_rsp_if (icache_rsp_if),
.wstall_if (wstall_if),
.join_if (join_if),
.warp_ctl_if (warp_ctl_if),
@@ -200,8 +200,8 @@ module VX_pipeline #(
.perf_pipeline_if (perf_pipeline_if),
`endif
.dcache_req_if (dcache_core_req_if),
.dcache_rsp_if (dcache_core_rsp_if),
.dcache_req_if (dcache_req_if),
.dcache_rsp_if (dcache_rsp_if),
.cmt_to_csr_if (cmt_to_csr_if),