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memory interface refactoring

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This commit is contained in:
Blaise Tine
2021-07-20 21:06:55 -07:00
parent 80cf1f26f9
commit d3b788784a
14 changed files with 144 additions and 144 deletions
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108
hw/rtl/VX_mem_unit.v
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@@ -5,63 +5,63 @@ module VX_mem_unit # (
) (
`SCOPE_IO_VX_mem_unit
input wire clk,
input wire reset,
input wire clk,
input wire reset,
`ifdef PERF_ENABLE
VX_perf_memsys_if perf_memsys_if,
VX_perf_memsys_if perf_memsys_if,
`endif
// Core <-> Dcache
VX_dcache_core_req_if dcache_core_req_if,
VX_dcache_core_rsp_if dcache_core_rsp_if,
VX_dcache_req_if dcache_req_if,
VX_dcache_rsp_if dcache_rsp_if,
// Core <-> Icache
VX_icache_core_req_if icache_core_req_if,
VX_icache_core_rsp_if icache_core_rsp_if,
VX_icache_req_if icache_req_if,
VX_icache_rsp_if icache_rsp_if,
// Memory
VX_cache_mem_req_if mem_req_if,
VX_cache_mem_rsp_if mem_rsp_if
VX_mem_req_if mem_req_if,
VX_mem_rsp_if mem_rsp_if
);
`ifdef PERF_ENABLE
VX_perf_cache_if perf_icache_if(), perf_dcache_if(), perf_smem_if();
`endif
VX_cache_mem_req_if #(
VX_mem_req_if #(
.MEM_LINE_WIDTH (`IMEM_LINE_WIDTH),
.MEM_ADDR_WIDTH (`IMEM_ADDR_WIDTH),
.MEM_TAG_WIDTH (`IMEM_TAG_WIDTH)
) icache_mem_req_if();
VX_cache_mem_rsp_if #(
VX_mem_rsp_if #(
.MEM_LINE_WIDTH (`IMEM_LINE_WIDTH),
.MEM_TAG_WIDTH (`IMEM_TAG_WIDTH)
) icache_mem_rsp_if();
VX_cache_mem_req_if #(
VX_mem_req_if #(
.MEM_LINE_WIDTH (`DMEM_LINE_WIDTH),
.MEM_ADDR_WIDTH (`DMEM_ADDR_WIDTH),
.MEM_TAG_WIDTH (`DMEM_TAG_WIDTH)
) dcache_mem_req_if();
VX_cache_mem_rsp_if #(
VX_mem_rsp_if #(
.MEM_LINE_WIDTH (`DMEM_LINE_WIDTH),
.MEM_TAG_WIDTH (`DMEM_TAG_WIDTH)
) dcache_mem_rsp_if();
VX_dcache_core_req_if #(
VX_dcache_req_if #(
.NUM_REQS (`DNUM_REQS),
.WORD_SIZE (`DWORD_SIZE),
.CORE_TAG_WIDTH (`DCORE_TAG_WIDTH-`SM_ENABLE)
) dcache_req_if();
) dcache_req_tmp_if();
VX_dcache_core_rsp_if #(
VX_dcache_rsp_if #(
.NUM_REQS (`DNUM_REQS),
.WORD_SIZE (`DWORD_SIZE),
.CORE_TAG_WIDTH (`DCORE_TAG_WIDTH-`SM_ENABLE)
) dcache_rsp_if();
) dcache_rsp_tmp_if();
`RESET_RELAY (icache_reset);
`RESET_RELAY (dcache_reset);
@@ -89,19 +89,19 @@ module VX_mem_unit # (
.reset (icache_reset),
// Core request
.core_req_valid (icache_core_req_if.valid),
.core_req_valid (icache_req_if.valid),
.core_req_rw (1'b0),
.core_req_byteen ({`IWORD_SIZE{1'b1}}),
.core_req_addr (icache_core_req_if.addr),
.core_req_addr (icache_req_if.addr),
.core_req_data ('x),
.core_req_tag (icache_core_req_if.tag),
.core_req_ready (icache_core_req_if.ready),
.core_req_tag (icache_req_if.tag),
.core_req_ready (icache_req_if.ready),
// Core response
.core_rsp_valid (icache_core_rsp_if.valid),
.core_rsp_data (icache_core_rsp_if.data),
.core_rsp_tag (icache_core_rsp_if.tag),
.core_rsp_ready (icache_core_rsp_if.ready),
.core_rsp_valid (icache_rsp_if.valid),
.core_rsp_data (icache_rsp_if.data),
.core_rsp_tag (icache_rsp_if.tag),
.core_rsp_ready (icache_rsp_if.ready),
`UNUSED_PIN (core_rsp_tmask),
`ifdef PERF_ENABLE
@@ -149,20 +149,20 @@ module VX_mem_unit # (
.reset (dcache_reset),
// Core req
.core_req_valid (dcache_req_if.valid),
.core_req_rw (dcache_req_if.rw),
.core_req_byteen (dcache_req_if.byteen),
.core_req_addr (dcache_req_if.addr),
.core_req_data (dcache_req_if.data),
.core_req_tag (dcache_req_if.tag),
.core_req_ready (dcache_req_if.ready),
.core_req_valid (dcache_req_tmp_if.valid),
.core_req_rw (dcache_req_tmp_if.rw),
.core_req_byteen (dcache_req_tmp_if.byteen),
.core_req_addr (dcache_req_tmp_if.addr),
.core_req_data (dcache_req_tmp_if.data),
.core_req_tag (dcache_req_tmp_if.tag),
.core_req_ready (dcache_req_tmp_if.ready),
// Core response
.core_rsp_valid (dcache_rsp_if.valid),
.core_rsp_tmask (dcache_rsp_if.tmask),
.core_rsp_data (dcache_rsp_if.data),
.core_rsp_tag (dcache_rsp_if.tag),
.core_rsp_ready (dcache_rsp_if.ready),
.core_rsp_valid (dcache_rsp_tmp_if.valid),
.core_rsp_tmask (dcache_rsp_tmp_if.tmask),
.core_rsp_data (dcache_rsp_tmp_if.data),
.core_rsp_tag (dcache_rsp_tmp_if.tag),
.core_rsp_ready (dcache_rsp_tmp_if.ready),
`ifdef PERF_ENABLE
.perf_cache_if (perf_dcache_if),
@@ -185,13 +185,13 @@ module VX_mem_unit # (
);
if (`SM_ENABLE) begin
VX_dcache_core_req_if #(
VX_dcache_req_if #(
.NUM_REQS (`DNUM_REQS),
.WORD_SIZE (`DWORD_SIZE),
.CORE_TAG_WIDTH (`DCORE_TAG_WIDTH-`SM_ENABLE)
) smem_req_if();
VX_dcache_core_rsp_if #(
VX_dcache_rsp_if #(
.NUM_REQS (`DNUM_REQS),
.WORD_SIZE (`DWORD_SIZE),
.CORE_TAG_WIDTH (`DCORE_TAG_WIDTH-`SM_ENABLE)
@@ -201,13 +201,13 @@ module VX_mem_unit # (
.clk (clk),
.reset (reset),
.core_req_if (dcache_core_req_if),
.cache_req_if (dcache_req_if),
.core_req_if (dcache_req_if),
.cache_req_if (dcache_req_tmp_if),
.smem_req_if (smem_req_if),
.cache_rsp_if (dcache_rsp_if),
.cache_rsp_if (dcache_rsp_tmp_if),
.smem_rsp_if (smem_rsp_if),
.core_rsp_if (dcache_core_rsp_if)
.core_rsp_if (dcache_rsp_if)
);
`RESET_RELAY (smem_reset);
@@ -249,19 +249,19 @@ module VX_mem_unit # (
);
end else begin
// core to D-cache request
assign dcache_req_if.valid = dcache_core_req_if.valid;
assign dcache_req_if.addr = dcache_core_req_if.addr;
assign dcache_req_if.rw = dcache_core_req_if.rw;
assign dcache_req_if.byteen = dcache_core_req_if.byteen;
assign dcache_req_if.data = dcache_core_req_if.data;
assign dcache_req_if.tag = dcache_core_req_if.tag;
assign dcache_core_req_if.ready = dcache_req_if.ready;
assign dcache_req_tmp_if.valid = dcache_req_if.valid;
assign dcache_req_tmp_if.addr = dcache_req_if.addr;
assign dcache_req_tmp_if.rw = dcache_req_if.rw;
assign dcache_req_tmp_if.byteen = dcache_req_if.byteen;
assign dcache_req_tmp_if.data = dcache_req_if.data;
assign dcache_req_tmp_if.tag = dcache_req_if.tag;
assign dcache_req_tmp_if.ready = dcache_req_if.ready;
// D-cache to core reponse
assign dcache_core_rsp_if.valid = dcache_rsp_if.valid;
assign dcache_core_rsp_if.tag = dcache_rsp_if.tag;
assign dcache_core_rsp_if.data = dcache_rsp_if.data;
assign dcache_rsp_if.ready = dcache_core_rsp_if.ready;
assign dcache_rsp_if.valid = dcache_rsp_tmp_if.valid;
assign dcache_rsp_if.tag = dcache_rsp_tmp_if.tag;
assign dcache_rsp_if.data = dcache_rsp_tmp_if.data;
assign dcache_rsp_if.ready = dcache_rsp_tmp_if.ready;
end
wire [`DMEM_TAG_WIDTH-1:0] icache_mem_req_tag = `DMEM_TAG_WIDTH'(icache_mem_req_if.tag);