memory interface refactoring

2021-07-20 21:06:55 -07:00
parent 80cf1f26f9
commit d3b788784a
14 changed files with 144 additions and 144 deletions
--- a/hw/rtl/VX_lsu_unit.v
+++ b/hw/rtl/VX_lsu_unit.v
@@ -9,8 +9,8 @@ module VX_lsu_unit #(
    input wire reset,

   // Dcache interface
-    VX_dcache_core_req_if dcache_req_if,
-    VX_dcache_core_rsp_if dcache_rsp_if,
+    VX_dcache_req_if dcache_req_if,
+    VX_dcache_rsp_if dcache_rsp_if,

    // inputs
    VX_lsu_req_if   lsu_req_if,