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round robin arbiter + auto buffered queue + fixed dcache arbiter

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This commit is contained in:
Blaise Tine
2020-06-20 17:56:04 -04:00
parent 9c157e4929
commit d3440de403
30 changed files with 339 additions and 209 deletions
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20
hw/rtl/cache/VX_bank.v vendored
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@@ -192,13 +192,13 @@ module VX_bank #(
wire [`WORD_WIDTH-1:0] reqq_req_writeword_st0;
wire [CORE_TAG_WIDTH-1:0] reqq_req_tag_st0;
VX_cache_req_queue #(
VX_bank_core_req_arb #(
.WORD_SIZE (WORD_SIZE),
.NUM_REQUESTS (NUM_REQUESTS),
.CREQ_SIZE (CREQ_SIZE),
.CORE_TAG_WIDTH (CORE_TAG_WIDTH),
.CORE_TAG_ID_BITS (CORE_TAG_ID_BITS)
) req_queue (
) core_req_arb (
.clk (clk),
.reset (reset),
// Enqueue
@@ -722,25 +722,25 @@ module VX_bank #(
`ifdef DBG_PRINT_CACHE_BANK
always @(posedge clk) begin
if ((|core_req_valid) && core_req_ready) begin
$display("%t: bank%0d-%0d core req: addr=%0h, tag=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(core_req_addr, BANK_ID), core_req_tag);
$display("%t: bank%0d:%0d core req: addr=%0h, tag=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(core_req_addr[0], BANK_ID), core_req_tag);
end
if (core_rsp_valid && core_rsp_ready) begin
$display("%t: bank%0d-%0d core rsp: tag=%0h, data=%0h", $time, CACHE_ID, BANK_ID, core_rsp_tag, core_rsp_data);
$display("%t: bank%0d:%0d core rsp: tag=%0h, data=%0h", $time, CACHE_ID, BANK_ID, core_rsp_tag, core_rsp_data);
end
if (dram_fill_req_valid && dram_fill_req_ready) begin
$display("%t: bank%0d-%0d dram_fill req: addr=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_fill_req_addr, BANK_ID));
$display("%t: bank%0d:%0d dram_fill req: addr=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_fill_req_addr, BANK_ID));
end
if (dram_wb_req_firevalid && dram_wb_req_ready) begin
$display("%t: bank%0d-%0d dram_wb req: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_wb_req_addr, BANK_ID), dram_wb_req_data);
if (dram_wb_req_valid && dram_wb_req_ready) begin
$display("%t: bank%0d:%0d dram_wb req: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_wb_req_addr, BANK_ID), dram_wb_req_data);
end
if (dram_fill_rsp_valid && dram_fill_rsp_ready) begin
$display("%t: bank%0d-%0d dram_fill rsp: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_fill_rsp_addr, BANK_ID), dram_fill_rsp_data);
$display("%t: bank%0d:%0d dram_fill rsp: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_fill_rsp_addr, BANK_ID), dram_fill_rsp_data);
end
if (snp_req_valid && snp_req_ready) begin
$display("%t: bank%0d-%0d snp req: addr=%0h, invalidate=%0d, tag=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(snp_req_addr, BANK_ID), snp_req_invalidate, snp_req_tag);
$display("%t: bank%0d:%0d snp req: addr=%0h, invalidate=%0d, tag=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(snp_req_addr, BANK_ID), snp_req_invalidate, snp_req_tag);
end
if (snp_rsp_valid && snp_rsp_ready) begin
$display("%t: bank%0d-%0d snp rsp: tag=%0h", $time, CACHE_ID, BANK_ID, snp_rsp_tag);
$display("%t: bank%0d:%0d snp rsp: tag=%0h", $time, CACHE_ID, BANK_ID, snp_rsp_tag);
end
end
`endif

13
hw/rtl/cache/VX_cache_req_queue.v → hw/rtl/cache/VX_bank_core_req_arb.v vendored
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@@ -1,6 +1,6 @@
`include "VX_cache_config.vh"
module VX_cache_req_queue #(
module VX_bank_core_req_arb #(
// Size of a word in bytes
parameter WORD_SIZE = 0,
// Number of Word requests per cycle {1, 2, 4, 8, ...}
@@ -95,12 +95,15 @@ module VX_cache_req_queue #(
wire[`REQS_BITS-1:0] qual_request_index;
wire qual_has_request;
VX_generic_priority_encoder #(
VX_fixed_arbiter #(
.N(NUM_REQUESTS)
) sel_bank (
.valids(qual_valids),
.index (qual_request_index),
.found (qual_has_request)
.clk (clk),
.reset (reset),
.requests (qual_valids),
.grant_index (qual_request_index),
.grant_valid (qual_has_request),
`UNUSED_PIN (grant_onehot)
);
assign reqq_empty = !qual_has_request;

15
hw/rtl/cache/VX_cache.v vendored
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@@ -458,22 +458,26 @@ module VX_cache #(
.CORE_TAG_WIDTH (CORE_TAG_WIDTH),
.CORE_TAG_ID_BITS (CORE_TAG_ID_BITS)
) cache_core_rsp_merge (
.clk (clk),
.reset (reset),
.per_bank_core_rsp_tid (per_bank_core_rsp_tid),
.per_bank_core_rsp_valid (per_bank_core_rsp_valid),
.per_bank_core_rsp_data (per_bank_core_rsp_data),
.per_bank_core_rsp_tag (per_bank_core_rsp_tag),
.per_bank_core_rsp_ready (per_bank_core_rsp_ready),
.core_rsp_valid (core_rsp_valid),
.core_rsp_data (core_rsp_data),
.core_rsp_tag (core_rsp_tag),
.core_rsp_ready (core_rsp_ready)
.core_rsp_valid (core_rsp_valid),
.core_rsp_data (core_rsp_data),
.core_rsp_tag (core_rsp_tag),
.core_rsp_ready (core_rsp_ready)
);
VX_snp_rsp_arb #(
.NUM_BANKS (NUM_BANKS),
.BANK_LINE_SIZE (BANK_LINE_SIZE),
.SNP_REQ_TAG_WIDTH (SNP_REQ_TAG_WIDTH)
) snp_rsp_arb (
) snp_rsp_arb (
.clk (clk),
.reset (reset),
.per_bank_snp_rsp_valid (per_bank_snp_rsp_valid),
.per_bank_snp_rsp_tag (per_bank_snp_rsp_tag),
.per_bank_snp_rsp_ready (per_bank_snp_rsp_ready),
@@ -486,6 +490,5 @@ module VX_cache #(
`SCOPE_ASSIGN(scope_idram_req_ready, dram_fill_req_ready);
`SCOPE_ASSIGN(scope_idram_rsp_valid, per_bank_core_rsp_valid[0]);
`SCOPE_ASSIGN(scope_idram_rsp_ready, per_bank_core_rsp_ready[0]);
endmodule

2
hw/rtl/cache/VX_cache_config.vh vendored
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@@ -72,6 +72,6 @@
`define LINE_TO_DRAM_ADDR(x, i) {x, `BANK_SELECT_BITS'(i)}
`define LINE_TO_BYTE_ADDR(x, i) {x, (((`BANK_SELECT_BITS + `BASE_ADDR_BITS)'(i)) << `BASE_ADDR_BITS)}
`define LINE_TO_BYTE_ADDR(x, i) {x, (32-$bits(x))'(i << (32-$bits(x)-`BANK_SELECT_BITS))}
`endif

14
hw/rtl/cache/VX_cache_core_rsp_merge.v vendored
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@@ -12,6 +12,9 @@ module VX_cache_core_rsp_merge #(
// size of tag id in core request tag
parameter CORE_TAG_ID_BITS = 0
) (
input wire clk,
input wire reset,
// Per Bank WB
input wire [NUM_BANKS-1:0][`REQS_BITS-1:0] per_bank_core_rsp_tid,
input wire [NUM_BANKS-1:0] per_bank_core_rsp_valid,
@@ -32,12 +35,15 @@ module VX_cache_core_rsp_merge #(
wire [`BANK_BITS-1:0] main_bank_index;
VX_generic_priority_encoder #(
VX_fixed_arbiter #(
.N(NUM_BANKS)
) sel_bank (
.valids(per_bank_core_rsp_valid),
.index (main_bank_index),
`UNUSED_PIN (found)
.clk (clk),
.reset (reset),
.requests (per_bank_core_rsp_valid),
.grant_index (main_bank_index),
`UNUSED_PIN (grant_valid),
`UNUSED_PIN (grant_onehot)
);
integer i;

13
hw/rtl/cache/VX_cache_dfq_queue.v → hw/rtl/cache/VX_cache_dram_fill_arb.v vendored
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@@ -1,6 +1,6 @@
`include "VX_cache_config.vh"
module VX_cache_dfq_queue #(
module VX_cache_dram_fill_arb #(
// Size of line inside a bank in bytes
parameter BANK_LINE_SIZE = 0,
// Number of banks {1, 2, 4, 8,...}
@@ -60,12 +60,15 @@ module VX_cache_dfq_queue #(
wire[`BANK_BITS-1:0] qual_request_index;
wire qual_has_request;
VX_generic_priority_encoder #(
VX_fixed_arbiter #(
.N(NUM_BANKS)
) sel_bank (
.valids(use_per_bqual_bank_dram_fill_req_valid),
.index (qual_request_index),
.found (qual_has_request)
.clk (clk),
.reset (reset),
.requests (use_per_bqual_bank_dram_fill_req_valid),
.grant_index (qual_request_index),
.grant_valid (qual_has_request),
`UNUSED_PIN (grant_onehot)
);
assign dfqq_empty = !qual_has_request;

15
hw/rtl/cache/VX_cache_dram_req_arb.v vendored
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@@ -74,11 +74,11 @@ module VX_cache_dram_req_arb #(
wire dfqq_push = (| per_bank_dram_fill_req_valid);
wire dfqq_full;
VX_cache_dfq_queue #(
VX_cache_dram_fill_arb #(
.BANK_LINE_SIZE(BANK_LINE_SIZE),
.NUM_BANKS(NUM_BANKS),
.DFQQ_SIZE(DFQQ_SIZE)
) cache_dfq_queue (
) dram_fill_arb (
.clk (clk),
.reset (reset),
.dfqq_push (dfqq_push),
@@ -95,12 +95,15 @@ module VX_cache_dram_req_arb #(
wire [`BANK_BITS-1:0] dwb_bank;
VX_generic_priority_encoder #(
VX_fixed_arbiter #(
.N(NUM_BANKS)
) sel_dwb (
.valids(per_bank_dram_wb_req_valid),
.index (dwb_bank),
.found (dwb_valid)
.clk (clk),
.reset (reset),
.requests (per_bank_dram_wb_req_valid),
.grant_index (dwb_bank),
.grant_valid (dwb_valid),
`UNUSED_PIN (grant_onehot)
);
genvar i;

4
hw/rtl/cache/VX_cache_miss_resrv.v vendored
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@@ -81,7 +81,7 @@ module VX_cache_miss_resrv #(
genvar i;
generate
for (i = 0; i < MRVQ_SIZE; i++) begin
assign valid_address_match[i] = valid_table[i] && (addr_table[i] === fill_addr_st1);
assign valid_address_match[i] = valid_table[i] ? (addr_table[i] == fill_addr_st1) : 0;
assign make_ready[i] = is_fill_st1 && valid_address_match[i];
end
endgenerate
@@ -155,7 +155,7 @@ module VX_cache_miss_resrv #(
integer j;
always @(posedge clk) begin
if (mrvq_push || mrvq_pop || increment_head || recover_state) begin
$write("%t: bank%0d-%0d msrq: push=%b pop=%b incr=%d recv=%d", $time, CACHE_ID, BANK_ID, mrvq_push, mrvq_pop, increment_head, recover_state);
$write("%t: bank%0d:%0d msrq: push=%b pop=%b incr=%d recv=%d", $time, CACHE_ID, BANK_ID, mrvq_push, mrvq_pop, increment_head, recover_state);
for (j = 0; j < MRVQ_SIZE; j++) begin
if (valid_table[j]) begin
$write(" ");

24
hw/rtl/cache/VX_snp_forwarder.v vendored
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@@ -40,8 +40,7 @@ module VX_snp_forwarder #(
`STATIC_ASSERT(NUM_REQUESTS > 1, "invalid value");
reg [`REQS_BITS:0] pending_cntrs [SNRQ_SIZE-1:0];
reg [`REQS_BITS-1:0] fwdin_sel;
wire [`LOG2UP(SNRQ_SIZE)-1:0] sfq_write_addr, sfq_read_addr, dbg_sfq_write_addr;
wire sfq_push, sfq_pop, sfq_full;
@@ -100,13 +99,18 @@ module VX_snp_forwarder #(
assign snp_req_ready = !sfq_full && fwdout_ready;
always @(posedge clk) begin
if (reset) begin
fwdin_sel <= 0;
end else if (NUM_REQUESTS > 1) begin
fwdin_sel <= fwdin_sel + 1;
end
end
reg [`REQS_BITS-1:0] fwdin_sel;
VX_fixed_arbiter #(
.N(NUM_REQUESTS)
) arbiter (
.clk (clk),
.reset (reset),
.requests (snp_fwdin_valid),
.grant_index (fwdin_sel),
`UNUSED_PIN (grant_valid),
`UNUSED_PIN (grant_onehot)
);
assign fwdin_valid = snp_fwdin_valid[fwdin_sel];
assign fwdin_tag = snp_fwdin_tag[fwdin_sel];
@@ -124,7 +128,7 @@ module VX_snp_forwarder #(
$display("%t: cache%0d snp fwd_out: addr=%0h, invalidate=%0d, tag=%0h", $time, CACHE_ID, `DRAM_TO_BYTE_ADDR(snp_fwdout_addr[0]), snp_fwdout_invalidate[0], snp_fwdout_tag[0]);
end
if (fwdin_valid && fwdin_ready) begin
$display("%t: cache%0d snp fwd_in[%01d]: tag=%0h", $time, CACHE_ID, fwdin_sel, fwdin_tag);
$display("%t: cache%0d snp fwd_in[%0d]: tag=%0h", $time, CACHE_ID, fwdin_sel, fwdin_tag);
end
if (snp_rsp_valid && snp_rsp_ready) begin
$display("%t: cache%0d snp rsp: addr=%0h, invalidate=%0d, tag=%0h", $time, CACHE_ID, snp_rsp_addr, snp_rsp_invalidate, snp_rsp_tag);

14
hw/rtl/cache/VX_snp_rsp_arb.v vendored
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@@ -5,6 +5,9 @@ module VX_snp_rsp_arb #(
parameter BANK_LINE_SIZE = 0,
parameter SNP_REQ_TAG_WIDTH = 0
) (
input wire clk,
input wire reset,
input wire [NUM_BANKS-1:0] per_bank_snp_rsp_valid,
input wire [NUM_BANKS-1:0][SNP_REQ_TAG_WIDTH-1:0] per_bank_snp_rsp_tag,
output wire [NUM_BANKS-1:0] per_bank_snp_rsp_ready,
@@ -17,12 +20,15 @@ module VX_snp_rsp_arb #(
wire [`BANK_BITS-1:0] fsq_bank;
wire fsq_valid;
VX_generic_priority_encoder #(
VX_fixed_arbiter #(
.N(NUM_BANKS)
) sel_ffsq (
.valids (per_bank_snp_rsp_valid),
.index (fsq_bank),
.found (fsq_valid)
.clk (clk),
.reset (reset),
.requests (per_bank_snp_rsp_valid),
.grant_index (fsq_bank),
.grant_valid (fsq_valid),
`UNUSED_PIN (grant_onehot)
);
assign snp_rsp_valid = fsq_valid;

7
hw/rtl/cache/VX_tag_data_access.v vendored
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@@ -77,9 +77,8 @@ module VX_tag_data_access #(
wire invalidate_line;
wire tags_match;
wire real_writefill = writefill_st1e
&& ((valid_req_st1e && !use_read_valid_st1e)
|| (valid_req_st1e && use_read_valid_st1e && !tags_match));
wire real_writefill = valid_req_st1e && writefill_st1e
&& ((!use_read_valid_st1e) || (use_read_valid_st1e && !tags_match));
wire[`TAG_SELECT_BITS-1:0] writetag_st1e = writeaddr_st1e[`TAG_LINE_ADDR_RNG];
wire[`LINE_SELECT_BITS-1:0] writeladdr_st1e = writeaddr_st1e[`LINE_SELECT_BITS-1:0];
@@ -173,7 +172,7 @@ module VX_tag_data_access #(
assign use_write_data = data_write;
// use "case equality" to handle uninitialized tag when block entry is not valid
assign tags_match = ((writetag_st1e == use_read_tag_st1e) === 1'b1);
assign tags_match = (writetag_st1e === use_read_tag_st1e);
wire snoop_hit_no_pending = valid_req_st1e && is_snp_st1e && use_read_valid_st1e && tags_match && (use_read_dirty_st1e || snp_invalidate_st1e) && !force_request_miss_st1e;
wire req_invalid = valid_req_st1e && !is_snp_st1e && !use_read_valid_st1e && !writefill_st1e;