round robin arbiter + auto buffered queue + fixed dcache arbiter
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@@ -261,17 +261,18 @@ module Vortex #(
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.icache_dram_rsp_if (icache_dram_rsp_if)
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);
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// use "case equality" to handle uninitialized address value
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wire io_select = (({core_dcache_req_if.core_req_addr[0], 2'b0} >= `IO_BUS_BASE_ADDR) === 1'b1);
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// select io address
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wire is_io_addr = ({core_dcache_req_if.core_req_addr[0], 2'b0} >= `IO_BUS_BASE_ADDR);
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wire io_select = (| core_dcache_req_if.core_req_valid) ? is_io_addr : 0;
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VX_dcache_arb dcache_io_arb (
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.io_select (io_select),
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.core_req_if (core_dcache_req_if),
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.core_dcache_req_if (arb_dcache_req_if),
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.core_io_req_if (arb_io_req_if),
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.core_dcache_rsp_if (arb_dcache_rsp_if),
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.core_io_rsp_if (arb_io_rsp_if),
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.core_rsp_if (core_dcache_rsp_if)
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.req_select (io_select),
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.in_core_req_if (core_dcache_req_if),
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.out0_core_req_if (arb_dcache_req_if),
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.out1_core_req_if (arb_io_req_if),
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.in0_core_rsp_if (arb_dcache_rsp_if),
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.in1_core_rsp_if (arb_io_rsp_if),
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.out_core_rsp_if (core_dcache_rsp_if)
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);
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endmodule // Vortex
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