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[debug] Elevate DEBUG_LEVEL for load/store; trace prefetch and fence

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This commit is contained in:
Hansung Kim
2023-09-26 11:44:20 -07:00
parent b97e94b8ed
commit d34177ea9c
1 changed files with 6 additions and 4 deletions
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10
sim/simx/execute.cpp
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@@ -691,7 +691,7 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
uint64_t mem_data = 0; uint64_t mem_data = 0;
core_->dcache_read(&mem_data, mem_addr, mem_bytes); core_->dcache_read(&mem_data, mem_addr, mem_bytes);
trace->mem_addrs.at(t).push_back({mem_addr, mem_bytes}); trace->mem_addrs.at(t).push_back({mem_addr, mem_bytes});
DP(1, "LOAD MEM: CYCLE=" << SimPlatform::instance().cycles() DP(2, "LOAD MEM: CYCLE=" << std::dec << SimPlatform::instance().cycles()
<< ", CORE=" << core_->id() << ", CORE=" << core_->id()
<< ", THREAD=" << t << ", THREAD=" << t
<< ", ADDRESS=0x" << std::hex << mem_addr << ", ADDRESS=0x" << std::hex << mem_addr
@@ -736,7 +736,7 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
core_->dcache_read(&mem_data, mem_addr, 4); core_->dcache_read(&mem_data, mem_addr, 4);
Word *result_ptr = (Word *)(vd.data() + i); Word *result_ptr = (Word *)(vd.data() + i);
*result_ptr = mem_data; *result_ptr = mem_data;
DP(1, "LOAD MEM: CYCLE=" << SimPlatform::instance().cycles() DP(2, "LOAD MEM: CYCLE=" << std::dec << SimPlatform::instance().cycles()
<< ", CORE=" << core_->id() << ", CORE=" << core_->id()
<< ", VLEN=" << vl_ << ", VLEN=" << vl_
<< ", VID=" << i << ", VID=" << i
@@ -773,7 +773,7 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
mem_data &= mask; mem_data &= mask;
} }
trace->mem_addrs.at(t).push_back({mem_addr, mem_bytes}); trace->mem_addrs.at(t).push_back({mem_addr, mem_bytes});
DP(1, "STORE MEM: CYCLE=" << SimPlatform::instance().cycles() DP(2, "STORE MEM: CYCLE=" << std::dec << SimPlatform::instance().cycles()
<< ", CORE=" << core_->id() << ", CORE=" << core_->id()
<< ", THREAD=" << t << ", THREAD=" << t
<< ", ADDRESS=0x" << std::hex << mem_addr << ", ADDRESS=0x" << std::hex << mem_addr
@@ -798,7 +798,7 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
// store word and unit strided (not checking for unit stride) // store word and unit strided (not checking for unit stride)
uint32_t mem_data = *(uint32_t *)(vreg_file_.at(instr.getVs3()).data() + i); uint32_t mem_data = *(uint32_t *)(vreg_file_.at(instr.getVs3()).data() + i);
core_->dcache_write(&mem_data, mem_addr, 4); core_->dcache_write(&mem_data, mem_addr, 4);
DP(1, "STORE MEM: CYCLE=" << SimPlatform::instance().cycles() DP(2, "STORE MEM: CYCLE=" << std::dec << SimPlatform::instance().cycles()
<< ", CORE=" << core_->id() << ", CORE=" << core_->id()
<< ", VLEN=" << vl_ << ", VLEN=" << vl_
<< ", VID=" << i << ", VID=" << i
@@ -900,6 +900,7 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
case FENCE: { case FENCE: {
trace->exe_type = ExeType::LSU; trace->exe_type = ExeType::LSU;
trace->lsu.type = LsuType::FENCE; trace->lsu.type = LsuType::FENCE;
DP(2, "FENCE MEM");
break; break;
} }
case FCI: { case FCI: {
@@ -1422,6 +1423,7 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
trace->exe_type = ExeType::LSU; trace->exe_type = ExeType::LSU;
trace->lsu.type = LsuType::PREFETCH; trace->lsu.type = LsuType::PREFETCH;
trace->used_iregs.set(rsrc0); trace->used_iregs.set(rsrc0);
DP(2, "PREFETCH MEM");
for (uint32_t t = 0; t < num_threads; ++t) { for (uint32_t t = 0; t < num_threads; ++t) {
if (!tmask_.test(t)) if (!tmask_.test(t))
continue; continue;