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minor update

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This commit is contained in:
Blaise Tine
2020-06-29 00:38:59 -07:00
parent 0b7a869470
commit d33916f1e0
4 changed files with 6 additions and 11 deletions
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5
driver/rtlsim/Makefile
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@@ -13,7 +13,7 @@ DBG_PRINT_FLAGS += -DDBG_PRINT_DRAM
DBG_PRINT_FLAGS += -DDBG_PRINT_PIPELINE DBG_PRINT_FLAGS += -DDBG_PRINT_PIPELINE
DBG_PRINT_FLAGS += -DDBG_PRINT_OPAE DBG_PRINT_FLAGS += -DDBG_PRINT_OPAE
DBG_FLAGS += $(DBG_PRINT_FLAGS) #DBG_FLAGS += $(DBG_PRINT_FLAGS)
DBG_FLAGS += -DDBG_CORE_REQ_INFO DBG_FLAGS += -DDBG_CORE_REQ_INFO
#CONFIGS += -DNUM_CLUSTERS=2 -DNUM_CORES=4 #CONFIGS += -DNUM_CLUSTERS=2 -DNUM_CORES=4
@@ -38,8 +38,7 @@ RTL_INCLUDE = -I../../hw/rtl -I../../hw/rtl/libs -I../../hw/rtl/interfaces -I../
VL_FLAGS += --language 1800-2009 --assert -Wall -Wpedantic $(CONFIGS) VL_FLAGS += --language 1800-2009 --assert -Wall -Wpedantic $(CONFIGS)
VL_FLAGS += -Wno-DECLFILENAME VL_FLAGS += -Wno-DECLFILENAME
VL_FLAGS += --x-initial unique VL_FLAGS += --x-initial unique --x-assign unique
VL_FLAGS += --x-assign unique
# Enable Verilator multithreaded simulation # Enable Verilator multithreaded simulation
#THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))') #THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))')

2
hw/rtl/VX_lsu_unit.v
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@@ -116,7 +116,7 @@ module VX_lsu_unit #(
end end
if (mrq_pop_part) begin if (mrq_pop_part) begin
mem_rsp_mask[mrq_read_addr] <= mem_rsp_mask_upd; mem_rsp_mask[mrq_read_addr] <= mem_rsp_mask_upd;
assert(mrq_read_addr == dbg_mrq_write_addr); assert(($time < 2) || mrq_read_addr == dbg_mrq_write_addr);
end end
end end

4
hw/simulate/Makefile
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@@ -12,7 +12,7 @@ DBG_PRINT_FLAGS += -DDBG_PRINT_DRAM
DBG_PRINT_FLAGS += -DDBG_PRINT_PIPELINE DBG_PRINT_FLAGS += -DDBG_PRINT_PIPELINE
DBG_PRINT_FLAGS += -DDBG_PRINT_OPAE DBG_PRINT_FLAGS += -DDBG_PRINT_OPAE
DBG_FLAGS += $(DBG_PRINT_FLAGS) #DBG_FLAGS += $(DBG_PRINT_FLAGS)
DBG_FLAGS += -DDBG_CORE_REQ_INFO DBG_FLAGS += -DDBG_CORE_REQ_INFO
INCLUDE = -I../rtl/ -I../rtl/libs -I../rtl/interfaces -I../rtl/pipe_regs -I../rtl/cache -I../rtl/simulate INCLUDE = -I../rtl/ -I../rtl/libs -I../rtl/interfaces -I../rtl/pipe_regs -I../rtl/cache -I../rtl/simulate
@@ -25,7 +25,7 @@ CF += -std=c++11 -fms-extensions -I../..
VF += --language 1800-2009 --assert -Wall -Wpedantic VF += --language 1800-2009 --assert -Wall -Wpedantic
VF += -Wno-DECLFILENAME VF += -Wno-DECLFILENAME
VF += --x-initial unique VF += --x-initial unique --x-assign unique
VF += -exe $(SRCS) $(INCLUDE) VF += -exe $(SRCS) $(INCLUDE)
DBG += -DVCD_OUTPUT $(DBG_FLAGS) DBG += -DVCD_OUTPUT $(DBG_FLAGS)

6
hw/simulate/simulator.cpp
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@@ -9,13 +9,9 @@ double sc_time_stamp() {
return timestamp; return timestamp;
} }
Simulator::Simulator() { Simulator::Simulator() {
#ifdef NDEBUG
// force random values for unitialized signals // force random values for unitialized signals
Verilated::randReset(2); Verilated::randReset(2);
Verilated::assertOn(false);
#endif
ram_ = nullptr; ram_ = nullptr;
vortex_ = new VVortex(); vortex_ = new VVortex();