sync
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@@ -101,29 +101,6 @@ module VX_decode(
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// wire[31:0] internal_rd1;
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// wire[31:0] internal_rd2;
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// always @(posedge clk) begin
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// $display("Decode: curr_pc: %h", in_curr_PC);
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// end
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genvar index;
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generate
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for (index=0; index < `NT; index=index+1)
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begin: gen_code_label
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VX_register_file vx_register_file(
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.clk(clk),
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.in_valid(in_wb_valid[index]),
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.in_write_register(write_register),
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.in_rd(in_rd),
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.in_data(in_write_data[index]),
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.in_src1(out_rs1),
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.in_src2(out_rs2),
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.out_src1_data(rd1_register[index]),
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.out_src2_data(rd2_register[index])
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);
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end
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endgenerate
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// VX_register_file vx_register_file_0(
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// .clk(clk),
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// .in_valid(in_wb_valid[0]),
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@@ -152,6 +129,36 @@ module VX_decode(
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assign out_valid = in_valid;
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assign write_register = (in_wb != 2'h0) ? (1'b1) : (1'b0);
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always @(posedge clk) begin
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$display("Decode: curr_pc: %h", in_curr_PC);
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end
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genvar index;
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generate
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for (index=0; index < `NT; index=index+1)
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begin: gen_code_label
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VX_register_file vx_register_file(
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.clk(clk),
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.in_valid(in_wb_valid[index]),
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.in_write_register(write_register),
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.in_rd(in_rd),
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.in_data(in_write_data[index]),
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.in_src1(out_rs1),
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.in_src2(out_rs2),
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.out_src1_data(rd1_register[index]),
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.out_src2_data(rd2_register[index])
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);
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end
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endgenerate
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assign curr_opcode = in_instruction[6:0];
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