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minor update

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This commit is contained in:
Blaise Tine
2020-05-21 13:42:08 -04:00
parent d12c40131e
commit cf22ef2bf3
16 changed files with 82 additions and 92 deletions
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4
driver/rtlsim/Makefile
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@@ -30,6 +30,7 @@ SRCS = vortex.cpp ../common/vx_utils.cpp ../../hw/simulate/simulator.cpp
RTL_INCLUDE = -I../../hw/rtl -I../../hw/rtl/libs -I../../hw/rtl/interfaces -I../../hw/rtl/pipe_regs -I../../hw/rtl/cache RTL_INCLUDE = -I../../hw/rtl -I../../hw/rtl/libs -I../../hw/rtl/interfaces -I../../hw/rtl/pipe_regs -I../../hw/rtl/cache
VL_FLAGS += --language 1800-2009 --assert -Wall -Wpedantic $(MULTICORE) VL_FLAGS += --language 1800-2009 --assert -Wall -Wpedantic $(MULTICORE)
VL_FLAGS += -Wno-DECLFILENAME
# Use 64 bytes DRAM blocks # Use 64 bytes DRAM blocks
CFLAGS += -DGLOBAL_BLOCK_SIZE=64 CFLAGS += -DGLOBAL_BLOCK_SIZE=64
@@ -37,6 +38,9 @@ VL_FLAGS += -DGLOBAL_BLOCK_SIZE=64
VL_FLAGS += --x-initial unique VL_FLAGS += --x-initial unique
VL_FLAGS += -DDPRFQ_SIZE=0 -DIPRFQ_SIZE=0 -DSPRFQ_SIZE=0 -DL2PRFQ_SIZE=0 -DL3PRFQ_SIZE=0
VL_FLAGS += -DDFILL_INVALIDAOR_SIZE=0 -DIFILL_INVALIDAOR_SIZE=0 -DSFILL_INVALIDAOR_SIZE=0 -DL2FILL_INVALIDAOR_SIZE=0 -DL3FILL_INVALIDAOR_SIZE=0
# Enable Verilator multithreaded simulation # Enable Verilator multithreaded simulation
#THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))') #THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))')
#VL_FLAGS += --threads $(THREADS) #VL_FLAGS += --threads $(THREADS)

1
hw/Makefile
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@@ -3,6 +3,7 @@ all: build-s
CF += -std=c++11 -fms-extensions CF += -std=c++11 -fms-extensions
VF += --language 1800-2009 --assert -Wall -Wpedantic VF += --language 1800-2009 --assert -Wall -Wpedantic
VF += -Wno-DECLFILENAME
VF += -exe $(SRCS) $(INCLUDE) VF += -exe $(SRCS) $(INCLUDE)

4
hw/rtl/VX_define.vh
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@@ -22,6 +22,10 @@
/* verilator lint_on PINCONNECTEMPTY */ \ /* verilator lint_on PINCONNECTEMPTY */ \
/* verilator lint_on DECLFILENAME */ /* verilator lint_on DECLFILENAME */
`define UNUSED_VAR(x) /* verilator lint_off UNUSED */ \
wire [$bits(x)-1:0] __``x``__ = x; \
/* verilator lint_on UNUSED */
`define UNUSED_PIN(x) /* verilator lint_off PINCONNECTEMPTY */ \ `define UNUSED_PIN(x) /* verilator lint_off PINCONNECTEMPTY */ \
. x () \ . x () \
/* verilator lint_on PINCONNECTEMPTY */ /* verilator lint_on PINCONNECTEMPTY */

10
hw/rtl/Vortex_Cluster.v
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@@ -115,11 +115,9 @@ module Vortex_Cluster #(
.D_dram_rsp_data (per_core_D_dram_rsp_data [i]), .D_dram_rsp_data (per_core_D_dram_rsp_data [i]),
.D_dram_rsp_tag (per_core_D_dram_rsp_tag [i]), .D_dram_rsp_tag (per_core_D_dram_rsp_tag [i]),
.D_dram_rsp_ready (per_core_D_dram_rsp_ready [i]), .D_dram_rsp_ready (per_core_D_dram_rsp_ready [i]),
.I_dram_req_read (per_core_I_dram_req_read [i]),
`IGNORE_WARNINGS_BEGIN .I_dram_req_read (per_core_I_dram_req_read [i]),
.I_dram_req_write (), `UNUSED_PIN (I_dram_req_write),
`IGNORE_WARNINGS_END
.I_dram_req_addr (per_core_I_dram_req_addr [i]), .I_dram_req_addr (per_core_I_dram_req_addr [i]),
.I_dram_req_data (per_core_I_dram_req_data [i]), .I_dram_req_data (per_core_I_dram_req_data [i]),
.I_dram_req_tag (per_core_I_dram_req_tag [i]), .I_dram_req_tag (per_core_I_dram_req_tag [i]),
@@ -401,10 +399,8 @@ module Vortex_Cluster #(
.snp_req_ready (snp_req_ready), .snp_req_ready (snp_req_ready),
.snp_rsp_valid (snp_rsp_valid), .snp_rsp_valid (snp_rsp_valid),
`UNUSED_PIN (snp_rsp_addr),
.snp_rsp_tag (snp_rsp_tag), .snp_rsp_tag (snp_rsp_tag),
`IGNORE_WARNINGS_BEGIN
.snp_rsp_addr (),
`IGNORE_WARNINGS_END
.snp_rsp_ready (snp_rsp_ready), .snp_rsp_ready (snp_rsp_ready),
.snp_fwdout_valid (arb_snp_fwdout_valid), .snp_fwdout_valid (arb_snp_fwdout_valid),

2
hw/rtl/cache/VX_bank.v vendored
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@@ -113,7 +113,6 @@ module VX_bank #(
wire[2:0] debug_mem_write_st0; wire[2:0] debug_mem_write_st0;
wire[`REQS_BITS-1:0] debug_tid_st0; wire[`REQS_BITS-1:0] debug_tid_st0;
wire[31:0] debug_use_pc_st1e; wire[31:0] debug_use_pc_st1e;
wire[1:0] debug_wb_st1e; wire[1:0] debug_wb_st1e;
wire[4:0] debug_rd_st1e; wire[4:0] debug_rd_st1e;
@@ -122,7 +121,6 @@ module VX_bank #(
wire[2:0] debug_mem_write_st1e; wire[2:0] debug_mem_write_st1e;
wire[`REQS_BITS-1:0] debug_tid_st1e; wire[`REQS_BITS-1:0] debug_tid_st1e;
wire[31:0] debug_use_pc_st2; wire[31:0] debug_use_pc_st2;
wire[1:0] debug_wb_st2; wire[1:0] debug_wb_st2;
wire[4:0] debug_rd_st2; wire[4:0] debug_rd_st2;

9
hw/rtl/cache/VX_fill_invalidator.v vendored
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@@ -10,12 +10,9 @@ module VX_fill_invalidator #(
) ( ) (
input wire clk, input wire clk,
input wire reset, input wire reset,
input wire possible_fill, input wire possible_fill,
input wire success_fill, input wire success_fill,
input wire[`LINE_ADDR_WIDTH-1:0] fill_addr, input wire[`LINE_ADDR_WIDTH-1:0] fill_addr,
output reg invalidate_fill output reg invalidate_fill
); );
@@ -23,6 +20,12 @@ module VX_fill_invalidator #(
assign invalidate_fill = 0; assign invalidate_fill = 0;
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
`UNUSED_VAR (possible_fill)
`UNUSED_VAR (success_fill)
`UNUSED_VAR (fill_addr)
end else begin end else begin
reg [FILL_INVALIDAOR_SIZE-1:0] fills_active; reg [FILL_INVALIDAOR_SIZE-1:0] fills_active;

13
hw/rtl/libs/VX_divide.v
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@@ -27,9 +27,7 @@ module VX_divide #(
generate generate
if (NREP != DREP) begin if (NREP != DREP) begin
`IGNORE_WARNINGS_BEGIN
different_nrep_drep_not_yet_supported non_existing_module(); different_nrep_drep_not_yet_supported non_existing_module();
`IGNORE_WARNINGS_END
end end
if (IMPL == "quartus") begin if (IMPL == "quartus") begin
@@ -58,6 +56,7 @@ module VX_divide #(
wire [WIDTHN-1:0] numer_pipe_end; wire [WIDTHN-1:0] numer_pipe_end;
wire [WIDTHD-1:0] denom_pipe_end; wire [WIDTHD-1:0] denom_pipe_end;
if (PIPELINE == 0) begin if (PIPELINE == 0) begin
assign numer_pipe_end = numer; assign numer_pipe_end = numer;
assign denom_pipe_end = denom; assign denom_pipe_end = denom;
@@ -100,16 +99,6 @@ module VX_divide #(
if (NREP == "SIGNED") begin if (NREP == "SIGNED") begin
/*VX_divide_ifnal_signed #(
.WIDTHN,
.WIDTHD
)div(
.numer(numer_pipe_end),
.denom(denom_pipe_end),
.quotient,
.remainder
);*/
always @(*) begin always @(*) begin
if (denom_pipe_end == 0) begin if (denom_pipe_end == 0) begin
quotient = 32'hffffffff; quotient = 32'hffffffff;

14
hw/rtl/libs/VX_generic_queue.v
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@@ -5,25 +5,29 @@ module VX_generic_queue #(
parameter SIZE = 16, parameter SIZE = 16,
parameter BUFFERED_OUTPUT = 1 parameter BUFFERED_OUTPUT = 1
) ( ) (
`IGNORE_WARNINGS_BEGIN
input wire clk, input wire clk,
input wire reset, input wire reset,
input wire push, input wire push,
input wire pop, input wire pop,
output wire empty,
output wire full,
`IGNORE_WARNINGS_END
input wire [DATAW-1:0] data_in, input wire [DATAW-1:0] data_in,
output wire [DATAW-1:0] data_out, output wire [DATAW-1:0] data_out,
output wire empty,
output wire full,
output wire [`LOG2UP(SIZE+1)-1:0] size output wire [`LOG2UP(SIZE+1)-1:0] size
); );
if (SIZE == 0) begin if (SIZE == 0) begin
assign empty = 1; assign empty = 1;
assign data_out = data_in; assign data_out = 0;
assign full = 0; assign full = 0;
assign size = 0; assign size = 0;
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
`UNUSED_VAR (push)
`UNUSED_VAR (pop)
`UNUSED_VAR (data_in)
end else begin // (SIZE > 0) end else begin // (SIZE > 0)
`ifdef QUEUE_FORCE_MLAB `ifdef QUEUE_FORCE_MLAB

10
hw/rtl/libs/VX_generic_register.v
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@@ -4,20 +4,13 @@ module VX_generic_register #(
parameter N, parameter N,
parameter PassThru = 0 parameter PassThru = 0
) ( ) (
`IGNORE_WARNINGS_BEGIN
input wire clk, input wire clk,
input wire reset, input wire reset,
input wire stall, input wire stall,
input wire flush, input wire flush,
`IGNORE_WARNINGS_END
input wire[N-1:0] in, input wire[N-1:0] in,
output wire[N-1:0] out output wire[N-1:0] out
); );
if (PassThru) begin
assign out = in;
end else begin
reg [(N-1):0] value; reg [(N-1):0] value;
always @(posedge clk) begin always @(posedge clk) begin
@@ -30,7 +23,6 @@ module VX_generic_register #(
end end
end end
assign out = value; assign out = PassThru ? in : value;
end
endmodule endmodule

3
hw/rtl/libs/VX_mult.v
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@@ -34,7 +34,6 @@ module VX_mult #(
localparam lpm_speed = (SPEED == "HIGHEST") ? 10 : 5; localparam lpm_speed = (SPEED == "HIGHEST") ? 10 : 5;
if (FORCE_LE == "YES") begin if (FORCE_LE == "YES") begin
`IGNORE_WARNINGS_BEGIN
lpm_mult #( lpm_mult #(
.LPM_WIDTHA(WIDTHA), .LPM_WIDTHA(WIDTHA),
.LPM_WIDTHB(WIDTHB), .LPM_WIDTHB(WIDTHB),
@@ -51,7 +50,6 @@ module VX_mult #(
.datab(datab), .datab(datab),
.result(result) .result(result)
); );
`IGNORE_WARNINGS_END
end end
else begin else begin
lpm_mult#( lpm_mult#(
@@ -76,6 +74,7 @@ module VX_mult #(
wire [WIDTHA-1:0] dataa_pipe_end; wire [WIDTHA-1:0] dataa_pipe_end;
wire [WIDTHB-1:0] datab_pipe_end; wire [WIDTHB-1:0] datab_pipe_end;
if (PIPELINE == 0) begin if (PIPELINE == 0) begin
assign dataa_pipe_end = dataa; assign dataa_pipe_end = dataa;
assign datab_pipe_end = datab; assign datab_pipe_end = datab;