minor update
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@@ -27,9 +27,7 @@ module VX_divide #(
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generate
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if (NREP != DREP) begin
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`IGNORE_WARNINGS_BEGIN
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different_nrep_drep_not_yet_supported non_existing_module();
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`IGNORE_WARNINGS_END
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end
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if (IMPL == "quartus") begin
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@@ -58,6 +56,7 @@ module VX_divide #(
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wire [WIDTHN-1:0] numer_pipe_end;
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wire [WIDTHD-1:0] denom_pipe_end;
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if (PIPELINE == 0) begin
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assign numer_pipe_end = numer;
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assign denom_pipe_end = denom;
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@@ -100,16 +99,6 @@ module VX_divide #(
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if (NREP == "SIGNED") begin
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/*VX_divide_ifnal_signed #(
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.WIDTHN,
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.WIDTHD
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)div(
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.numer(numer_pipe_end),
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.denom(denom_pipe_end),
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.quotient,
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.remainder
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);*/
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always @(*) begin
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if (denom_pipe_end == 0) begin
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quotient = 32'hffffffff;
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@@ -118,12 +107,12 @@ module VX_divide #(
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else if (denom_pipe_end == 32'hffffffff && numer_pipe_end == 32'h80000000) begin
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// this edge case kills verilator in some cases by causing a division
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// overflow exception. INT_MIN / -1 (on x86)
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quotient = 0;
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quotient = 0;
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remainder = 0;
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end
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else begin
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quotient = $signed($signed(numer_pipe_end)/$signed(denom_pipe_end));
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remainder = $signed($signed(numer_pipe_end)%$signed(denom_pipe_end));
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quotient = $signed($signed(numer_pipe_end) / $signed(denom_pipe_end));
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remainder = $signed($signed(numer_pipe_end) % $signed(denom_pipe_end));
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end
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end
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